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8
new_project_rtl_template/sim/_file_vhd.f
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8
new_project_rtl_template/sim/_file_vhd.f
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@@ -0,0 +1,8 @@
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#../../../01_source/01_func/IP/*.vhd
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../../../01_source/01_func/SRC/ad_da_pack.vhd
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../../../01_source/01_func/SRC/com_pack.vhd
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../../../01_source/01_func/SRC/ld_pack.vhd
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../../../01_source/01_func/SRC/top_pack.vhd
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../../../01_source/01_func/IP/*.vhd
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../../../01_source/01_func/SRC/*.vhd
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100
new_project_rtl_template/sim/apb_uart/apb_uart_interrupt.sv
Normal file
100
new_project_rtl_template/sim/apb_uart/apb_uart_interrupt.sv
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@@ -0,0 +1,100 @@
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// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
|
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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||||
// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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module apb_uart_interrupt
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#(
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parameter TX_FIFO_DEPTH = 32,
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parameter RX_FIFO_DEPTH = 32
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)
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(
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input logic clk_i,
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input logic rstn_i,
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// registers
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input logic [7:0] IER_i, // interrupt enable register
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input logic RDA_i, // receiver data available
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input logic overrun_i, // character timeout indication
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// control logic
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input logic error_i,
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input logic [$clog2(RX_FIFO_DEPTH):0] rx_elements_i,
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input logic [$clog2(TX_FIFO_DEPTH):0] tx_elements_i,
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input logic [1:0] trigger_level_i,
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input logic [3:0] clr_int_i, // one hot
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output logic interrupt_o,
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output logic [3:0] IIR_o
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);
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logic [3:0] iir_n, iir_q;
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logic trigger_level_reached;
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always_comb
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begin
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trigger_level_reached = 1'b0;
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case (trigger_level_i)
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2'b00:
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if ($unsigned(rx_elements_i) == 1)
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trigger_level_reached = 1'b1;
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2'b01:
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if ($unsigned(rx_elements_i) == 4)
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trigger_level_reached = 1'b1;
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2'b10:
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if ($unsigned(rx_elements_i) == 8)
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trigger_level_reached = 1'b1;
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2'b11:
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if ($unsigned(rx_elements_i) == 14)
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trigger_level_reached = 1'b1;
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default : /* default */;
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endcase
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end
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always_comb
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begin
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iir_n = iir_q;
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if (clr_int_i == iir_q)
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iir_n = 4'b0001;
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if (iir_q == 4'b0100 && (!trigger_level_reached && !RDA_i))
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iir_n = 4'b0001;
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// Parity error
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if (IER_i[2] & error_i)
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iir_n = 4'b0110;
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// Received data available or trigger level reached in FIFO mode
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else if (IER_i[0] & (trigger_level_reached | RDA_i))
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iir_n = 4'b0100;
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// Overrun error
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else if (IER_i[4] & overrun_i)
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iir_n = 4'b1100;
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// Transmitter holding register empty
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else if (IER_i[1] & tx_elements_i == 0)
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iir_n = 4'b0010;
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end
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always_ff @(posedge clk_i, negedge rstn_i)
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begin
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if (~rstn_i)
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begin
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iir_q <= 4'b0001;
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end
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else
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begin
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iir_q <= iir_n;
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end
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end
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assign IIR_o = iir_q;
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assign interrupt_o = ~iir_q[0];
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endmodule
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199
new_project_rtl_template/sim/apb_uart/apb_uart_rx.sv
Normal file
199
new_project_rtl_template/sim/apb_uart/apb_uart_rx.sv
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@@ -0,0 +1,199 @@
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module apb_uart_rx (
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input logic clk_i,
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input logic rstn_i,
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input logic rx_i,
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input logic [15:0] cfg_div_i,
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input logic cfg_en_i,
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input logic cfg_parity_en_i,
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input logic cfg_even_parity_i,
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input logic [1:0] cfg_bits_i,
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// input logic cfg_stop_bits_i,
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output logic busy_o,
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output logic parity_error_o,
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output logic overrun_o,
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input logic err_clr_i,
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output logic [7:0] rx_data_o,
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output logic rx_valid_o,
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input logic rx_ready_i
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);
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enum logic [2:0] {IDLE,START_BIT,DATA,PARITY,STOP_BIT} CS, NS;
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logic [7:0] reg_data;
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logic [2:0] reg_rx_sync;
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logic [2:0] reg_bit_count;
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logic [2:0] s_target_bits;
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logic parity_bit;
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logic [15:0] baud_cnt;
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logic baudgen_en;
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logic bit_done;
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logic start_bit;
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logic s_rx_fall;
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assign busy_o = (CS != IDLE);
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always_comb begin
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case(cfg_bits_i)
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2'b00:
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s_target_bits = 3'h4;
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2'b01:
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s_target_bits = 3'h5;
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2'b10:
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s_target_bits = 3'h6;
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2'b11:
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s_target_bits = 3'h7;
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endcase
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end
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always_comb begin
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NS = CS;
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baudgen_en = 1'b0;
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start_bit = 1'b0;
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case(CS)
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IDLE: begin
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if (s_rx_fall) begin
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NS = START_BIT;
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baudgen_en = 1'b1;
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start_bit = 1'b1;
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end
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end
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START_BIT: begin
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baudgen_en = 1'b1;
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start_bit = 1'b1;
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if (bit_done)
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NS = DATA;
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end
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DATA: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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if (reg_bit_count == s_target_bits) begin
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if (cfg_parity_en_i)
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NS = PARITY;
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else
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NS = STOP_BIT;
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end
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end
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end
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PARITY: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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NS = STOP_BIT;
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end
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end
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STOP_BIT: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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NS = IDLE;
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end
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end
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default:
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NS = IDLE;
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endcase
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end
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always_ff @(posedge clk_i or negedge rstn_i)
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begin
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if (rstn_i == 1'b0) begin
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CS <= IDLE;
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reg_data <= 8'hFF;
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reg_bit_count <= 'h0;
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parity_bit <= 1'b0;
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parity_error_o <= 1'b0;
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rx_valid_o <= 1'b0;
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overrun_o <= 1'b0;
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end else begin
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if(cfg_en_i)
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CS <= NS;
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else
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CS <= IDLE;
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rx_valid_o <= 0;
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case (CS)
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START_BIT:
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parity_bit <= ~cfg_even_parity_i;
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DATA:
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if (bit_done) begin
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parity_bit <= parity_bit ^ reg_rx_sync[2];
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case(cfg_bits_i)
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2'b00:
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reg_data <= {3'b000,reg_rx_sync[2],reg_data[4:1]};
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2'b01:
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reg_data <= {2'b00,reg_rx_sync[2],reg_data[5:1]};
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2'b10:
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reg_data <= {1'b0,reg_rx_sync[2],reg_data[6:1]};
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2'b11:
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reg_data <= {reg_rx_sync[2],reg_data[7:1]};
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endcase
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if (reg_bit_count == s_target_bits)
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reg_bit_count <= 'h0;
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else
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reg_bit_count <= reg_bit_count + 1;
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end
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PARITY:
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if (bit_done)
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if(parity_bit != reg_rx_sync[2])
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parity_error_o <= 1'b1;
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else
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parity_error_o <= 1'b0;
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STOP_BIT:
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if (bit_done) begin
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rx_valid_o <= 1'b1;
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overrun_o <= ~rx_ready_i;
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end
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endcase
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end
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end
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assign s_rx_fall = ~reg_rx_sync[1] & reg_rx_sync[2];
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always_ff @(posedge clk_i or negedge rstn_i) begin
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if (rstn_i == 1'b0)
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reg_rx_sync <= 3'b111;
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else begin
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if (cfg_en_i)
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reg_rx_sync <= {reg_rx_sync[1:0],rx_i};
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else
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reg_rx_sync <= 3'b111;
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end
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end
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always_ff @(posedge clk_i or negedge rstn_i) begin
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if (rstn_i == 1'b0) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b0;
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end else begin
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if(baudgen_en) begin
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if(!start_bit && (baud_cnt == cfg_div_i)) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b1;
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end else if(start_bit && (baud_cnt == {1'b0,cfg_div_i[15:1]})) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b1;
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end else begin
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baud_cnt <= baud_cnt + 1;
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bit_done <= 1'b0;
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end
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end else begin
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baud_cnt <= 'h0;
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bit_done <= 1'b0;
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end
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end
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end
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assign rx_data_o = reg_data;
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endmodule
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362
new_project_rtl_template/sim/apb_uart/apb_uart_top.sv
Normal file
362
new_project_rtl_template/sim/apb_uart/apb_uart_top.sv
Normal file
@@ -0,0 +1,362 @@
|
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// Copyright 2017 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the “License”); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
module apb_uart_top
|
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#(
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parameter CLOCK_FREQUENCY = 50e6,
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parameter BAUD_RATE = 115200,
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parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
|
||||
)
|
||||
(
|
||||
input logic CLK,
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||||
input logic RSTN,
|
||||
/* verilator lint_off UNUSED */
|
||||
input logic [APB_ADDR_WIDTH-1:0] PADDR,
|
||||
/* lint_on */
|
||||
input logic [31:0] PWDATA,
|
||||
input logic PWRITE,
|
||||
input logic PSEL,
|
||||
input logic PENABLE,
|
||||
output logic [31:0] PRDATA,
|
||||
output logic PREADY,
|
||||
output logic PSLVERR,
|
||||
|
||||
input logic rx_i, // Receiver input
|
||||
output logic tx_o, // Transmitter output
|
||||
|
||||
output logic rda_o, // rx data avaiable
|
||||
output logic tde_o, // tx data empty
|
||||
output logic event_o // interrupt/event output
|
||||
);
|
||||
// register addresses
|
||||
parameter RBR = 3'h0, THR = 3'h0, DLL = 3'h0, IER = 3'h1, DLM = 3'h1, IIR = 3'h2,
|
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FCR = 3'h2, LCR = 3'h3, MCR = 3'h4, LSR = 3'h5, MSR = 3'h6, SCR = 3'h7;
|
||||
|
||||
parameter TX_FIFO_DEPTH = 16; // in bytes
|
||||
parameter RX_FIFO_DEPTH = 16; // in bytes
|
||||
|
||||
logic [2:0] register_adr;
|
||||
logic [9:0][7:0] regs_q, regs_n;
|
||||
logic [1:0] trigger_level_n, trigger_level_q;
|
||||
|
||||
// receive buffer register, read only
|
||||
logic [7:0] rx_data;
|
||||
// parity error
|
||||
logic parity_error;
|
||||
logic rx_overrun;
|
||||
logic [3:0] IIR_o;
|
||||
logic [3:0] clr_int;
|
||||
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
// tx flow control
|
||||
logic tx_ready;
|
||||
/* lint_on */
|
||||
|
||||
// rx flow control
|
||||
logic apb_rx_ready;
|
||||
logic rx_valid;
|
||||
|
||||
logic tx_fifo_clr_n, tx_fifo_clr_q;
|
||||
logic rx_fifo_clr_n, rx_fifo_clr_q;
|
||||
|
||||
logic fifo_tx_valid;
|
||||
logic tx_valid;
|
||||
logic fifo_rx_valid;
|
||||
logic fifo_rx_ready;
|
||||
logic rx_ready;
|
||||
|
||||
logic [7:0] fifo_tx_data;
|
||||
logic [8:0] fifo_rx_data;
|
||||
|
||||
logic [7:0] tx_data;
|
||||
logic [$clog2(TX_FIFO_DEPTH):0] tx_elements;
|
||||
logic [$clog2(RX_FIFO_DEPTH):0] rx_elements;
|
||||
|
||||
// TODO: check that stop bits are really not necessary here
|
||||
apb_uart_rx apb_uart_rx_i
|
||||
(
|
||||
.clk_i ( CLK ),
|
||||
.rstn_i ( RSTN ),
|
||||
.rx_i ( rx_i ),
|
||||
.cfg_en_i ( 1'b1 ),
|
||||
.cfg_div_i ( {regs_q[DLM + 'd8], regs_q[DLL + 'd8]} ),
|
||||
.cfg_parity_en_i ( regs_q[LCR][3] ),
|
||||
.cfg_even_parity_i ( regs_q[LCR][4] ),
|
||||
.cfg_bits_i ( regs_q[LCR][1:0] ),
|
||||
// .cfg_stop_bits_i ( regs_q[LCR][2] ),
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
.busy_o ( ),
|
||||
/* lint_on */
|
||||
.parity_error_o ( parity_error ),
|
||||
.overrun_o ( rx_overrun ),
|
||||
.err_clr_i ( 1'b1 ),
|
||||
.rx_data_o ( rx_data ),
|
||||
.rx_valid_o ( rx_valid ),
|
||||
.rx_ready_i ( rx_ready )
|
||||
);
|
||||
|
||||
apb_uart_tx apb_uart_tx_i
|
||||
(
|
||||
.clk_i ( CLK ),
|
||||
.rstn_i ( RSTN ),
|
||||
.tx_o ( tx_o ),
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
.busy_o ( ),
|
||||
/* lint_on */
|
||||
.cfg_en_i ( 1'b1 ),
|
||||
.cfg_div_i ( {regs_q[DLM + 'd8], regs_q[DLL + 'd8]} ),
|
||||
.cfg_parity_en_i ( regs_q[LCR][3] ),
|
||||
.cfg_even_parity_i ( regs_q[LCR][4] ),
|
||||
.cfg_bits_i ( regs_q[LCR][1:0] ),
|
||||
.cfg_stop_bits_i ( regs_q[LCR][2] ),
|
||||
|
||||
.tx_data_i ( tx_data ),
|
||||
.tx_valid_i ( tx_valid ),
|
||||
.tx_ready_o ( tx_ready )
|
||||
);
|
||||
|
||||
io_generic_fifo
|
||||
#(
|
||||
.DATA_WIDTH ( 9 ),
|
||||
.BUFFER_DEPTH ( RX_FIFO_DEPTH )
|
||||
)
|
||||
apb_uart_rx_fifo_i
|
||||
(
|
||||
.clk_i ( CLK ),
|
||||
.rstn_i ( RSTN ),
|
||||
|
||||
.clr_i ( rx_fifo_clr_q ),
|
||||
|
||||
.elements_o ( rx_elements ),
|
||||
|
||||
.data_o ( fifo_rx_data ),
|
||||
.valid_o ( fifo_rx_valid ),
|
||||
.ready_i ( fifo_rx_ready ),
|
||||
|
||||
.valid_i ( rx_valid ),
|
||||
.data_i ( { parity_error, rx_data } ),
|
||||
.ready_o ( rx_ready )
|
||||
);
|
||||
|
||||
io_generic_fifo
|
||||
#(
|
||||
.DATA_WIDTH ( 8 ),
|
||||
.BUFFER_DEPTH ( TX_FIFO_DEPTH )
|
||||
)
|
||||
apb_uart_tx_fifo_i
|
||||
(
|
||||
.clk_i ( CLK ),
|
||||
.rstn_i ( RSTN ),
|
||||
|
||||
.clr_i ( tx_fifo_clr_q ),
|
||||
|
||||
.elements_o ( tx_elements ),
|
||||
|
||||
.data_o ( tx_data ),
|
||||
.valid_o ( tx_valid ),
|
||||
.ready_i ( tx_ready ),
|
||||
|
||||
.valid_i ( fifo_tx_valid ),
|
||||
.data_i ( fifo_tx_data ),
|
||||
// not needed since we are getting the status via the fifo population
|
||||
.ready_o ( )
|
||||
);
|
||||
|
||||
apb_uart_interrupt
|
||||
#(
|
||||
.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
|
||||
.RX_FIFO_DEPTH (RX_FIFO_DEPTH)
|
||||
)
|
||||
apb_uart_interrupt_i
|
||||
(
|
||||
.clk_i ( CLK ),
|
||||
.rstn_i ( RSTN ),
|
||||
|
||||
|
||||
.IER_i ( regs_q[IER] ), // interrupt enable register
|
||||
.RDA_i ( regs_n[LSR][0] ), // receiver data available
|
||||
.overrun_i ( regs_n[LSR][1] ), // rx data overrun
|
||||
|
||||
|
||||
.error_i ( regs_n[LSR][2] ),
|
||||
.rx_elements_i ( rx_elements ),
|
||||
.tx_elements_i ( tx_elements ),
|
||||
.trigger_level_i ( trigger_level_q ),
|
||||
|
||||
.clr_int_i ( clr_int ), // one hot
|
||||
|
||||
.interrupt_o ( event_o ),
|
||||
.IIR_o ( IIR_o )
|
||||
|
||||
);
|
||||
|
||||
// UART Registers
|
||||
|
||||
// register write and update logic
|
||||
always_comb
|
||||
begin
|
||||
regs_n = regs_q;
|
||||
trigger_level_n = trigger_level_q;
|
||||
|
||||
fifo_tx_valid = 1'b0;
|
||||
tx_fifo_clr_n = 1'b0; // self clearing
|
||||
rx_fifo_clr_n = 1'b0; // self clearing
|
||||
|
||||
// rx status
|
||||
regs_n[LSR][0] = fifo_rx_valid; // fifo is empty
|
||||
|
||||
// rx data discarded (no overrun in fact, the last rx byte was discarded.)
|
||||
regs_n[LSR][1] = rx_overrun;
|
||||
|
||||
// parity error on receiving part has occured
|
||||
regs_n[LSR][2] = parity_error;
|
||||
|
||||
// tx status register
|
||||
regs_n[LSR][5] = ~ (|tx_elements); // fifo is empty
|
||||
regs_n[LSR][6] = tx_ready & ~ (|tx_elements); // shift register and fifo are empty
|
||||
|
||||
if (PSEL && PENABLE && PWRITE)
|
||||
begin
|
||||
case (register_adr)
|
||||
|
||||
THR: // either THR or DLL
|
||||
begin
|
||||
if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
|
||||
begin
|
||||
regs_n[DLL + 'd8] = PWDATA[7:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
fifo_tx_data = PWDATA[7:0];
|
||||
fifo_tx_valid = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
IER: // either IER or DLM
|
||||
begin
|
||||
if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
|
||||
regs_n[DLM + 'd8] = PWDATA[7:0];
|
||||
else
|
||||
regs_n[IER] = PWDATA[7:0];
|
||||
end
|
||||
|
||||
LCR:
|
||||
regs_n[LCR] = PWDATA[7:0];
|
||||
|
||||
FCR: // write only register, fifo control register
|
||||
begin
|
||||
rx_fifo_clr_n = PWDATA[1];
|
||||
tx_fifo_clr_n = PWDATA[2];
|
||||
trigger_level_n = PWDATA[7:6];
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// register read logic
|
||||
always_comb
|
||||
begin
|
||||
PRDATA = 'b0;
|
||||
apb_rx_ready = 1'b0;
|
||||
fifo_rx_ready = 1'b0;
|
||||
clr_int = 4'b0;
|
||||
|
||||
if (PSEL && PENABLE && !PWRITE)
|
||||
begin
|
||||
case (register_adr)
|
||||
RBR: // either RBR or DLL
|
||||
begin
|
||||
if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
|
||||
PRDATA = {24'b0, regs_q[DLL + 'd8]};
|
||||
else
|
||||
begin
|
||||
|
||||
fifo_rx_ready = 1'b1;
|
||||
|
||||
PRDATA = {24'b0, fifo_rx_data[7:0]};
|
||||
|
||||
clr_int = 4'b1100; // clear Received Data Available interrupt
|
||||
end
|
||||
end
|
||||
|
||||
LSR: // Line Status Register
|
||||
begin
|
||||
PRDATA = {24'b0, regs_q[LSR]};
|
||||
clr_int = 4'b0110; // clear parrity interrupt error
|
||||
end
|
||||
|
||||
LCR: // Line Control Register
|
||||
PRDATA = {24'b0, regs_q[LCR]};
|
||||
|
||||
IER: // either IER or DLM
|
||||
begin
|
||||
if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
|
||||
PRDATA = {24'b0, regs_q[DLM + 'd8]};
|
||||
else
|
||||
PRDATA = {24'b0, regs_q[IER]};
|
||||
end
|
||||
|
||||
IIR: // interrupt identification register read only
|
||||
begin
|
||||
PRDATA = {24'b0, 1'b1, 1'b1, 2'b0, IIR_o};
|
||||
clr_int = 4'b0010; // clear Transmitter Holding Register Empty
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// synchronouse part
|
||||
always_ff @(posedge CLK, negedge RSTN)
|
||||
begin
|
||||
if(~RSTN)
|
||||
begin
|
||||
|
||||
regs_q[IER] <= 8'h0;
|
||||
regs_q[IIR] <= 8'h1;
|
||||
regs_q[LCR] <= 8'h3;
|
||||
regs_q[MCR] <= 8'h0;
|
||||
regs_q[LSR] <= 8'h60;
|
||||
regs_q[MSR] <= 8'h0;
|
||||
regs_q[SCR] <= 8'h0;
|
||||
regs_q[DLM + 'd8] <= 8'd1; // 50e6/115200 = 434
|
||||
regs_q[DLL + 'd8] <= 8'd178;
|
||||
|
||||
trigger_level_q <= 2'b00;
|
||||
tx_fifo_clr_q <= 1'b0;
|
||||
rx_fifo_clr_q <= 1'b0;
|
||||
|
||||
end
|
||||
else
|
||||
begin
|
||||
regs_q <= regs_n;
|
||||
|
||||
trigger_level_q <= trigger_level_n;
|
||||
tx_fifo_clr_q <= tx_fifo_clr_n;
|
||||
rx_fifo_clr_q <= rx_fifo_clr_n;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
assign register_adr = {PADDR[2:0]};
|
||||
// APB logic: we are always ready to capture the data into our regs
|
||||
// not supporting transfare failure
|
||||
assign PREADY = 1'b1;
|
||||
assign PSLVERR = 1'b0;
|
||||
|
||||
assign rda_o = regs_q[LSR][0]; // rx data avaiable
|
||||
assign tde_o = regs_q[LSR][5]; // tx data empty
|
||||
|
||||
endmodule
|
||||
162
new_project_rtl_template/sim/apb_uart/apb_uart_tx.sv
Normal file
162
new_project_rtl_template/sim/apb_uart/apb_uart_tx.sv
Normal file
@@ -0,0 +1,162 @@
|
||||
|
||||
module apb_uart_tx (
|
||||
input logic clk_i,
|
||||
input logic rstn_i,
|
||||
output logic tx_o,
|
||||
output logic busy_o,
|
||||
input logic cfg_en_i,
|
||||
input logic [15:0] cfg_div_i,
|
||||
input logic cfg_parity_en_i,
|
||||
input logic cfg_even_parity_i,
|
||||
input logic [1:0] cfg_bits_i,
|
||||
input logic cfg_stop_bits_i,
|
||||
input logic [7:0] tx_data_i,
|
||||
input logic tx_valid_i,
|
||||
output logic tx_ready_o
|
||||
);
|
||||
|
||||
enum logic [2:0] {IDLE,START_BIT,DATA,PARITY,STOP_BIT_FIRST,STOP_BIT_LAST} CS,NS;
|
||||
|
||||
logic [7:0] reg_data;
|
||||
|
||||
logic [2:0] reg_bit_count;
|
||||
|
||||
logic [2:0] s_target_bits;
|
||||
|
||||
logic parity_bit;
|
||||
|
||||
logic [15:0] baud_cnt;
|
||||
logic baudgen_en;
|
||||
logic bit_done;
|
||||
|
||||
assign busy_o = (CS != IDLE);
|
||||
|
||||
always_comb begin
|
||||
case(cfg_bits_i)
|
||||
2'b00:
|
||||
s_target_bits = 3'h4;
|
||||
2'b01:
|
||||
s_target_bits = 3'h5;
|
||||
2'b10:
|
||||
s_target_bits = 3'h6;
|
||||
2'b11:
|
||||
s_target_bits = 3'h7;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
NS = CS;
|
||||
tx_o = 1'b1;
|
||||
tx_ready_o = 1'b0;
|
||||
baudgen_en = 1'b0;
|
||||
case(CS)
|
||||
IDLE: begin
|
||||
if (cfg_en_i)
|
||||
tx_ready_o = 1'b1;
|
||||
if (tx_valid_i) begin
|
||||
NS = START_BIT;
|
||||
end
|
||||
end
|
||||
|
||||
START_BIT: begin
|
||||
tx_o = 1'b0;
|
||||
baudgen_en = 1'b1;
|
||||
if (bit_done)
|
||||
NS = DATA;
|
||||
end
|
||||
|
||||
DATA: begin
|
||||
tx_o = reg_data[0];
|
||||
baudgen_en = 1'b1;
|
||||
if (bit_done) begin
|
||||
if (reg_bit_count == s_target_bits) begin
|
||||
if (cfg_parity_en_i) begin
|
||||
NS = PARITY;
|
||||
end else begin
|
||||
NS = STOP_BIT_FIRST;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
PARITY: begin
|
||||
tx_o = parity_bit;
|
||||
baudgen_en = 1'b1;
|
||||
if (bit_done)
|
||||
NS = STOP_BIT_FIRST;
|
||||
end
|
||||
STOP_BIT_FIRST: begin
|
||||
tx_o = 1'b1;
|
||||
baudgen_en = 1'b1;
|
||||
if (bit_done) begin
|
||||
if (cfg_stop_bits_i)
|
||||
NS = STOP_BIT_LAST;
|
||||
else
|
||||
NS = IDLE;
|
||||
end
|
||||
end
|
||||
STOP_BIT_LAST: begin
|
||||
tx_o = 1'b1;
|
||||
baudgen_en = 1'b1;
|
||||
if (bit_done) begin
|
||||
NS = IDLE;
|
||||
end
|
||||
end
|
||||
default:
|
||||
NS = IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i or negedge rstn_i) begin
|
||||
if (rstn_i == 1'b0) begin
|
||||
CS <= IDLE;
|
||||
reg_data <= 8'hFF;
|
||||
reg_bit_count <= 'h0;
|
||||
parity_bit <= 1'b0;
|
||||
end else begin
|
||||
if(cfg_en_i)
|
||||
CS <= NS;
|
||||
else
|
||||
CS <= IDLE;
|
||||
|
||||
case (CS)
|
||||
IDLE:
|
||||
if (tx_valid_i)
|
||||
reg_data <= tx_data_i;
|
||||
START_BIT:
|
||||
parity_bit <= ~cfg_even_parity_i;
|
||||
DATA:
|
||||
if (bit_done) begin
|
||||
parity_bit <= parity_bit ^ reg_data[0];
|
||||
if (reg_bit_count == s_target_bits)
|
||||
reg_bit_count <= 'h0;
|
||||
else begin
|
||||
reg_bit_count <= reg_bit_count + 1;
|
||||
reg_data <= {1'b1,reg_data[7:1]};
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i or negedge rstn_i) begin
|
||||
if (rstn_i == 1'b0) begin
|
||||
baud_cnt <= 'h0;
|
||||
bit_done <= 1'b0;
|
||||
end else begin
|
||||
if(baudgen_en) begin
|
||||
if(baud_cnt == cfg_div_i) begin
|
||||
baud_cnt <= 'h0;
|
||||
bit_done <= 1'b1;
|
||||
end else begin
|
||||
baud_cnt <= baud_cnt + 1;
|
||||
bit_done <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
baud_cnt <= 'h0;
|
||||
bit_done <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
BIN
new_project_rtl_template/sim/apb_uart/doc/uart_registers.xlsx
Normal file
BIN
new_project_rtl_template/sim/apb_uart/doc/uart_registers.xlsx
Normal file
Binary file not shown.
139
new_project_rtl_template/sim/apb_uart/io_generic_fifo.sv
Normal file
139
new_project_rtl_template/sim/apb_uart/io_generic_fifo.sv
Normal file
@@ -0,0 +1,139 @@
|
||||
// Copyright 2017 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the “License”); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
module io_generic_fifo
|
||||
#(
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter BUFFER_DEPTH = 2,
|
||||
parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH)
|
||||
)
|
||||
(
|
||||
input logic clk_i,
|
||||
input logic rstn_i,
|
||||
|
||||
input logic clr_i,
|
||||
|
||||
output logic [LOG_BUFFER_DEPTH:0] elements_o,
|
||||
|
||||
output logic [DATA_WIDTH-1 : 0] data_o,
|
||||
output logic valid_o,
|
||||
input logic ready_i,
|
||||
|
||||
input logic valid_i,
|
||||
input logic [DATA_WIDTH-1 : 0] data_i,
|
||||
output logic ready_o
|
||||
);
|
||||
|
||||
// Internal data structures
|
||||
/* verilator lint_off WIDTH */
|
||||
logic [LOG_BUFFER_DEPTH-1:0] pointer_in; // location to which we last wrote
|
||||
logic [LOG_BUFFER_DEPTH-1:0] pointer_out; // location from which we last sent
|
||||
/* lint_off */
|
||||
logic [LOG_BUFFER_DEPTH:0] elements; // number of elements in the buffer
|
||||
logic [DATA_WIDTH-1:0] buffer [BUFFER_DEPTH - 1 : 0];
|
||||
|
||||
logic full;
|
||||
|
||||
int unsigned loop1;
|
||||
|
||||
assign full = (elements == BUFFER_DEPTH);
|
||||
assign elements_o = elements;
|
||||
|
||||
always_ff @(posedge clk_i, negedge rstn_i)
|
||||
begin: elements_sequential
|
||||
if (rstn_i == 1'b0)
|
||||
elements <= 0;
|
||||
else
|
||||
begin
|
||||
if (clr_i)
|
||||
elements <= 0;
|
||||
else
|
||||
begin
|
||||
// ------------------
|
||||
// Are we filling up?
|
||||
// ------------------
|
||||
// One out, none in
|
||||
if (ready_i && valid_o && (!valid_i || full))
|
||||
elements <= elements - 1;
|
||||
// None out, one in
|
||||
else if ((!valid_o || !ready_i) && valid_i && !full)
|
||||
elements <= elements + 1;
|
||||
// Else, either one out and one in, or none out and none in - stays unchanged
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i, negedge rstn_i)
|
||||
begin: buffers_sequential
|
||||
if (rstn_i == 1'b0)
|
||||
begin
|
||||
for (loop1 = 0 ; loop1 < BUFFER_DEPTH ; loop1 = loop1 + 1)
|
||||
buffer[loop1] <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Update the memory
|
||||
if (valid_i && !full)
|
||||
buffer[pointer_in] <= data_i;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i, negedge rstn_i)
|
||||
begin: sequential
|
||||
if (rstn_i == 1'b0)
|
||||
begin
|
||||
pointer_out <= 0;
|
||||
pointer_in <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(clr_i)
|
||||
begin
|
||||
pointer_out <= 0;
|
||||
pointer_in <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// ------------------------------------
|
||||
// Check what to do with the input side
|
||||
// ------------------------------------
|
||||
// We have some input, increase by 1 the input pointer
|
||||
if (valid_i && !full)
|
||||
begin
|
||||
if (pointer_in == $unsigned(BUFFER_DEPTH - 1))
|
||||
pointer_in <= 0;
|
||||
else
|
||||
pointer_in <= pointer_in + 1;
|
||||
end
|
||||
// Else we don't have any input, the input pointer stays the same
|
||||
|
||||
// -------------------------------------
|
||||
// Check what to do with the output side
|
||||
// -------------------------------------
|
||||
// We had pushed one flit out, we can try to go for the next one
|
||||
if (ready_i && valid_o)
|
||||
begin
|
||||
if (pointer_out == $unsigned(BUFFER_DEPTH - 1))
|
||||
pointer_out <= 0;
|
||||
else
|
||||
pointer_out <= pointer_out + 1;
|
||||
end
|
||||
// Else stay on the same output location
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Update output ports
|
||||
assign data_o = buffer[pointer_out];
|
||||
assign valid_o = (elements != 0);
|
||||
|
||||
assign ready_o = ~full;
|
||||
|
||||
endmodule
|
||||
23
new_project_rtl_template/sim/clear.tcl
Normal file
23
new_project_rtl_template/sim/clear.tcl
Normal file
@@ -0,0 +1,23 @@
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
|
||||
echo on
|
||||
|
||||
#quit from current runing simulation
|
||||
quit -sim
|
||||
#clear the transcript window,only valid in batch mode
|
||||
|
||||
if [batch_mode] {
|
||||
# log /*
|
||||
} else {
|
||||
.main clear
|
||||
}
|
||||
28
new_project_rtl_template/sim/commit.cmd
Normal file
28
new_project_rtl_template/sim/commit.cmd
Normal file
@@ -0,0 +1,28 @@
|
||||
svn add . data --depth=empty
|
||||
svn add . data/*.txt data/*.m
|
||||
|
||||
svn add . coverage --depth=empty
|
||||
svn add . coverage/*.ucdb
|
||||
|
||||
svn add . func* --depth=empty
|
||||
rem walk through all func* director
|
||||
for /D %%i in (fun*) do (
|
||||
svn add . %%i/*.sv
|
||||
svn add . %%i/*.tcl
|
||||
svn add . %%i/*.do
|
||||
svn add . %%i/*.mif )
|
||||
|
||||
|
||||
svn add . timing* --depth=empty
|
||||
rem walk through all func* director
|
||||
for /D %%i in (timing*) do (
|
||||
svn add . %%i/*.sv
|
||||
svn add . %%i/*.tcl
|
||||
svn add . %%i/*.do
|
||||
svn add . %%i/*.mif )
|
||||
|
||||
svn add --depth=empty . *.tcl *.sv *.v *.bat *.cmd *.f *.do
|
||||
|
||||
svn status -v .
|
||||
svn commit -m "autocommit" .
|
||||
pause
|
||||
20
new_project_rtl_template/sim/file_ver.f
Normal file
20
new_project_rtl_template/sim/file_ver.f
Normal file
@@ -0,0 +1,20 @@
|
||||
+define+__MICROSATE_SIM__
|
||||
vip_clock.sv
|
||||
tb.sv
|
||||
../glbl.v
|
||||
../apb_uart/apb_uart_top.sv
|
||||
../apb_uart/apb_uart_tx.sv
|
||||
../apb_uart/apb_uart_rx.sv
|
||||
../apb_uart/io_generic_fifo.sv
|
||||
../apb_uart/apb_uart_interrupt.sv
|
||||
../../src/debug_hub/debug_cli.sv
|
||||
../../src/apbmif.sv
|
||||
../../src/uart/uart.sv
|
||||
../../src/uart/uart_rx.sv
|
||||
../../src/uart/uart_tx.sv
|
||||
../../src/debug_hub.sv
|
||||
../../src/apb_slave_mux.sv
|
||||
../../src/apbsif.sv
|
||||
../../src/xx_regfile.sv
|
||||
../../src/subtop_module.sv
|
||||
../../src/top_module.sv
|
||||
119
new_project_rtl_template/sim/find_unreferenced_sources.tcl
Normal file
119
new_project_rtl_template/sim/find_unreferenced_sources.tcl
Normal file
@@ -0,0 +1,119 @@
|
||||
|
||||
proc relative_to_absolute {relative_path} {
|
||||
|
||||
#replace all "../" and count how many "../" occured in the original string
|
||||
set parent_dir_count [regsub -all {\.\.\/} $relative_path "" sufix_path]
|
||||
set redir_path [pwd];
|
||||
|
||||
#cut the current path by N-times to get the common parent path for both "abs" and "rela"
|
||||
for {set i 0 } {$i < $parent_dir_count} {incr i} {
|
||||
set last_dir [file tail redir_path];
|
||||
regsub /$last_dir $redir_path "" redir_path;
|
||||
}
|
||||
set prefix_path $redir_path;
|
||||
|
||||
set absolute_path $prefix_path/$sufix_path;
|
||||
|
||||
return $absolute_path;
|
||||
|
||||
}
|
||||
|
||||
|
||||
proc find_files {root_path } {
|
||||
list results;
|
||||
|
||||
#store the current path
|
||||
set current_path [pwd];
|
||||
cd $root_path;
|
||||
set root_path [pwd];
|
||||
|
||||
puts "entering $root_path"
|
||||
# get all files recusively
|
||||
foreach element [glob -nocomplain *] {
|
||||
|
||||
# entering sub dirs
|
||||
if { [file isdirectory $element]} {
|
||||
|
||||
set subList [find_files $element];
|
||||
set results [concat $results $subList];
|
||||
} else {
|
||||
# only valid source files are filtered
|
||||
if {[string match "*.v" $element] || [string match "*.sv" $element] || [string match "*.vhd" $element] || [string match "*.vhdl" $element]} {
|
||||
lappend results "$root_path/$element";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
cd $current_path;
|
||||
|
||||
return $results;
|
||||
}
|
||||
|
||||
puts "---------------------------------ATTENTION----------------------------------------"
|
||||
puts "----------- this file should be sourced after the vsim load sucessfully-----------"
|
||||
puts "----------- this file should be sourced from the funcXXX director-----------------"
|
||||
puts ""
|
||||
|
||||
#write report -l info.txt
|
||||
|
||||
|
||||
|
||||
puts ":::::::::get referced dut files:::::::::"
|
||||
set f_report [open info.txt r];
|
||||
|
||||
#read the report,get all referenced files
|
||||
while {![eof $f_report]} {
|
||||
gets $f_report line
|
||||
|
||||
if { [string match "*Source File*" $line] } {
|
||||
lappend referenced_files $line
|
||||
}
|
||||
}
|
||||
close $f_report
|
||||
|
||||
#remove those source file,point to precompiled vendor library
|
||||
#convert the relative path to absolute path
|
||||
list referenced_dut_files;
|
||||
foreach element $referenced_files {
|
||||
if { [string match "*Source File: \.\./\.\./*" $element] } {
|
||||
regsub {^.*Source File:} $element "" path
|
||||
set relative_path [string trim $path ]
|
||||
set abs_path [relative_to_absolute $relative_path]
|
||||
lappend referenced_dut_files $abs_path
|
||||
# puts $abs_path
|
||||
}
|
||||
}
|
||||
|
||||
puts ":::::::::get all compiled source files:::::::::"
|
||||
#get all source files in the source file directory ,recursively
|
||||
set root_path ../../../01_source/01_func;
|
||||
set all_sources [find_files $root_path ];
|
||||
|
||||
puts ":::::::::try to match:::::::::"
|
||||
#try to match the two lists,and filter the mis-matched ones
|
||||
|
||||
set f_referenced_dut_files [open "referenced.txt" w+];
|
||||
foreach sim_file $referenced_dut_files {
|
||||
puts $f_referenced_dut_files $sim_file;
|
||||
}
|
||||
close $f_referenced_dut_files
|
||||
|
||||
set f_dir_files [open "dir.txt" w+];
|
||||
foreach dir_file $all_sources {
|
||||
puts $f_dir_files $dir_file;
|
||||
}
|
||||
close $f_dir_files
|
||||
|
||||
lappend mis_matched_dir_files;
|
||||
foreach dir_file $all_sources {
|
||||
|
||||
puts $dir_file
|
||||
set index [lsearch $referenced_dut_files $dir_file]
|
||||
if {$index == -1} {
|
||||
lappend mis_matched_dir_files $dir_file
|
||||
puts dir=$dir_file
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
21
new_project_rtl_template/sim/func001/addwave.tcl
Normal file
21
new_project_rtl_template/sim/func001/addwave.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
echo off
|
||||
#useage do addwave.tcl uart,where uart is a module name
|
||||
#when there is mulitple matches,the 1st one is picked
|
||||
puts "---->find by design unit:$1"
|
||||
|
||||
set patten *$1*;
|
||||
#puts "---->find patten:$patten"
|
||||
|
||||
set rslt [find instance -bydu $patten];
|
||||
#puts "---->find result:$rslt"
|
||||
|
||||
regsub {\{} $rslt "" rslt;
|
||||
regsub {\}} $rslt "" rslt;
|
||||
|
||||
regsub { (.*)} $rslt "" path;
|
||||
#puts "---->design path is:$path"
|
||||
|
||||
set signal_list ${path}/*
|
||||
puts "---->list to be add to wave:$signal_list"
|
||||
|
||||
add wave $signal_list
|
||||
22
new_project_rtl_template/sim/func001/can_transceiver.sv
Normal file
22
new_project_rtl_template/sim/func001/can_transceiver.sv
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
can bus physical model by leguoqing
|
||||
*/
|
||||
|
||||
module can_transceiver
|
||||
(
|
||||
output logic rxd = 1,
|
||||
input logic txd,
|
||||
inout tri1 line
|
||||
);
|
||||
|
||||
always@(*)
|
||||
if (line == 1'b0) rxd <= 1'b0;
|
||||
else rxd <= 1'b1;
|
||||
|
||||
logic line_reg;
|
||||
always@(*)
|
||||
if (txd == 0) line_reg <= 0;
|
||||
else line_reg <= 1;
|
||||
|
||||
assign line = line_reg ? 1'bz : 0;
|
||||
endmodule
|
||||
254
new_project_rtl_template/sim/func001/cmsdk_uart_capture_ard.v
Normal file
254
new_project_rtl_template/sim/func001/cmsdk_uart_capture_ard.v
Normal file
@@ -0,0 +1,254 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited.
|
||||
//
|
||||
// (C) COPYRIGHT 2010-2013 ARM Limited.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited.
|
||||
//
|
||||
// SVN Information
|
||||
//
|
||||
// Checked In : $Date: 2013-02-08 10:40:04 +0000 (Fri, 08 Feb 2013) $
|
||||
//
|
||||
// Revision : $Revision: 365823 $
|
||||
//
|
||||
// Release Information : CM3DesignStart-r0p0-02rel0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
//-----------------------------------------------------------------------------
|
||||
// Abstract : A device to capture serial data
|
||||
//-----------------------------------------------------------------------------
|
||||
// This module assume CLK is same frequency as baud rate.
|
||||
// In the example UART a test mode is used to enable data output as maximum
|
||||
// speed (PCLK). In such case we can connect CLK signal directly to PCLK.
|
||||
// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
|
||||
// accordingly as well.
|
||||
//
|
||||
// This module stop the simulation when character 0x04 is received.
|
||||
// An output called SIMULATION_END is set for 1 cycle before simulation is
|
||||
// terminated to allow other testbench component like profiler (if any)
|
||||
// to output reports before the simulation stop.
|
||||
//
|
||||
// This model also support ESCAPE (0x1B, decimal 27) code sequence
|
||||
// ESC - 0x10 - XY Capture XY to AUXCTRL output
|
||||
// ESC - 0x11 Set DEBUG_TESTER_ENABLE to 1
|
||||
// ESC - 0x12 Clear DEBUG_TESTER_ENABLE to 0
|
||||
|
||||
|
||||
module cmsdk_uart_capture_ard (
|
||||
input wire RESETn, // Power on reset
|
||||
input wire CLK, // Clock (baud rate)
|
||||
input wire RXD, // Received data
|
||||
output wire SIMULATIONEND, // Simulation end indicator
|
||||
output wire DEBUG_TESTER_ENABLE, // Enable debug tester
|
||||
output wire [7:0] AUXCTRL, // Auxiliary control
|
||||
output wire SPI0, // Shield0 SPI enable
|
||||
output wire SPI1, // Shield1 SPI enable
|
||||
output wire I2C0, // Shield0 I2C enable
|
||||
output wire I2C1, // Shield1 I2C enable
|
||||
output wire UART0, // Shield0 UART enable
|
||||
output wire UART1); // Shield1 UART enable
|
||||
|
||||
reg [8:0] rx_shift_reg;
|
||||
wire[8:0] nxt_rx_shift;
|
||||
reg [6:0] string_length;
|
||||
reg [7:0] tube_string [127:0];
|
||||
reg [7:0] text_char;
|
||||
integer i;
|
||||
reg nxt_end_simulation;
|
||||
reg reg_end_simulation;
|
||||
wire char_received;
|
||||
reg reg_esc_code_mode; // Escape code mode
|
||||
reg reg_aux_ctrl_mode; // Auxiliary control capture mode
|
||||
reg [7:0] reg_aux_ctrl; // Registered Auxiliary control
|
||||
reg reg_dbgtester_enable;
|
||||
reg SPI0_reg;
|
||||
reg SPI1_reg;
|
||||
reg I2C0_reg;
|
||||
reg I2C1_reg;
|
||||
reg UART0_reg;
|
||||
reg UART1_reg;
|
||||
|
||||
// Receive shift register
|
||||
assign nxt_rx_shift = {RXD,rx_shift_reg[8:1]};
|
||||
assign char_received = (rx_shift_reg[0]==1'b0);
|
||||
|
||||
initial
|
||||
begin
|
||||
SPI0_reg <= 1'b0;
|
||||
SPI1_reg <= 1'b0;
|
||||
I2C0_reg <= 1'b0;
|
||||
I2C1_reg <= 1'b0;
|
||||
UART0_reg <= 1'b0;
|
||||
UART1_reg <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge CLK or negedge RESETn)
|
||||
begin
|
||||
if (~RESETn)
|
||||
rx_shift_reg <= {9{1'b1}};
|
||||
else
|
||||
if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
|
||||
rx_shift_reg <= {9{1'b1}};
|
||||
else
|
||||
rx_shift_reg <= nxt_rx_shift;
|
||||
end
|
||||
|
||||
// Escape code mode register
|
||||
always @(posedge CLK or negedge RESETn)
|
||||
begin
|
||||
if (~RESETn)
|
||||
reg_esc_code_mode <= 1'b0;
|
||||
else // Set to escape mode if ESC code is detected
|
||||
if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
|
||||
reg_esc_code_mode <= 1'b1;
|
||||
else if (char_received)
|
||||
reg_esc_code_mode <= 1'b0;
|
||||
end
|
||||
|
||||
// Aux Ctrl capture mode register
|
||||
always @(posedge CLK or negedge RESETn)
|
||||
begin
|
||||
if (~RESETn)
|
||||
reg_aux_ctrl_mode <= 1'b0;
|
||||
else // Set to Aux control capture mode if ESC-0x10 sequence is detected
|
||||
if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
|
||||
reg_aux_ctrl_mode <= 1'b1;
|
||||
else if (char_received)
|
||||
reg_aux_ctrl_mode <= 1'b0;
|
||||
end
|
||||
|
||||
// Aux Ctrl capture data register
|
||||
always @(posedge CLK or negedge RESETn)
|
||||
begin
|
||||
if (~RESETn)
|
||||
reg_aux_ctrl <= {8{1'b0}};
|
||||
else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
|
||||
if (char_received & (reg_aux_ctrl_mode==1'b1))
|
||||
reg_aux_ctrl <= rx_shift_reg[8:1];
|
||||
end
|
||||
|
||||
assign AUXCTRL = reg_aux_ctrl;
|
||||
|
||||
// Debug tester enable
|
||||
always @(posedge CLK or negedge RESETn)
|
||||
begin
|
||||
if (~RESETn)
|
||||
reg_dbgtester_enable <= 1'b0;
|
||||
else // Enable debug tester if ESC-0x11 sequence is detected
|
||||
if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
|
||||
reg_dbgtester_enable <= 1'b1;
|
||||
else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
|
||||
// Disable debug tester if ESC-0x12 sequence is detected
|
||||
reg_dbgtester_enable <= 1'b0;
|
||||
end
|
||||
|
||||
assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
|
||||
|
||||
// Message display
|
||||
always @ (posedge CLK or negedge RESETn)
|
||||
begin: p_tube
|
||||
if (~RESETn)
|
||||
begin
|
||||
string_length = 7'b0;
|
||||
nxt_end_simulation <= 1'b0;
|
||||
for (i=0; i<= 127; i=i+1) begin
|
||||
tube_string [i] = 8'h00;
|
||||
end
|
||||
end
|
||||
else
|
||||
if (char_received)
|
||||
begin
|
||||
if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
|
||||
begin
|
||||
// Escape code, or in escape code mode
|
||||
// Data receive can be command, aux ctrl data
|
||||
// Ignore this data
|
||||
end
|
||||
else if (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
|
||||
nxt_end_simulation <= 1'b1;
|
||||
else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
|
||||
// New line
|
||||
begin
|
||||
tube_string[string_length] = 8'h00;
|
||||
$write("%t UART: ",$time);
|
||||
|
||||
for (i=0; i<= string_length; i=i+1)
|
||||
begin
|
||||
text_char = tube_string[i];
|
||||
$write("%s",text_char);
|
||||
end
|
||||
|
||||
$write("\n");
|
||||
string_length = 7'b0;
|
||||
end
|
||||
else if (rx_shift_reg[8:1]==8'h0F)
|
||||
begin
|
||||
$write("%t UART: Switching on Shield I2C, SPI and UART\n",$time);
|
||||
SPI0_reg <= 1'b1;
|
||||
SPI1_reg <= 1'b1;
|
||||
I2C0_reg <= 1'b1;
|
||||
I2C1_reg <= 1'b1;
|
||||
UART0_reg <= 1'b1;
|
||||
UART1_reg <= 1'b1;
|
||||
end
|
||||
|
||||
else
|
||||
begin
|
||||
tube_string[string_length] = rx_shift_reg[8:1];
|
||||
string_length = string_length + 1;
|
||||
if (string_length >79) // line too long, display and clear buffer
|
||||
begin
|
||||
tube_string[string_length] = 8'h00;
|
||||
$write("%t UART: ",$time);
|
||||
|
||||
for (i=0; i<= string_length; i=i+1)
|
||||
begin
|
||||
text_char = tube_string[i];
|
||||
$write("%s",text_char);
|
||||
end
|
||||
|
||||
$write("\n");
|
||||
string_length = 7'b0;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end // p_TUBE
|
||||
|
||||
// Delay for simulation end
|
||||
always @ (posedge CLK or negedge RESETn)
|
||||
begin: p_sim_end
|
||||
if (~RESETn)
|
||||
begin
|
||||
reg_end_simulation <= 1'b0;
|
||||
end
|
||||
else
|
||||
reg_end_simulation <= nxt_end_simulation;
|
||||
if (reg_end_simulation==1'b1)
|
||||
begin
|
||||
$write("%t UART: Test Ended\n",$time);
|
||||
$stop;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign SIMULATIONEND = nxt_end_simulation & ~reg_end_simulation;
|
||||
|
||||
assign SPI0 = SPI0_reg;
|
||||
assign SPI1 = SPI1_reg;
|
||||
assign I2C0 = I2C0_reg;
|
||||
assign I2C1 = I2C1_reg;
|
||||
assign UART0 = UART0_reg;
|
||||
assign UART1 = UART1_reg;
|
||||
|
||||
endmodule
|
||||
27
new_project_rtl_template/sim/func001/debussy.bat
Normal file
27
new_project_rtl_template/sim/func001/debussy.bat
Normal file
@@ -0,0 +1,27 @@
|
||||
::关闭回显
|
||||
@ECHO OFF
|
||||
::设置软件路径
|
||||
SET Debussy=C:\Novas\Debussy\bin\Debussy.exe
|
||||
SET vericom=C:\Novas\Debussy\bin\vericom.exe
|
||||
SET vhdlcom=C:\Novas\Debussy\bin\vhdlcom.exe
|
||||
|
||||
::===== import design from file (compile design into ram) =====
|
||||
::仅适用于纯 v/sv 工程
|
||||
%Debussy% -sv -f ../file_ver.f
|
||||
|
||||
::===== import design from library (compile design into library) =====
|
||||
::适用于 混合语言工程 和 纯 v/sv 工程
|
||||
::%vericom% -sv -2001 -f file_ver.f
|
||||
::%vhdlcom% -2000 -f file_vhd.f
|
||||
::%Debussy% -lib work -top top &
|
||||
|
||||
::删除波形文件
|
||||
::DEL Debussy.fsdb /q
|
||||
|
||||
::删除Debussy生成的相关文件
|
||||
RD Debussy.exeLog /s /q
|
||||
DEL novas.rc /q
|
||||
|
||||
::退出命令行
|
||||
EXIT
|
||||
|
||||
@@ -0,0 +1,143 @@
|
||||
#usage : do find_unreferenced_sources.tcl [-d]
|
||||
# if -d is not specified,only list out the unrefferenced files
|
||||
# the script does:
|
||||
# step 1 :generate the report
|
||||
# step 2 :get all referced files from the report
|
||||
# step 3 :get all compiled files from the 01_source/01_func directory
|
||||
# step 4 :compare the two list,find out the unrefferenced ones
|
||||
# step 5:optionnnaly,delete the unrefferenced files
|
||||
# step 6: remove the generated reports
|
||||
|
||||
proc relative_to_absolute {relative_path} {
|
||||
|
||||
#replace all "../" and count how many "../" occured in the original string
|
||||
set parent_dir_count [regsub -all {\.\.\/} $relative_path "" sufix_path];
|
||||
set redir_path [pwd];
|
||||
|
||||
#cut the current path by N-times to get the common parent path for both "abs" and "rela"
|
||||
for {set i 0 } {$i < $parent_dir_count} {incr i} {
|
||||
set last_dir [file tail $redir_path];
|
||||
regsub /$last_dir $redir_path "" redir_path;
|
||||
}
|
||||
set prefix_path $redir_path;
|
||||
# puts redir_path=$redir_path
|
||||
set absolute_path $prefix_path/$sufix_path;
|
||||
|
||||
return $absolute_path;
|
||||
}
|
||||
|
||||
|
||||
proc find_files {root_path } {
|
||||
set results [list];
|
||||
# lappend results;
|
||||
|
||||
#store the current path
|
||||
set current_path [pwd];
|
||||
cd $root_path;
|
||||
set root_path [pwd];
|
||||
|
||||
puts "entering $root_path"
|
||||
# get all files recusively
|
||||
foreach element [glob -nocomplain * ;] {
|
||||
|
||||
# entering sub dirs
|
||||
if { [file isdirectory $element]} {
|
||||
|
||||
set sublist [find_files $element];
|
||||
set results [concat $results $sublist];
|
||||
} else {
|
||||
# only valid source files are filtered
|
||||
if {[string match "*.v" $element] || [string match "*.sv" $element] || [string match "*.vhd" $element] || [string match "*.vhdl" $element]} {
|
||||
lappend results "$root_path/$element";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
cd $current_path;
|
||||
|
||||
puts "++++++++++++++++++++++++++++"
|
||||
return $results;
|
||||
}
|
||||
|
||||
.main clear
|
||||
#exit simulation ,unless the change dir will not work
|
||||
q -sim
|
||||
|
||||
puts "---------------------------------ATTENTION----------------------------------------"
|
||||
puts "----------- this file should be sourced after the vsim load sucessfully-----------"
|
||||
puts "----------- this file should be sourced from the funcXXX director-----------------"
|
||||
puts ""
|
||||
|
||||
|
||||
puts ":::::::::get referced dut files:::::::::"
|
||||
set referenced_files [list ]
|
||||
set f_report [open $TEMP_REF_FILES r];
|
||||
|
||||
#read the report,get all referenced files
|
||||
while {![eof $f_report]} {
|
||||
gets $f_report line ;
|
||||
|
||||
if { [string match "*Source File*" $line] } {
|
||||
lappend referenced_files $line;
|
||||
}
|
||||
}
|
||||
close $f_report
|
||||
|
||||
#remove those source file,point to precompiled vendor library
|
||||
#convert the relative path to absolute path
|
||||
#list referenced_dut_files;
|
||||
foreach element $referenced_files {
|
||||
if { [string match "*Source File: \.\./\.\./*" $element] } {
|
||||
regsub {^.*Source File:} $element "" path;
|
||||
set relative_path [string trim $path ];
|
||||
set abs_path [relative_to_absolute $relative_path];
|
||||
lappend referenced_dut_files $abs_path
|
||||
# puts $abs_path
|
||||
}
|
||||
}
|
||||
|
||||
puts ":::::::::get all compiled source files:::::::::"
|
||||
#get all source files in the source file directory ,recursively
|
||||
set root_path ../../../01_source/01_func;
|
||||
set all_sources [find_files $root_path;];
|
||||
.main clear
|
||||
|
||||
puts ":::::::::try to match:::::::::"
|
||||
#try to match the two lists,and filter the mis-matched ones
|
||||
|
||||
#set f_referenced_dut_files [open "referenced.txt" w+];
|
||||
#foreach sim_file $referenced_dut_files {
|
||||
# puts $f_referenced_dut_files $sim_file;
|
||||
#}
|
||||
#close $f_referenced_dut_files;
|
||||
|
||||
#set f_dir_files [open "dir.txt" w+];
|
||||
#foreach dir_file $all_sources {
|
||||
# puts $f_dir_files $dir_file;
|
||||
#}
|
||||
#close $f_dir_files
|
||||
|
||||
puts "found dismated files as follow:"
|
||||
set mis_matched_dir_files [list]
|
||||
foreach dir_file $all_sources {
|
||||
|
||||
set index [lsearch $referenced_dut_files $dir_file];
|
||||
if {$index == -1} {
|
||||
lappend mis_matched_dir_files $dir_file;
|
||||
puts "path=$dir_file"
|
||||
}
|
||||
}
|
||||
|
||||
#if specified the -d switch,just delete the files
|
||||
if {$argc == 1 && [string equal $1 "-d"]} {
|
||||
|
||||
puts "the -d switch specified ,delete the dismatched files automatically"
|
||||
foreach del_file $mis_matched_dir_files {
|
||||
file delete -force $del_file
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#file delete -force $TEMP_REF_FILES
|
||||
|
||||
|
||||
98
new_project_rtl_template/sim/func001/format_save.tcl
Normal file
98
new_project_rtl_template/sim/func001/format_save.tcl
Normal file
@@ -0,0 +1,98 @@
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {true} {
|
||||
# raw script code in pre_format
|
||||
set pre_format {
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
}
|
||||
}; list
|
||||
# from stackoverflow.com "how to keep commands quiet in TCL?"
|
||||
# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
|
||||
# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
|
||||
# for instance: set a [open "giri.txt" r]; list
|
||||
|
||||
if {true} {
|
||||
# raw script code in post_format
|
||||
set post_format {
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
}
|
||||
}; list
|
||||
|
||||
# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
|
||||
if {true} {
|
||||
# save current wave format to a tmp file
|
||||
catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
|
||||
|
||||
if {$argc>=1} { # example: do savewave.tcl wave_name
|
||||
set wave_name $1
|
||||
if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
|
||||
# replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
|
||||
while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
|
||||
regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
|
||||
}
|
||||
} elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
|
||||
# nop
|
||||
} else {
|
||||
echo "Invalid file name $wave_name!"
|
||||
return
|
||||
}
|
||||
set fd_wave [open $wave_name.tcl w]
|
||||
echo "Wave format saved to $wave_name.tcl"
|
||||
} else { # example: do savewave.tcl
|
||||
set fd_wave [open lastwave.tcl w]
|
||||
echo "Wave format saved to lastwave.tcl"
|
||||
}
|
||||
|
||||
set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
|
||||
|
||||
# put lines in pre_format to final file(the file specified in argument $1)
|
||||
set lines [split $pre_format "\n"]
|
||||
set total_lines [llength $lines]
|
||||
for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
|
||||
set wave_format_line [lindex $lines $line_idx]
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
# put lines in tmp file to final file(the file specified in argument $1)
|
||||
while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
|
||||
if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
|
||||
# if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
|
||||
regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
|
||||
# and then add eval in the biginning
|
||||
regsub (^) $wave_format_line {eval } wave_format_line
|
||||
}
|
||||
# make virtual signal ok
|
||||
if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
|
||||
regsub -all {\{} $wave_format_line {[subst &} wave_format_line
|
||||
regsub -all {\}} $wave_format_line {&]} wave_format_line
|
||||
}
|
||||
regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
# put lines in post_format to final file(the file specified in argument $1)
|
||||
set lines [split $post_format "\n"]
|
||||
set total_lines [llength $lines]
|
||||
for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
|
||||
set wave_format_line [lindex $lines $line_idx]
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
close $fd_wave
|
||||
close $fd_intermediate_wave_format_file
|
||||
}
|
||||
280
new_project_rtl_template/sim/func001/lastwave.tcl
Normal file
280
new_project_rtl_template/sim/func001/lastwave.tcl
Normal file
@@ -0,0 +1,280 @@
|
||||
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/read_agent_state
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mode
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ready
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/write_ping_n_or_pong
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ping_ready
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_pong_ready
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en_d1
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_start
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_mode
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_next_page
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/tmr_cnt
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/page_cnt
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_lo_addr
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_grant
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req_end
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_addr
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_req
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_data
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_done
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/fifo_latency_cnt
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_dq
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_full
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_empty
|
||||
add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_rd
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/state_c
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_m_write_tmr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_read_page_tmr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_req
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_type
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_ack
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_done
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_req
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_type
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_ack
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_waddr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wdata
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_re
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata_vld
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_pending
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_writing
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_pending
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_reading
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mr_f
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mw_f
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_m_r
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_grant
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req_end
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_op_addr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_req
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wdata
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_done
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_req
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rdata
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_done
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/cnt_read_page_tmr
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_1
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_2
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_3
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_die
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_block
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_page
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_col_r
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_we
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_re
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_data_out
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_full
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_empty
|
||||
add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_q
|
||||
add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req
|
||||
add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req_end
|
||||
add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/o_grant
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/state_c
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/stat_vld
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/status
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/init_done
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/done
|
||||
add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/block_flag
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/state_c
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_full
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_flag
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_low
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_high
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_1
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_2
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_3
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/wram_re_reg
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/read_flag
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/write_flag
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_data_out
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_out_0
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata_vld
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_we
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_add_byte
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_re_n
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_we_n
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/activate
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_in
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_row
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_col
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/status
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/busy
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/stat_vld
|
||||
add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/done
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_mram_area
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/ARBT_ADC_CS
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req_end
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_arbt_grant
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_op_addr
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_req
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_data
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_wr_done
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_rd_req
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_data
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_done
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_smp_num
|
||||
add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_mram_data_volume
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_mram_area
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/NAND_WR_CS
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/ri_mode_code
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_axis
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_sensor
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req_end
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_arbt_grant
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_addr
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_req
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_data
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_done
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_smp_num
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_data_volume
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_if_dpram_rd_done
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_addr
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_data
|
||||
add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_done
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/vote_state
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ready
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ping_n_or_pong
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_clear
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_type
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/tmr_cnt
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/page_cnt
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_lo_addr
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req_end
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_grant
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_addr
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_req
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_data
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_done
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/burst_req
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/trunk_over
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data
|
||||
add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data_vld
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/SCI_CS
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_trunk_id_cnt
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_type
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_ready
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_service_request
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/ccsds
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_active
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_cs
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_en
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_addr
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data_vld
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm_done
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci_done
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data_vld
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_burst_req
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_trunk_over
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_addr_offset
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_frame_cnt
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_din_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_cs_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_r_wn_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_din_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_cs_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_r_wn_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_addr_b
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/chksum
|
||||
add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/sensor_id
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/CS
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_ce_n
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_oe_n
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_we_n
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_addr
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/io_bank_data
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_op_addr
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_req
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_data
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_wr_done
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_rd_req
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_data
|
||||
add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_done
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/DIST_CS
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_1553_int_n
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_buf_service_request
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/w_buf_service_request
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/vector_word
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_mem_reg_n
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/r_1553_int_n_neg
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_op_addr
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_req
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_data
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_wr_done
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_rd_req
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_data
|
||||
add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_done
|
||||
eval TreeUpdate \[SetDefaultTree\]
|
||||
WaveRestoreCursors {{Cursor 1} {703840517004 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 248
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1575 ms}
|
||||
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
|
||||
BIN
new_project_rtl_template/sim/func001/merged.ucdb
Normal file
BIN
new_project_rtl_template/sim/func001/merged.ucdb
Normal file
Binary file not shown.
2037
new_project_rtl_template/sim/func001/modelsim.ini
Normal file
2037
new_project_rtl_template/sim/func001/modelsim.ini
Normal file
File diff suppressed because it is too large
Load Diff
227
new_project_rtl_template/sim/func001/run.tcl
Normal file
227
new_project_rtl_template/sim/func001/run.tcl
Normal file
@@ -0,0 +1,227 @@
|
||||
#quit -sim
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#unbound the the "work" lib dir from vsim,to remove it
|
||||
|
||||
#when error do not save wave list
|
||||
if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
|
||||
source savewave.tcl
|
||||
}
|
||||
#catch {q -sim} res
|
||||
#dataset close -all
|
||||
|
||||
echo on
|
||||
.main clear
|
||||
|
||||
puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
|
||||
|
||||
vmap std $SIM_TOOL_PATH/std ;
|
||||
vmap ieee $SIM_TOOL_PATH/ieee ;
|
||||
|
||||
set FUNC_SOURCE_DIR ../../../01_source/01_func
|
||||
set TIMING_SOURCE_DIR ../../../01_source/02_timing
|
||||
|
||||
set source_vhdl false
|
||||
set source_verilog false
|
||||
|
||||
set LIB_OPTION ""
|
||||
set LOG_OPTION ""
|
||||
|
||||
#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
|
||||
# #-----------actel----------
|
||||
# #puts "IDE IS $FPGA_KIT_VER!"
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
|
||||
# set LOG_OPTION "-vhdlvariablelogging"
|
||||
# }
|
||||
# if {[string equal -nocase vhd $TOP_FILE_LANG]} {
|
||||
# vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
|
||||
# } else {
|
||||
# vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
|
||||
# }
|
||||
# set LIB_OPTION "-L ${ACTEL_FAMILY}"
|
||||
#
|
||||
#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
|
||||
# #puts "IDE IS $FPGA_KIT_VER!"
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
|
||||
# set source_vhdl true
|
||||
# set LOG_OPTION "-vhdlvariablelogging"
|
||||
# }
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
|
||||
# set source_verilog true
|
||||
# }
|
||||
# if { [string equal -nocase true $source_vhdl] } {
|
||||
# #-----------xilinx vhdl----------
|
||||
# #puts "vhdl file exist!"
|
||||
# vmap simprim $VHDL_LIB/simprim
|
||||
# vmap unisim $VHDL_LIB/unisim
|
||||
# vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
|
||||
# vmap unimacro $VHDL_LIB/unimacro
|
||||
# set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
|
||||
# }
|
||||
#
|
||||
# if { [string equal -nocase true $source_verilog] } {
|
||||
# #-----------xilinx verilog----------
|
||||
# #puts "verilog file exist!"
|
||||
# vmap unisims_ver $VLOG_LIB/unisims_ver
|
||||
# vmap simprims_ver $VLOG_LIB/simprims_ver
|
||||
# vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
|
||||
# vmap unimacro_ver $VLOG_LIB/unimacro_ver
|
||||
# vmap secureip $VLOG_LIB/secureip
|
||||
# set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
|
||||
# }
|
||||
#}
|
||||
|
||||
set defs [dict create;] ;
|
||||
dict append defs CASE_NAME $CASE_NAME;
|
||||
dict append defs TOP_ENTITY $TOP_ENTITY;
|
||||
dict append defs TOP_INSTANCE $TOP_INSTANCE;
|
||||
dict append defs timing;
|
||||
dict append defs SIM_TIME $SIM_TIME ;
|
||||
|
||||
set def_string "";
|
||||
dict for {def_name def_value} $defs {
|
||||
set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
|
||||
}
|
||||
puts "the define string is:$def_string"
|
||||
|
||||
|
||||
#file delete -force work ;
|
||||
|
||||
vlib $WORK_LIB_DIR/${CASE_DIR};
|
||||
vmap work $WORK_LIB_DIR/${CASE_DIR};
|
||||
catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock } res;
|
||||
catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/ } res;
|
||||
|
||||
#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
|
||||
#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
|
||||
|
||||
#if {[info exists 1]} {
|
||||
# set SIM_TIME $1
|
||||
#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
|
||||
|
||||
|
||||
|
||||
#by default,all cases use the same source file list
|
||||
set VLOG_SOURCE_LIST ../file_ver.f;
|
||||
set VHDL_SOURCE_LIST ../file_vhd.f;
|
||||
|
||||
#we specify individual file list for single case
|
||||
if {[file exists file_ver.f ]} {
|
||||
puts "---->using case dependent verilog file list"
|
||||
set VLOG_SOURCE_LIST file_ver.f;
|
||||
}
|
||||
|
||||
if {[file exists file_vhd.f ]} {
|
||||
puts "---->using case dependent vhdl file list"
|
||||
set VHDL_SOURCE_LIST file_vhd.f;
|
||||
}
|
||||
|
||||
if {![string equal vhd $TOP_FILE_LANG]} {
|
||||
set GLBL glbl
|
||||
}
|
||||
|
||||
if {$SIM_TYPE == "timing"} {
|
||||
|
||||
set SDF_TYPE "-sdfmax";
|
||||
set SDFCOM_TYPE "-maxdelays";
|
||||
|
||||
puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
|
||||
if {[string equal $CORNER_TYPE "01_min" ]} {
|
||||
set SDF_TYPE "-sdfmin";
|
||||
set SDFCOM_TYPE "-mindelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
|
||||
} elseif {[string equal $CORNER_TYPE "02_type" ]} {
|
||||
set SDF_TYPE "-sdftyp";
|
||||
set SDFCOM_TYPE "-typdelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
|
||||
} elseif {[string equal $CORNER_TYPE "03_max" ]} {
|
||||
set SDF_TYPE "-sdfmax";
|
||||
set SDFCOM_TYPE "-maxdelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
|
||||
}
|
||||
|
||||
if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
|
||||
puts "++++++++++ develop kit is libero ++++++++++";
|
||||
} else {
|
||||
puts "++++++++++ develop kit is not libero ++++++++++";
|
||||
set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
|
||||
}
|
||||
|
||||
sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
|
||||
|
||||
#in timing simulation ,here only glbl may be compiled seperately
|
||||
if {[file exists ${VLOG_SOURCE_LIST}]} {
|
||||
vlog -incr -quiet -sv +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
|
||||
}
|
||||
|
||||
vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
|
||||
|
||||
vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
|
||||
|
||||
eval vopt ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
|
||||
+initmem+0 +initreg+0 +initwire+0;
|
||||
|
||||
|
||||
eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout \
|
||||
+no_notifier +no_tchk_msg\
|
||||
work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
|
||||
${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
|
||||
|
||||
do ../suppresswarning.tcl
|
||||
|
||||
|
||||
catch {run ${SIM_TIME} } res
|
||||
} else {
|
||||
|
||||
|
||||
#compile source files
|
||||
if {[file exists ${VLOG_SOURCE_LIST}]} {
|
||||
puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
|
||||
# vlog -incr -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
|
||||
vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
|
||||
}
|
||||
|
||||
|
||||
if {[file exists ${VHDL_SOURCE_LIST}]} {
|
||||
puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
|
||||
vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
|
||||
}
|
||||
|
||||
# eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
|
||||
# +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
|
||||
# +initmem+0 +initreg+0 +initwire+0 \
|
||||
# -suppress 2912 \
|
||||
# -suppress 1127
|
||||
|
||||
#to mask 211 error
|
||||
catch {
|
||||
if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
|
||||
eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
|
||||
-t 1ps -wlfopt -wlfcompress -nostdout \
|
||||
+initmem+0 +initreg+0 +initwire+0 \
|
||||
+no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
|
||||
-classdebug \
|
||||
glbl work.${CASE_NAME} \
|
||||
-wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
|
||||
} else {
|
||||
restart -f
|
||||
}
|
||||
} res;
|
||||
|
||||
do ../suppresswarning.tcl
|
||||
|
||||
catch {do wave.tcl} res
|
||||
|
||||
set TEMP_REF_FILES info.txt;
|
||||
write report -l $TEMP_REF_FILES
|
||||
|
||||
catch {run ${SIM_TIME} } res
|
||||
|
||||
do ../saveucdb.tcl
|
||||
#}
|
||||
|
||||
set current_path [pwd]
|
||||
puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
|
||||
20
new_project_rtl_template/sim/func001/runone.tcl
Normal file
20
new_project_rtl_template/sim/func001/runone.tcl
Normal file
@@ -0,0 +1,20 @@
|
||||
quit -sim
|
||||
cd ..
|
||||
|
||||
#clear the simulator transcript window and make the wave,data & coverage director
|
||||
.main clear
|
||||
|
||||
set wrap_args [list];
|
||||
#put the do command $1-$9 to list,because we can't use the argv,we should construct the "argv" mannully.
|
||||
for {set i 1} {$i <= $argc} {incr i 1} {
|
||||
lappend wrap_args [set $i];
|
||||
}
|
||||
|
||||
#echo $args
|
||||
|
||||
eval do runone.tcl $wrap_args
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
7
new_project_rtl_template/sim/func001/save.tcl
Normal file
7
new_project_rtl_template/sim/func001/save.tcl
Normal file
@@ -0,0 +1,7 @@
|
||||
if {$argc>=1} {
|
||||
catch {write format wave -window Wave $1.tcl} res
|
||||
} else {
|
||||
catch {write format wave -window Wave case.tcl} res
|
||||
}
|
||||
|
||||
|
||||
114
new_project_rtl_template/sim/func001/savewave.tcl
Normal file
114
new_project_rtl_template/sim/func001/savewave.tcl
Normal file
@@ -0,0 +1,114 @@
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {true} {
|
||||
# raw script code in pre_format
|
||||
set pre_format {
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
}
|
||||
}; list
|
||||
# from stackoverflow.com "how to keep commands quiet in TCL?"
|
||||
# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
|
||||
# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
|
||||
# for instance: set a [open "giri.txt" r]; list
|
||||
|
||||
if {true} {
|
||||
# raw script code in post_format
|
||||
set post_format {
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
}
|
||||
}; list
|
||||
|
||||
# support save format when only open .wlf instead of run a case
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
|
||||
# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
|
||||
if {true} {
|
||||
# save current wave format to a tmp file
|
||||
catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
|
||||
|
||||
if {$argc>=1} { # example: do savewave.tcl wave_name
|
||||
set wave_name $1
|
||||
if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
|
||||
# replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
|
||||
while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
|
||||
regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
|
||||
}
|
||||
} elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
|
||||
# nop
|
||||
} else {
|
||||
echo "Invalid file name $wave_name!"
|
||||
return
|
||||
}
|
||||
set fd_wave [open $wave_name.tcl w]
|
||||
echo "Wave format saved to $wave_name.tcl"
|
||||
} else { # example: do savewave.tcl
|
||||
set fd_wave [open wave1.tcl w]
|
||||
echo "Wave format saved to wave1.tcl"
|
||||
}
|
||||
|
||||
set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
|
||||
|
||||
# put lines in pre_format to final file(the file specified in argument $1)
|
||||
set lines [split $pre_format "\n"]
|
||||
set total_lines [llength $lines]
|
||||
for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
|
||||
set wave_format_line [lindex $lines $line_idx]
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
# put lines in tmp file to final file(the file specified in argument $1)
|
||||
while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
|
||||
if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
|
||||
# if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
|
||||
regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
|
||||
# and then add eval in the biginning
|
||||
regsub (^) $wave_format_line {eval } wave_format_line
|
||||
}
|
||||
# make virtual signal ok
|
||||
if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
|
||||
regsub -all {\{} $wave_format_line {[subst &} wave_format_line
|
||||
regsub -all {\}} $wave_format_line {&]} wave_format_line
|
||||
}
|
||||
regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
# put lines in post_format to final file(the file specified in argument $1)
|
||||
set lines [split $post_format "\n"]
|
||||
set total_lines [llength $lines]
|
||||
for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
|
||||
set wave_format_line [lindex $lines $line_idx]
|
||||
chan puts $fd_wave $wave_format_line
|
||||
}
|
||||
|
||||
close $fd_wave
|
||||
close $fd_intermediate_wave_format_file
|
||||
}
|
||||
235
new_project_rtl_template/sim/func001/tb.sv
Normal file
235
new_project_rtl_template/sim/func001/tb.sv
Normal file
@@ -0,0 +1,235 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module
|
||||
`CASE_NAME();
|
||||
`include "../instantiate_top.sv"
|
||||
|
||||
final mti_fli::mti_Cmd("do ../saveucdb.tcl");
|
||||
|
||||
initial begin
|
||||
$fsdbDumpfile("fsdb_wave.fsdb");
|
||||
$fsdbDumpvars;
|
||||
end
|
||||
|
||||
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||||
/*to end the simulation commandary*/
|
||||
/*if you want to end the simulation case by case,just comment the line
|
||||
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||||
//TODO:
|
||||
|
||||
logic apb_uart_irq;
|
||||
logic apb_uart_rda; // rx data avaiable
|
||||
logic apb_uart_tde; // tx data empty
|
||||
|
||||
logic apb_uart_req;
|
||||
logic apb_uart_write;
|
||||
logic [16-1:0] apb_uart_addr;
|
||||
logic [32-1:0] apb_uart_wdata;
|
||||
logic [32-1:0] apb_uart_rdata;
|
||||
logic apb_uart_ready;
|
||||
|
||||
logic [16-1:0] apb_uart_paddr;
|
||||
logic apb_uart_psel;
|
||||
logic apb_uart_penable;
|
||||
logic apb_uart_pwrite;
|
||||
logic [32-1:0] apb_uart_pwdata;
|
||||
|
||||
logic [32-1:0] apb_uart_prdata;
|
||||
logic apb_uart_pready;
|
||||
|
||||
// instance vip
|
||||
vip_clock # (.FREQUENCY_MHZ(50)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
|
||||
|
||||
apb_uart_top tb_apb_uart_top(
|
||||
.CLK (clk),
|
||||
.RSTN (rstn),
|
||||
/* verilator lint_off UNUSED */
|
||||
.PADDR (apb_uart_paddr),
|
||||
/* lint_on */
|
||||
.PWDATA (apb_uart_pwdata),
|
||||
.PWRITE (apb_uart_pwrite),
|
||||
.PSEL (apb_uart_psel),
|
||||
.PENABLE (apb_uart_penable),
|
||||
.PRDATA (apb_uart_prdata),
|
||||
.PREADY (apb_uart_pready),
|
||||
.PSLVERR (),
|
||||
|
||||
.rx_i (uart_tx), // Receiver input
|
||||
.tx_o (uart_rx), // Transmitter output
|
||||
|
||||
.rda_o (apb_uart_rda), // rx data avaiable
|
||||
.tde_o (apb_uart_tde), // tx data empty
|
||||
.event_o (apb_uart_irq) // interrupt/event output
|
||||
);
|
||||
|
||||
apbmif tb_apb_uart_apbmif(
|
||||
.req (apb_uart_req),
|
||||
.write (apb_uart_write),
|
||||
.addr (apb_uart_addr),
|
||||
.wdata (apb_uart_wdata),
|
||||
.rdata (apb_uart_rdata),
|
||||
.ready (apb_uart_ready),
|
||||
// APB interface
|
||||
.PRESETn (rstn),
|
||||
.PCLK (clk),
|
||||
// APB master
|
||||
.PADDR (apb_uart_paddr),
|
||||
.PSEL (apb_uart_psel),
|
||||
.PENABLE (apb_uart_penable),
|
||||
.PWRITE (apb_uart_pwrite),
|
||||
.PSTRB (),
|
||||
.PWDATA (apb_uart_pwdata),
|
||||
|
||||
.PRDATA (apb_uart_prdata),
|
||||
.PREADY (apb_uart_pready)
|
||||
);
|
||||
|
||||
logic [4:0] ehex;
|
||||
logic ehex_valid;
|
||||
|
||||
logic cli_poll;
|
||||
logic echo_push;
|
||||
|
||||
logic run_priority ;
|
||||
logic cli_poll_pending ;
|
||||
logic echo_push_pending;
|
||||
|
||||
logic apb_uart_ready_d1;
|
||||
logic apb_uart_read_done;
|
||||
logic apb_uart_write_done;
|
||||
logic apb_uart_is_reading;
|
||||
|
||||
always_ff @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
apb_uart_ready_d1 <= 1'b1;
|
||||
end else begin
|
||||
apb_uart_ready_d1 <= apb_uart_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign apb_uart_read_done = apb_uart_is_reading && apb_uart_ready && !apb_uart_ready_d1;
|
||||
assign apb_uart_write_done = !apb_uart_is_reading && apb_uart_ready && !apb_uart_ready_d1;
|
||||
|
||||
always_ff @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
apb_uart_req <= 0;
|
||||
apb_uart_write <= 0;
|
||||
apb_uart_addr <= 0;
|
||||
run_priority <= 0; // 0: read; 1: write;
|
||||
cli_poll_pending <= 0;
|
||||
echo_push_pending <= 0;
|
||||
apb_uart_is_reading <= 0;
|
||||
end else begin
|
||||
if (cli_poll)
|
||||
cli_poll_pending <= 1'b1;
|
||||
if (echo_push)
|
||||
echo_push_pending <= 1'b1;
|
||||
|
||||
apb_uart_req <= 0;
|
||||
apb_uart_write <= 0;
|
||||
|
||||
if (apb_uart_ready) begin
|
||||
if (cli_poll_pending && !echo_push_pending) begin // read
|
||||
cli_poll_pending <= 1'b0;
|
||||
run_priority <= 1'b1; // next time write first
|
||||
apb_uart_req <= 1'b1;
|
||||
apb_uart_write <= 1'b0;
|
||||
apb_uart_addr <= 0;
|
||||
apb_uart_is_reading <= 1'b1;
|
||||
end else if (!cli_poll_pending && echo_push_pending) begin // write
|
||||
echo_push_pending <= 1'b0;
|
||||
run_priority <= 1'b0; // next time read first
|
||||
apb_uart_req <= 1'b1;
|
||||
apb_uart_write <= 1'b1;
|
||||
apb_uart_addr <= 0;
|
||||
apb_uart_is_reading <= 0;
|
||||
end else if (cli_poll_pending && echo_push_pending) begin
|
||||
if (run_priority) begin // write
|
||||
echo_push_pending <= 1'b0;
|
||||
run_priority <= 1'b0; // next time read first
|
||||
apb_uart_req <= 1'b1;
|
||||
apb_uart_write <= 1'b1;
|
||||
apb_uart_addr <= 0;
|
||||
apb_uart_is_reading <= 0;
|
||||
end else begin // read
|
||||
cli_poll_pending <= 1'b0;
|
||||
run_priority <= 1'b1; // next time write first
|
||||
apb_uart_req <= 1'b1;
|
||||
apb_uart_write <= 1'b0;
|
||||
apb_uart_addr <= 0;
|
||||
apb_uart_is_reading <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
rstn = 0;
|
||||
#1us rstn = 1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
int uart_recv = $fopen("uart_recv.log");
|
||||
cli_poll = 0;
|
||||
#1ns;
|
||||
@(posedge rstn);
|
||||
forever begin
|
||||
wait (apb_uart_rda == 1'b1);
|
||||
@(posedge clk);
|
||||
fork
|
||||
cli_poll = 1'b1;
|
||||
@(posedge clk) cli_poll = 1'b0;
|
||||
join_none
|
||||
@(posedge apb_uart_read_done) $fwrite(uart_recv, "%s", apb_uart_rdata[7:0]);
|
||||
@(negedge apb_uart_rda);
|
||||
end
|
||||
end
|
||||
|
||||
task send_cmd(input string cmd);
|
||||
begin
|
||||
foreach(cmd[i]) begin
|
||||
wait (apb_uart_tde == 1'b1);
|
||||
@(posedge clk);
|
||||
echo_push = 1'b1;
|
||||
apb_uart_wdata = cmd[i];
|
||||
@(posedge clk) echo_push = 1'b0;
|
||||
@(negedge apb_uart_tde);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
echo_push = 0;
|
||||
#1ns;
|
||||
@(posedge rstn);
|
||||
#1ms;
|
||||
send_cmd("\x03");
|
||||
#5ms;
|
||||
send_cmd("\x03");
|
||||
#5ms;
|
||||
send_cmd("\n");
|
||||
#1ms;
|
||||
send_cmd("w");
|
||||
#1ms;
|
||||
send_cmd("\n");
|
||||
send_cmd("w 0 beef1111 beef2222 beef3333 beef4444\n");
|
||||
send_cmd("w 10 beef5555 beef6666 beef7777 beef8888\n");
|
||||
send_cmd("r 0 -s 8 -t a\n");
|
||||
#25ms;
|
||||
send_cmd("\x03");
|
||||
#5ms;
|
||||
send_cmd("\x03");
|
||||
#5ms;
|
||||
send_cmd("\x03");
|
||||
#5ms;
|
||||
send_cmd("r 0 -s 2\n");
|
||||
#5ms;
|
||||
send_cmd("r 8 -s 2\n");
|
||||
#5ms;
|
||||
send_cmd("r 10 -s\n");
|
||||
#5ms;
|
||||
send_cmd("r 10 -s -s\n");
|
||||
end
|
||||
|
||||
endmodule
|
||||
29
new_project_rtl_template/sim/func001/vip_clock.sv
Normal file
29
new_project_rtl_template/sim/func001/vip_clock.sv
Normal file
@@ -0,0 +1,29 @@
|
||||
module vip_clock
|
||||
#(
|
||||
parameter FREQUENCY_MHZ = 1,
|
||||
parameter PHASE_DEGREE = 0
|
||||
)
|
||||
(
|
||||
input int duty_percent = 50,//dynamical parameter
|
||||
input int jitter_percent = 0,//dynamical parameter
|
||||
output clk
|
||||
);
|
||||
|
||||
|
||||
|
||||
logic ideal_clk;
|
||||
|
||||
initial begin
|
||||
ideal_clk = 0;
|
||||
#(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
|
||||
forever begin
|
||||
ideal_clk = 0;
|
||||
#(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);
|
||||
|
||||
ideal_clk = 1;
|
||||
#(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
|
||||
end
|
||||
end
|
||||
|
||||
assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk = ideal_clk;
|
||||
endmodule
|
||||
75
new_project_rtl_template/sim/func001/wave.tcl
Normal file
75
new_project_rtl_template/sim/func001/wave.tcl
Normal file
@@ -0,0 +1,75 @@
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
|
||||
#preset envieroment variables
|
||||
if {[info exists SIM_TYPE] && $SIM_TYPE == "timing"} {
|
||||
|
||||
} else {
|
||||
|
||||
puts "---->checing the simulator status to decide whether to restore the wave session.................."
|
||||
puts "---->the runstatus is :[runStatus]"
|
||||
#if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "error" ]} {
|
||||
puts "---->trying restore to saved wave window.................."
|
||||
|
||||
catch {
|
||||
set size [file size lastwave.tcl];
|
||||
#check if size is too much
|
||||
if($size > (10*1024){
|
||||
puts "lastwave.tcl size is $size,try to recover"
|
||||
do lastwave.tcl
|
||||
}
|
||||
} res;
|
||||
#}
|
||||
|
||||
|
||||
# catch {log -mvcreccomplete -r -depth 6 /* } res
|
||||
|
||||
catch {log -mvcreccomplete -r -depth 6 /$CASE_NAME/*} res
|
||||
catch {log -mvcreccomplete -r -depth 6 /$CASE_NAME/$TOP_INSTANCE/*} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/CENTRAL_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/TRAIN_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/SEQUENCER_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/GENIMGVAL_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGRXDATA_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_AREF_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_INIT_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_READ_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_WRITE_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instLow} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/SDRAM_FRMRDCTRL_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGTX_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/IMGSPI_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/COMMANDHANDLER_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/ERUPRAMCAL_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/ERUPSUM_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/FRMHEADWR_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/GUIDEPIEZORX_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/STATE_RETURN_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/TEMP461_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res
|
||||
# catch {log -mvcreccomplete -r -depth 4 /$CASE_NAME/$TOP_INSTANCE/TIMEPRO_inst} res
|
||||
|
||||
|
||||
|
||||
# log -class pkg_uart::uart
|
||||
# catch {class/pkg_uart::uart::uart__2} res;
|
||||
}
|
||||
142
new_project_rtl_template/sim/func001/wave1.tcl
Normal file
142
new_project_rtl_template/sim/func001/wave1.tcl
Normal file
@@ -0,0 +1,142 @@
|
||||
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/CLK
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/RSTN
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PADDR
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PWDATA
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PWRITE
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PSEL
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PENABLE
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PRDATA
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PREADY
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/PSLVERR
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_i
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_o
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rda_o
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tde_o
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/event_o
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/register_adr
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/regs_q
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/regs_n
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/trigger_level_n
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/trigger_level_q
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/parity_error
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_overrun
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/IIR_o
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/clr_int
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/apb_rx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_fifo_clr_n
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_fifo_clr_q
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_fifo_clr_n
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_fifo_clr_q
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_tx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_rx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_rx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_rx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_tx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_elements
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/rx_elements
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/write
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/addr
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/rdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PRESETn
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PCLK
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PADDR
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PSEL
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PENABLE
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PWRITE
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PSTRB
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PWDATA
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PRDATA
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/PREADY
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_apbmif/STATE
|
||||
add wave -noupdate /$CASE_NAME/uart_read_done
|
||||
add wave -noupdate /$CASE_NAME/uart_rdata
|
||||
add wave -noupdate /$CASE_NAME/uart_ready
|
||||
add wave -noupdate /$CASE_NAME/uart_ready_d1
|
||||
add wave -noupdate /$CASE_NAME/uart_is_reading
|
||||
add wave -noupdate /$CASE_NAME/cli_poll
|
||||
add wave -noupdate /$CASE_NAME/uart_rda
|
||||
add wave -noupdate /$CASE_NAME/echo_push
|
||||
add wave -noupdate /$CASE_NAME/uart_tde
|
||||
add wave -noupdate /$CASE_NAME/uart_wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/exec_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/ehex
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/ehex_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_rda
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_rdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_read_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_is_reading
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/op_code
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/op_addr_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/rcnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/read_size_latch
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/timer_en
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_data_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/tx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_tx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_apb_uart/fifo_tx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_write
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_push
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_push_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_poll
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_poll_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_char
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/hex2char_req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_rdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/char_cnt
|
||||
eval TreeUpdate \[SetDefaultTree\]
|
||||
WaveRestoreCursors {{Cursor 1} {1606410000 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 427
|
||||
configure wave -valuecolwidth 142
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {950499888 ps} {2263000112 ps}
|
||||
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
|
||||
104
new_project_rtl_template/sim/func001/wave2.tcl
Normal file
104
new_project_rtl_template/sim/func001/wave2.tcl
Normal file
@@ -0,0 +1,104 @@
|
||||
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/exec_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_tx
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/uart_rx
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/read_period
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/read_period_latch
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_abort_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_enter_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_err_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_read_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_write_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_ctrlc_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_prompt_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_mem_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/timeout
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/timer_en
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/hex2char_req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_push
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_char
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_rdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_data_latch
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_buf
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_poll
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_poll_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_push_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_is_reading
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_read_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_write_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/strlen
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/char_cnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_write
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_rdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/uart_rda
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/word_cnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data0
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data1
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data2
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data3
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data4
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data5
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data6
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/data7
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/rcnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/wcnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/ehex_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/ehex
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/option_s_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/read_size
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/read_size_latch
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/op_addr
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/op_addr_latch
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_req
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_write
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u0_module/u_regfile/addr
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/apb_addr
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/led
|
||||
eval TreeUpdate \[SetDefaultTree\]
|
||||
WaveRestoreCursors {{Cursor 1} {44875450000 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 429
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {44875169561 ps} {44875810439 ps}
|
||||
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
|
||||
66
new_project_rtl_template/sim/func001/wave3.tcl
Normal file
66
new_project_rtl_template/sim/func001/wave3.tcl
Normal file
@@ -0,0 +1,66 @@
|
||||
|
||||
# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
|
||||
if {![info exists CASE_NAME]} {
|
||||
puts "++++++++++ search case name ++++++++++"
|
||||
set wave_sim_type func
|
||||
for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
|
||||
set wave_case_num [format "%03d" $wave_i];
|
||||
set wave_case_name ${wave_sim_type}${wave_case_num}
|
||||
if {[search structure $wave_case_name] >= 0} {
|
||||
break
|
||||
}
|
||||
}
|
||||
set unset_CASE_NAME true
|
||||
set CASE_NAME $wave_case_name
|
||||
}
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/exec_state
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_abort_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_read_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cmd_write_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_ctrlc_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_enter_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_err_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_mem_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/echo_split_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_push
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_push_pending
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_wdata
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/cli_write_done
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/char_cnt
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/rx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/rx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/rx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/tx_data
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/tx_ready
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/tx_valid
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/errno
|
||||
add wave -noupdate /$CASE_NAME/u0_top_module/u_debug_hub/u0_debug_cli/ehex
|
||||
eval TreeUpdate \[SetDefaultTree\]
|
||||
WaveRestoreCursors {{Cursor 1} {1171070000 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 469
|
||||
configure wave -valuecolwidth 99
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {1170929782 ps} {1171250218 ps}
|
||||
|
||||
if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
|
||||
set unset_CASE_NAME false
|
||||
unset CASE_NAME
|
||||
}
|
||||
|
||||
39
new_project_rtl_template/sim/functions.tcl
Normal file
39
new_project_rtl_template/sim/functions.tcl
Normal file
@@ -0,0 +1,39 @@
|
||||
#usage: "do xxx.tcl timing" for timing simulation and "do xxx.tcl" for functional simulation
|
||||
|
||||
#get the current script file name by [info frame],walk through all frame return lines
|
||||
#here we use the "do ..." command to start this script,so we can't use the [info script]
|
||||
#command to start this script
|
||||
#with the "do ..." command,we can start this script with command line options,and we
|
||||
#can refercen these options by $1,$2,etc.
|
||||
proc get_file_name { } {
|
||||
|
||||
set file_name 0
|
||||
catch {
|
||||
set max_info [info frame]
|
||||
puts "maxinfo=$max_info"
|
||||
puts "...................................."
|
||||
for {set a $max_info} {$a>0} {incr a -1} {
|
||||
puts $a
|
||||
set framestring [info frame $a];
|
||||
puts $framestring;
|
||||
set cmdstring [dict get $framestring cmd]; #extract command with "cmd" key
|
||||
if {[string match *case*.tcl* $cmdstring]} { #search "do xxx.tcl timing" patten
|
||||
puts $cmdstring
|
||||
set ary [split $cmdstring " "]
|
||||
puts $ary
|
||||
set file_name [lindex $ary 1]
|
||||
puts $file_name
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
return $file_name
|
||||
}
|
||||
|
||||
|
||||
proc get_case_num {case_name} {
|
||||
regsub {[a-z]*} $case_name {} case_num
|
||||
# puts $case_num
|
||||
return $case_num
|
||||
}
|
||||
|
||||
66
new_project_rtl_template/sim/glbl.v
Normal file
66
new_project_rtl_template/sim/glbl.v
Normal file
@@ -0,0 +1,66 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (weak1, weak0) GSR = GSR_int;
|
||||
assign (weak1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
56
new_project_rtl_template/sim/globalset.tcl
Normal file
56
new_project_rtl_template/sim/globalset.tcl
Normal file
@@ -0,0 +1,56 @@
|
||||
|
||||
|
||||
#TODO:set the top module name with extention
|
||||
set TOP_FILE top_module.sv
|
||||
|
||||
#TODO:set the top entity architecuture,vhdl file only;If the top module file is verilog,just ignore this var
|
||||
set TOP_VHD_ARCH Behavioral
|
||||
|
||||
#TODO:set the coverage collect option
|
||||
set COVERAGE_OPTION sbfce
|
||||
|
||||
#TODO:set the root path of simlation library,relative to the run.tcl
|
||||
set SIM_LIB_ROOT ../../../../../../03_simlib
|
||||
#set SIM_LIB_ROOT d:/02_work/simlib
|
||||
|
||||
#TODO:sset the simulator excutable path
|
||||
set SIM_TOOL_PATH c:/questasim64_10.7
|
||||
|
||||
#TODO: device family, microsemi/actel only
|
||||
set ACTEL_FAMILY proasic3l
|
||||
|
||||
#TODO:set simulator name
|
||||
set SIMULATOR questasim
|
||||
#TODO:set simulator verion
|
||||
set SIMULATOR_VER 10.7
|
||||
#TODO:set simulator platform
|
||||
set SIMULATOR_PLATFORM nt64
|
||||
#TODO:set fpga par tools
|
||||
set FPGA_KIT_VER libero11.8
|
||||
#TODO:set vhdl library full path
|
||||
#set VHDL_LIB $SIM_LIB_ROOT/vhdl/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
|
||||
#TODO:set verilog library full pth
|
||||
#set VLOG_LIB $SIM_LIB_ROOT/verilog/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
|
||||
|
||||
|
||||
file mkdir coverage
|
||||
file mkdir wave
|
||||
file mkdir data
|
||||
file mkdir work
|
||||
|
||||
#DO NOT MODIFYset the coverage data dirctory,relative to the run.tcl
|
||||
set COVERAGE_OUTPUT_DIR ../coverage
|
||||
#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
|
||||
set WAVE_OUTPUT_DIR ../wave
|
||||
#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
|
||||
set WORK_LIB_DIR ../work
|
||||
#DO NOT MODIFYget the top most module name
|
||||
set TOP_ENTITY [file rootname ${TOP_FILE}]
|
||||
#DO NOT MODIFYget the top most module language,vhdl or verilog
|
||||
set TOP_FILE_LANG [file extension ${TOP_FILE}]
|
||||
#DO NOT MODIFYse the top most instance name,with "u0_" prefix
|
||||
set TOP_INSTANCE u0_${TOP_ENTITY}
|
||||
|
||||
|
||||
|
||||
|
||||
27
new_project_rtl_template/sim/instantiate_top.sv
Normal file
27
new_project_rtl_template/sim/instantiate_top.sv
Normal file
@@ -0,0 +1,27 @@
|
||||
/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/
|
||||
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||||
/*add all port here*/
|
||||
/*use "logic" to replace "logic" and "logic" ports*/
|
||||
/*use "wire" to replace "inout" ports*/
|
||||
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||||
//TODO:
|
||||
|
||||
logic clk;
|
||||
logic rstn;
|
||||
|
||||
logic uart_rx;
|
||||
logic uart_tx;
|
||||
|
||||
logic [7:0] led;
|
||||
|
||||
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||||
/*initialize all "logic" ports here
|
||||
/*all inputs default as 0,modify if necessary
|
||||
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||||
//TODO:
|
||||
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||||
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||||
|
||||
/*do not modify
|
||||
*/
|
||||
`TOP_ENTITY `TOP_INSTANCE(.*);
|
||||
16
new_project_rtl_template/sim/mergeucdb.tcl
Normal file
16
new_project_rtl_template/sim/mergeucdb.tcl
Normal file
@@ -0,0 +1,16 @@
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
source globalset.tcl
|
||||
|
||||
if {[info exists TOP_FILE_LANG] && ![string compare ${TOP_FILE_LANG} ".vhd"]} {
|
||||
vcover merge -stats=none -strip 0 -du [string tolower ${TOP_ENTITY}]([string tolower ${TOP_VHD_ARCH}]) -recursive -totals merge.ucdb ./coverage/*.ucdb
|
||||
} else {
|
||||
vcover merge -stats=none -strip 0 -du ${TOP_ENTITY} -recursive -totals merge.ucdb ./coverage/*.ucdb
|
||||
}
|
||||
2037
new_project_rtl_template/sim/modelsim.ini
Normal file
2037
new_project_rtl_template/sim/modelsim.ini
Normal file
File diff suppressed because it is too large
Load Diff
147
new_project_rtl_template/sim/parse_args.tcl
Normal file
147
new_project_rtl_template/sim/parse_args.tcl
Normal file
@@ -0,0 +1,147 @@
|
||||
|
||||
set SIM_TYPE func ;
|
||||
set CASE_NUM 1 ;
|
||||
set SIM_TIME 100sec ;#as all
|
||||
set CORNER_TYPE max ;
|
||||
set COPY_RUN_TEMPLATE no;
|
||||
|
||||
#declear a empty list
|
||||
|
||||
set args [list];
|
||||
#put the do command $1-$9 to list,because we can't use the argv,we should construct the "argv" mannully.
|
||||
for {set i 1} {$i <= $argc} {incr i 1} {
|
||||
lappend args [set $i];
|
||||
}
|
||||
puts "---->parsing the command line....argc=$argc,args=$args*************************"
|
||||
|
||||
#get the max index of the list,the "expr" command should be use to calculate out the express
|
||||
set max_index [expr $argc-1];
|
||||
|
||||
#search copy templation option
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-c"]} {
|
||||
set COPY_RUN_TEMPLATE yes
|
||||
puts "whether to copy run.tcl template=$COPY_RUN_TEMPLATE"
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#search generate instantiate_top.sv opton
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-g"]} {
|
||||
set GEN_INSTANTIATE_TOP yes
|
||||
puts "force generate instantiate_top.sv and override exist file"
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#search case number
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
set para [lindex $args $i];
|
||||
if {[string equal $para "-n"] } {
|
||||
|
||||
if {$i < $max_index} {
|
||||
set num [lindex $args [expr [expr $i+1]]];
|
||||
if { [string is digit $num] } {
|
||||
set CASE_NUM [format "%03d" $num];
|
||||
puts "case number=$CASE_NUM"
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#search simulation time
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-t"]} {
|
||||
if {$i < $max_index} {
|
||||
set time [lindex $args [expr $i+1]]
|
||||
if {[regexp {^[0-9]+((n|u|m)s|sec)$} $time]} {
|
||||
set SIM_TIME $time
|
||||
puts "simulation time=$SIM_TIME"
|
||||
} else {
|
||||
puts "unknow simulation time,set to 1us"
|
||||
set SIM_TIME 1us
|
||||
puts "simulation time=$SIM_TIME"
|
||||
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#search simulation type
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-timing"]} {
|
||||
set SIM_TYPE "timing"
|
||||
puts "simulation type=$SIM_TYPE"
|
||||
break;
|
||||
} elseif {[string equal $para "-func"]} {
|
||||
set SIM_TYPE "func"
|
||||
puts "simulation type=$SIM_TYPE"
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#search corner type
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-corner"]} {
|
||||
if {$i < $max_index } {
|
||||
set corner [lindex $args [expr $i+1]]
|
||||
|
||||
#处理run.tcl中再次调用本脚本导致的bug ,删除前导的数字
|
||||
regsub -nocase {[0-9]+_} $corner "" corner
|
||||
|
||||
switch -glob $corner {
|
||||
"max" {
|
||||
set CORNER_TYPE 03_max
|
||||
}
|
||||
"min" {
|
||||
set CORNER_TYPE 01_min
|
||||
}
|
||||
"type" {
|
||||
set CORNER_TYPE 02_type
|
||||
}
|
||||
default {
|
||||
puts "unknow corner type,set to 03_max"
|
||||
set CORNER_TYPE 03_max
|
||||
}
|
||||
|
||||
}
|
||||
puts "corner type=$CORNER_TYPE"
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#search simulation type
|
||||
for {set i 0} {$i < $argc} {incr i 1} {
|
||||
|
||||
set para [lindex $args $i]
|
||||
if {[string equal $para "-h"]} {
|
||||
puts "------------------------help------------------------"
|
||||
puts "-n x:specify case number to be excuted,x stand for case number,default to 0"
|
||||
puts "-t x:specify simulation time to be excuted,x stand for time,unit may be ns,us,ms,sec,default to 1us"
|
||||
puts "-timing:specify to excute in timing simulation mode"
|
||||
puts "-corner x:specify the timing simulation corner,may be max,min,type,default to max"
|
||||
puts "-c:force to override run.tcl scripts in case directory,be carefull"
|
||||
puts "-h:to display this help information,it has the highest priority,thus block other options"
|
||||
puts "----------------------------------------------------"
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
puts "---->parsing the command line complete ***************************"
|
||||
227
new_project_rtl_template/sim/run_template.tcl
Normal file
227
new_project_rtl_template/sim/run_template.tcl
Normal file
@@ -0,0 +1,227 @@
|
||||
#quit -sim
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#unbound the the "work" lib dir from vsim,to remove it
|
||||
|
||||
#when error do not save wave list
|
||||
if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
|
||||
source savewave.tcl
|
||||
}
|
||||
#catch {q -sim} res
|
||||
#dataset close -all
|
||||
|
||||
echo on
|
||||
.main clear
|
||||
|
||||
puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
|
||||
|
||||
vmap std $SIM_TOOL_PATH/std ;
|
||||
vmap ieee $SIM_TOOL_PATH/ieee ;
|
||||
|
||||
set FUNC_SOURCE_DIR ../../../01_source/01_func
|
||||
set TIMING_SOURCE_DIR ../../../01_source/02_timing
|
||||
|
||||
set source_vhdl false
|
||||
set source_verilog false
|
||||
|
||||
set LIB_OPTION ""
|
||||
set LOG_OPTION ""
|
||||
|
||||
#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
|
||||
# #-----------actel----------
|
||||
# #puts "IDE IS $FPGA_KIT_VER!"
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
|
||||
# set LOG_OPTION "-vhdlvariablelogging"
|
||||
# }
|
||||
# if {[string equal -nocase vhd $TOP_FILE_LANG]} {
|
||||
# vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
|
||||
# } else {
|
||||
# vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
|
||||
# }
|
||||
# set LIB_OPTION "-L ${ACTEL_FAMILY}"
|
||||
#
|
||||
#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
|
||||
# #puts "IDE IS $FPGA_KIT_VER!"
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
|
||||
# set source_vhdl true
|
||||
# set LOG_OPTION "-vhdlvariablelogging"
|
||||
# }
|
||||
# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
|
||||
# set source_verilog true
|
||||
# }
|
||||
# if { [string equal -nocase true $source_vhdl] } {
|
||||
# #-----------xilinx vhdl----------
|
||||
# #puts "vhdl file exist!"
|
||||
# vmap simprim $VHDL_LIB/simprim
|
||||
# vmap unisim $VHDL_LIB/unisim
|
||||
# vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
|
||||
# vmap unimacro $VHDL_LIB/unimacro
|
||||
# set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
|
||||
# }
|
||||
#
|
||||
# if { [string equal -nocase true $source_verilog] } {
|
||||
# #-----------xilinx verilog----------
|
||||
# #puts "verilog file exist!"
|
||||
# vmap unisims_ver $VLOG_LIB/unisims_ver
|
||||
# vmap simprims_ver $VLOG_LIB/simprims_ver
|
||||
# vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
|
||||
# vmap unimacro_ver $VLOG_LIB/unimacro_ver
|
||||
# vmap secureip $VLOG_LIB/secureip
|
||||
# set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
|
||||
# }
|
||||
#}
|
||||
|
||||
set defs [dict create;] ;
|
||||
dict append defs CASE_NAME $CASE_NAME;
|
||||
dict append defs TOP_ENTITY $TOP_ENTITY;
|
||||
dict append defs TOP_INSTANCE $TOP_INSTANCE;
|
||||
dict append defs timing;
|
||||
dict append defs SIM_TIME $SIM_TIME ;
|
||||
|
||||
set def_string "";
|
||||
dict for {def_name def_value} $defs {
|
||||
set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
|
||||
}
|
||||
puts "the define string is:$def_string"
|
||||
|
||||
|
||||
#file delete -force work ;
|
||||
|
||||
vlib $WORK_LIB_DIR/${CASE_DIR};
|
||||
vmap work $WORK_LIB_DIR/${CASE_DIR};
|
||||
catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock } res;
|
||||
catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/ } res;
|
||||
|
||||
#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
|
||||
#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
|
||||
|
||||
#if {[info exists 1]} {
|
||||
# set SIM_TIME $1
|
||||
#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
|
||||
|
||||
|
||||
|
||||
#by default,all cases use the same source file list
|
||||
set VLOG_SOURCE_LIST ../file_ver.f;
|
||||
set VHDL_SOURCE_LIST ../file_vhd.f;
|
||||
|
||||
#we specify individual file list for single case
|
||||
if {[file exists file_ver.f ]} {
|
||||
puts "---->using case dependent verilog file list"
|
||||
set VLOG_SOURCE_LIST file_ver.f;
|
||||
}
|
||||
|
||||
if {[file exists file_vhd.f ]} {
|
||||
puts "---->using case dependent vhdl file list"
|
||||
set VHDL_SOURCE_LIST file_vhd.f;
|
||||
}
|
||||
|
||||
if {![string equal vhd $TOP_FILE_LANG]} {
|
||||
set GLBL glbl
|
||||
}
|
||||
|
||||
if {$SIM_TYPE == "timing"} {
|
||||
|
||||
set SDF_TYPE "-sdfmax";
|
||||
set SDFCOM_TYPE "-maxdelays";
|
||||
|
||||
puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
|
||||
if {[string equal $CORNER_TYPE "01_min" ]} {
|
||||
set SDF_TYPE "-sdfmin";
|
||||
set SDFCOM_TYPE "-mindelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
|
||||
} elseif {[string equal $CORNER_TYPE "02_type" ]} {
|
||||
set SDF_TYPE "-sdftyp";
|
||||
set SDFCOM_TYPE "-typdelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
|
||||
} elseif {[string equal $CORNER_TYPE "03_max" ]} {
|
||||
set SDF_TYPE "-sdfmax";
|
||||
set SDFCOM_TYPE "-maxdelays";
|
||||
puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
|
||||
}
|
||||
|
||||
if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
|
||||
puts "++++++++++ develop kit is libero ++++++++++";
|
||||
} else {
|
||||
puts "++++++++++ develop kit is not libero ++++++++++";
|
||||
set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
|
||||
}
|
||||
|
||||
sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
|
||||
|
||||
#in timing simulation ,here only glbl may be compiled seperately
|
||||
if {[file exists ${VLOG_SOURCE_LIST}]} {
|
||||
vlog -incr -quiet -sv +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
|
||||
}
|
||||
|
||||
vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
|
||||
|
||||
vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
|
||||
|
||||
eval vopt ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
|
||||
+initmem+0 +initreg+0 +initwire+0;
|
||||
|
||||
|
||||
eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout \
|
||||
+no_notifier +no_tchk_msg\
|
||||
work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
|
||||
${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
|
||||
|
||||
do ../suppresswarning.tcl
|
||||
|
||||
|
||||
catch {run ${SIM_TIME} } res
|
||||
} else {
|
||||
|
||||
|
||||
#compile source files
|
||||
if {[file exists ${VLOG_SOURCE_LIST}]} {
|
||||
puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
|
||||
# vlog -incr -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
|
||||
vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
|
||||
}
|
||||
|
||||
|
||||
if {[file exists ${VHDL_SOURCE_LIST}]} {
|
||||
puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
|
||||
vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
|
||||
}
|
||||
|
||||
# eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
|
||||
# +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
|
||||
# +initmem+0 +initreg+0 +initwire+0 \
|
||||
# -suppress 2912 \
|
||||
# -suppress 1127
|
||||
|
||||
#to mask 211 error
|
||||
catch {
|
||||
if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
|
||||
eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
|
||||
-t 1ps -wlfopt -wlfcompress -nostdout \
|
||||
+initmem+0 +initreg+0 +initwire+0 \
|
||||
+no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
|
||||
-classdebug \
|
||||
glbl work.${CASE_NAME} \
|
||||
-wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
|
||||
} else {
|
||||
restart -f
|
||||
}
|
||||
} res;
|
||||
|
||||
do ../suppresswarning.tcl
|
||||
|
||||
catch {do wave.tcl} res
|
||||
|
||||
set TEMP_REF_FILES info.txt;
|
||||
write report -l $TEMP_REF_FILES
|
||||
|
||||
catch {run ${SIM_TIME} } res
|
||||
|
||||
do ../saveucdb.tcl
|
||||
#}
|
||||
|
||||
set current_path [pwd]
|
||||
puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
|
||||
15
new_project_rtl_template/sim/runall.tcl
Normal file
15
new_project_rtl_template/sim/runall.tcl
Normal file
@@ -0,0 +1,15 @@
|
||||
#usage do runall.tcl 1ms
|
||||
|
||||
set ROOT_PATH [pwd]
|
||||
|
||||
for {set NUMBER 3} { $NUMBER < 14} {incr NUMBER} {
|
||||
set CASE_NUMBER [format "%03d" $NUMBER]
|
||||
puts ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>$CASE_NUMBER start>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>"
|
||||
catch {do runone.tcl -n $CASE_NUMBER -t $1} result
|
||||
quit -sim
|
||||
cd ${ROOT_PATH}
|
||||
puts "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<$CASE_NUMBER end<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
|
||||
}
|
||||
|
||||
|
||||
|
||||
80
new_project_rtl_template/sim/runone.tcl
Normal file
80
new_project_rtl_template/sim/runone.tcl
Normal file
@@ -0,0 +1,80 @@
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
|
||||
|
||||
#clear the simulator transcript window and make the wave,data & coverage director
|
||||
do clear.tcl
|
||||
#preset envieroment variables
|
||||
do globalset.tcl
|
||||
set ROOT_PATH [pwd];
|
||||
|
||||
|
||||
#import common routines
|
||||
source functions.tcl
|
||||
source parse_args.tcl;
|
||||
|
||||
|
||||
set CASE_DIR ${SIM_TYPE}${CASE_NUM}
|
||||
|
||||
#we discard the case_num,thus all cases use the same case name.
|
||||
#thus the signal_name in the lastwave.tcl will be case independent
|
||||
#it's convinient to share and inherit lastwave in different case
|
||||
set CASE_NAME ${SIM_TYPE}${CASE_NUM}
|
||||
|
||||
|
||||
#puts "SIM_TYPE = $SIM_TYPE "
|
||||
#puts "CASE_NUM = $CASE_NUM "
|
||||
#puts "SIM_TIME = $SIM_TIME "
|
||||
#puts "CORNER_TYPE = $CORNER_TYPE"
|
||||
#puts "CASE_NAME = $CASE_NAME "
|
||||
|
||||
#copy modelsim.ini to case dir,and enter the case dependent directory
|
||||
file copy -force modelsim.ini ./${CASE_DIR}
|
||||
|
||||
|
||||
#by default,all cases use the same run.tcl
|
||||
#we can make trivial change to each case
|
||||
|
||||
|
||||
file copy -force run_template.tcl ./${CASE_DIR}/run.tcl
|
||||
|
||||
#we can use -c command to override run.tcl
|
||||
puts "---->check if override the run.tcl commandary..............."
|
||||
if {[string equal $COPY_RUN_TEMPLATE "yes" ]} {
|
||||
file copy -force run_template.tcl ./${CASE_DIR}/run.tcl
|
||||
puts "<<<<<<<<<<force copy run_template.tcl to ${CASE_DIR} dirctory>>>>>>>>>"
|
||||
}
|
||||
|
||||
#force generate instantiate_top.sv and override exist file
|
||||
if {[info exists GEN_INSTANTIATE_TOP] && [string equal $GEN_INSTANTIATE_TOP "yes" ]} {
|
||||
exec python ../../../../../python/gen_instantiate_top.py ../../01_source/01_func/${TOP_FILE}
|
||||
}
|
||||
|
||||
if {![file exists ./instantiate_top.sv]} {
|
||||
exec python ../../../../../python/gen_instantiate_top.py ../../01_source/01_func/${TOP_FILE}
|
||||
}
|
||||
|
||||
cd ${CASE_DIR}
|
||||
if { [ catch {do run.tcl -t $SIM_TIME -type $SIM_TYPE -corner $CORNER_TYPE} result ] } {
|
||||
|
||||
quit -sim
|
||||
cd ${ROOT_PATH}
|
||||
|
||||
}
|
||||
|
||||
set current_path [pwd]
|
||||
puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
|
||||
|
||||
14
new_project_rtl_template/sim/saveucdb.tcl
Normal file
14
new_project_rtl_template/sim/saveucdb.tcl
Normal file
@@ -0,0 +1,14 @@
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
#ATTTION : DO NOT MODIFY THE WHOLE FILE
|
||||
|
||||
|
||||
coverage save ${COVERAGE_OUTPUT_DIR}/${CASE_NAME}.ucdb
|
||||
8
new_project_rtl_template/sim/start_questasim_here.cmd
Normal file
8
new_project_rtl_template/sim/start_questasim_here.cmd
Normal file
@@ -0,0 +1,8 @@
|
||||
|
||||
del /f /q transcript
|
||||
start c:\questasim64_10.7\win64\questasim.exe -do sstc.preference
|
||||
rem start C:\questasim64_10.4c\win64\questasim.exe -do sstc.preference
|
||||
rem start D:\questasim64_10.7\win64\questasim.exe
|
||||
rem vsim -batch -logfile this.log
|
||||
|
||||
rem vsim -c
|
||||
21
new_project_rtl_template/sim/suppresswarning.tcl
Normal file
21
new_project_rtl_template/sim/suppresswarning.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
#ATTTION : MODIFY THIS FILE AS YOU WANT
|
||||
|
||||
|
||||
#0=note,1=warning,2=error,3=failure,4=fatal
|
||||
# set BreakOnAssertion 3 ;
|
||||
# set IgnoreNote 1 ;
|
||||
# set IgnoreWarning 1 ;
|
||||
# #set IgnoreError 1 ;
|
||||
# #set IgnoreFailure 1 ;
|
||||
# set IgnoreSVAInfo 1 ;
|
||||
# set IgnoreSVAWarning 1 ;
|
||||
# #set IgnoreSVAError 1 ;
|
||||
# #set IgnoreSVAFatal 1 ;
|
||||
# set NumericStdNoWarnings 1 ;
|
||||
# set StdArithNoWarnings 1 ;
|
||||
Reference in New Issue
Block a user