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FPGA_DESIGN_IP/uart_cli_axil/sim/_file_vhd.f

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2026-03-06 16:22:17 +08:00
#../../../01_source/01_func/IP/*.vhd
../../../01_source/01_func/SRC/ad_da_pack.vhd
../../../01_source/01_func/SRC/com_pack.vhd
../../../01_source/01_func/SRC/ld_pack.vhd
../../../01_source/01_func/SRC/top_pack.vhd
../../../01_source/01_func/IP/*.vhd
../../../01_source/01_func/SRC/*.vhd