Files
FPGA_DESIGN_IP/uart_cli_axil/cmd_line_buffer.sv

59 lines
1.7 KiB
Systemverilog
Raw Normal View History

2026-03-06 16:22:17 +08:00
//---------------------------------------------------------------------------------------
// filename: cmd_line_buffer.sv
// description: command line buffer
// author: leguoqing@paisat.cn
//---------------------------------------------------------------------------------------
module cmd_line_buffer
#(
parameter MODULE_FREQ_HZ = 50,
parameter BUF_SIZE = 4096,
parameter MAX_LINE_LEN = 256
)(
input logic clk,
input logic resetn,
// interface to byte stream of CLI
input logic byte_in_valid,
input logic [7:0] byte_in_data,
output logic byte_in_ready,
output logic byte_out_valid,
output logic [7:0] byte_out_data,
input logic byte_out_ready,
// interface to cli2axil
input logic from_cli_valid,
input logic [7:0] from_cli_data,
output logic from_cli_ready,
output logic to_cli_valid,
output logic [7:0] to_cli_data,
output logic to_cli_last,
input logic to_cli_ready
);
localparam integer MODULE_FREQ_MHZ = MODULE_FREQ_HZ / 1e6;
localparam integer MAX_LINE_CNT = BUF_SIZE / MAX_LINE_LEN;
localparam integer PTR_WIDTH = $clog2(BUF_SIZE);
localparam integer LINE_LEN_WIDTH = $clog2(MAX_LINE_LEN);
localparam integer LINE_CNT_WIDTH = $clog2(MAX_LINE_CNT);
// RX buffer
logic [7:0] rx_buffer [0:BUF_SIZE-1];
logic
logic [PTR_WIDTH-1:0] wr_ptr;
logic [PTR_WIDTH-1:0] rd_ptr;
logic [LINE_CNT_WIDTH:0] wr_idx;
logic [LINE_CNT_WIDTH:0] rd_idx;
logic [LINE_CNT_WIDTH:0] history_idx;
endmodule