51 lines
2.4 KiB
Systemverilog
51 lines
2.4 KiB
Systemverilog
|
/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/
|
||
|
|
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||
|
|
/*add all port here*/
|
||
|
|
/*use "logic" to replace "logic" and "logic" ports*/
|
||
|
|
/*use "wire" to replace "inout" ports*/
|
||
|
|
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||
|
|
//TODO:
|
||
|
|
|
||
|
|
parameter BRAM_LATENCY = 1; // 1: LATCH only; 2: +primitive or core out reg; 3: +primitive and core out reg; 4+: +pipeline
|
||
|
|
parameter STREAM_WIDTH = 8;
|
||
|
|
parameter BUF_SIZE = 4096; // in bytes
|
||
|
|
parameter SEG_SIZE = 256; // in bytes
|
||
|
|
|
||
|
|
logic clk;
|
||
|
|
logic rst_n;
|
||
|
|
logic enable;
|
||
|
|
logic [15:0] burst_time_interval; // us
|
||
|
|
logic [31:0] doorbell;
|
||
|
|
logic [31:0] buf_status;
|
||
|
|
logic [31:0] counter_tx_beats;
|
||
|
|
logic [31:0] counter_tx_bursts;
|
||
|
|
|
||
|
|
logic [STREAM_WIDTH-1:0] tdata;
|
||
|
|
logic tvalid;
|
||
|
|
logic tlast;
|
||
|
|
logic [STREAM_WIDTH/8-1:0] tkeep;
|
||
|
|
logic [STREAM_WIDTH/8-1:0] tstrb;
|
||
|
|
logic tready;
|
||
|
|
logic buf_clk;
|
||
|
|
logic [$clog2(BUF_SIZE)-1:0] buf_addr;
|
||
|
|
logic [STREAM_WIDTH/8-1:0] buf_wea;
|
||
|
|
logic [STREAM_WIDTH-1:0] buf_wdata;
|
||
|
|
logic [STREAM_WIDTH-1:0] buf_rdata;
|
||
|
|
logic list_clk;
|
||
|
|
logic [11:0] list_addr;
|
||
|
|
logic [ 3:0] list_wea;
|
||
|
|
logic [31:0] list_wdata;
|
||
|
|
logic [31:0] list_rdata;
|
||
|
|
|
||
|
|
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||
|
|
/*initialize all "logic" ports here
|
||
|
|
/*all inputs default as 0;modify if necessary
|
||
|
|
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||
|
|
//TODO:
|
||
|
|
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
|
||
|
|
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
|
||
|
|
|
||
|
|
/*do not modify
|
||
|
|
*/
|
||
|
|
`TOP_ENTITY `TOP_INSTANCE(.*);
|