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FPGA_DESIGN_IP/stream_tx_ctrl/sim/func001/debussy.bat

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2026-03-06 16:22:17 +08:00
::<3A>رջ<D8B1><D5BB><EFBFBD>
@ECHO OFF
::<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7>
SET Debussy=C:\Novas\Debussy\bin\Debussy.exe
SET vericom=C:\Novas\Debussy\bin\vericom.exe
SET vhdlcom=C:\Novas\Debussy\bin\vhdlcom.exe
::===== import design from file (compile design into ram) =====
::<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD> v/sv <20><><EFBFBD><EFBFBD>
%Debussy% -sv -f ../file_ver.f
::===== import design from library (compile design into library) =====
::<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Թ<EFBFBD><D4B9><EFBFBD> <20><> <20><> v/sv <20><><EFBFBD><EFBFBD>
::%vericom% -sv -2001 -f file_ver.f
::%vhdlcom% -2000 -f file_vhd.f
::%Debussy% -lib work -top top &
:<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
::DEL Debussy.fsdb /q
:<><C9BE>Debussy<73><79><EFBFBD>ɵ<EFBFBD><C9B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
RD Debussy.exeLog /s /q
DEL novas.rc /q
::<3A>˳<EFBFBD><CBB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
EXIT