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FPGA_DESIGN_IP/stream_tx_ctrl/sim/file_ver.f

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2026-03-06 16:22:17 +08:00
//+define+__MICROSATE_SIM__
vip_clock.sv
vip_uart.sv
axil_ram.v
tb.sv
../glbl.v
../../src/stream_tx_if.sv
../../src/wall_timer.sv