363 lines
12 KiB
Systemverilog
363 lines
12 KiB
Systemverilog
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// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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module apb_uart
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#(
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parameter CLOCK_FREQUENCY = 50e6,
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parameter BAUD_RATE = 115200,
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parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
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)
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(
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input logic CLK,
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input logic RSTN,
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/* verilator lint_off UNUSED */
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input logic [APB_ADDR_WIDTH-1:0] PADDR,
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/* lint_on */
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input logic [31:0] PWDATA,
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input logic PWRITE,
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input logic PSEL,
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input logic PENABLE,
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output logic [31:0] PRDATA,
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output logic PREADY,
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output logic PSLVERR,
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input logic rx_i, // Receiver input
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output logic tx_o, // Transmitter output
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output logic rda_o, // rx data avaiable
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output logic tde_o, // tx data empty
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output logic event_o // interrupt/event output
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);
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// register addresses
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parameter RBR = 3'h0, THR = 3'h0, DLL = 3'h0, IER = 3'h1, DLM = 3'h1, IIR = 3'h2,
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FCR = 3'h2, LCR = 3'h3, MCR = 3'h4, LSR = 3'h5, MSR = 3'h6, SCR = 3'h7;
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parameter TX_FIFO_DEPTH = 16; // in bytes
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parameter RX_FIFO_DEPTH = 16; // in bytes
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logic [2:0] register_adr;
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logic [9:0][7:0] regs_q, regs_n;
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logic [1:0] trigger_level_n, trigger_level_q;
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// receive buffer register, read only
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logic [7:0] rx_data;
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// parity error
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logic parity_error;
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logic rx_overrun;
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logic [3:0] IIR_o;
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logic [3:0] clr_int;
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/* verilator lint_off UNOPTFLAT */
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// tx flow control
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logic tx_ready;
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/* lint_on */
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// rx flow control
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logic apb_rx_ready;
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logic rx_valid;
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logic tx_fifo_clr_n, tx_fifo_clr_q;
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logic rx_fifo_clr_n, rx_fifo_clr_q;
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logic fifo_tx_valid;
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logic tx_valid;
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logic fifo_rx_valid;
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logic fifo_rx_ready;
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logic rx_ready;
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logic [7:0] fifo_tx_data;
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logic [8:0] fifo_rx_data;
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logic [7:0] tx_data;
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logic [$clog2(TX_FIFO_DEPTH):0] tx_elements;
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logic [$clog2(RX_FIFO_DEPTH):0] rx_elements;
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// TODO: check that stop bits are really not necessary here
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uart_rx uart_rx_i
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(
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.clk_i ( CLK ),
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.rstn_i ( RSTN ),
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.rx_i ( rx_i ),
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.cfg_en_i ( 1'b1 ),
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.cfg_div_i ( {regs_q[DLM + 'd8], regs_q[DLL + 'd8]} ),
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.cfg_parity_en_i ( regs_q[LCR][3] ),
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.cfg_even_parity_i ( regs_q[LCR][4] ),
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.cfg_bits_i ( regs_q[LCR][1:0] ),
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// .cfg_stop_bits_i ( regs_q[LCR][2] ),
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/* verilator lint_off PINCONNECTEMPTY */
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.busy_o ( ),
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/* lint_on */
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.parity_error_o ( parity_error ),
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.overrun_o ( rx_overrun ),
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.err_clr_i ( 1'b1 ),
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.rx_data_o ( rx_data ),
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.rx_valid_o ( rx_valid ),
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.rx_ready_i ( rx_ready )
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);
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uart_tx uart_tx_i
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(
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.clk_i ( CLK ),
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.rstn_i ( RSTN ),
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.tx_o ( tx_o ),
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/* verilator lint_off PINCONNECTEMPTY */
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.busy_o ( ),
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/* lint_on */
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.cfg_en_i ( 1'b1 ),
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.cfg_div_i ( {regs_q[DLM + 'd8], regs_q[DLL + 'd8]} ),
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.cfg_parity_en_i ( regs_q[LCR][3] ),
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.cfg_even_parity_i ( regs_q[LCR][4] ),
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.cfg_bits_i ( regs_q[LCR][1:0] ),
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.cfg_stop_bits_i ( regs_q[LCR][2] ),
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.tx_data_i ( tx_data ),
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.tx_valid_i ( tx_valid ),
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.tx_ready_o ( tx_ready )
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);
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io_generic_fifo
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#(
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.DATA_WIDTH ( 9 ),
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.BUFFER_DEPTH ( RX_FIFO_DEPTH )
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)
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uart_rx_fifo_i
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(
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.clk_i ( CLK ),
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.rstn_i ( RSTN ),
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.clr_i ( rx_fifo_clr_q ),
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.elements_o ( rx_elements ),
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.data_o ( fifo_rx_data ),
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.valid_o ( fifo_rx_valid ),
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.ready_i ( fifo_rx_ready ),
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.valid_i ( rx_valid ),
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.data_i ( { parity_error, rx_data } ),
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.ready_o ( rx_ready )
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);
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io_generic_fifo
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#(
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.DATA_WIDTH ( 8 ),
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.BUFFER_DEPTH ( TX_FIFO_DEPTH )
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)
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uart_tx_fifo_i
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(
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.clk_i ( CLK ),
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.rstn_i ( RSTN ),
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.clr_i ( tx_fifo_clr_q ),
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.elements_o ( tx_elements ),
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.data_o ( tx_data ),
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.valid_o ( tx_valid ),
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.ready_i ( tx_ready ),
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.valid_i ( fifo_tx_valid ),
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.data_i ( fifo_tx_data ),
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// not needed since we are getting the status via the fifo population
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.ready_o ( )
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);
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uart_interrupt
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#(
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.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
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.RX_FIFO_DEPTH (RX_FIFO_DEPTH)
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)
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uart_interrupt_i
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(
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.clk_i ( CLK ),
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.rstn_i ( RSTN ),
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.IER_i ( regs_q[IER] ), // interrupt enable register
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.RDA_i ( regs_n[LSR][0] ), // receiver data available
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.overrun_i ( regs_n[LSR][1] ), // rx data overrun
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.error_i ( regs_n[LSR][2] ),
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.rx_elements_i ( rx_elements ),
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.tx_elements_i ( tx_elements ),
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.trigger_level_i ( trigger_level_q ),
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.clr_int_i ( clr_int ), // one hot
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.interrupt_o ( event_o ),
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.IIR_o ( IIR_o )
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);
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// UART Registers
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// register write and update logic
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always_comb
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begin
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regs_n = regs_q;
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trigger_level_n = trigger_level_q;
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fifo_tx_valid = 1'b0;
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tx_fifo_clr_n = 1'b0; // self clearing
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rx_fifo_clr_n = 1'b0; // self clearing
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// rx status
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regs_n[LSR][0] = fifo_rx_valid; // fifo is empty
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// rx data discarded (no overrun in fact, the last rx byte was discarded.)
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regs_n[LSR][1] = rx_overrun;
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// parity error on receiving part has occured
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regs_n[LSR][2] = parity_error;
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// tx status register
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regs_n[LSR][5] = ~ (|tx_elements); // fifo is empty
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regs_n[LSR][6] = tx_ready & ~ (|tx_elements); // shift register and fifo are empty
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if (PSEL && PENABLE && PWRITE)
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begin
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case (register_adr)
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THR: // either THR or DLL
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begin
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if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
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begin
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regs_n[DLL + 'd8] = PWDATA[7:0];
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end
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else
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begin
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fifo_tx_data = PWDATA[7:0];
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fifo_tx_valid = 1'b1;
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end
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end
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IER: // either IER or DLM
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begin
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if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
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regs_n[DLM + 'd8] = PWDATA[7:0];
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else
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regs_n[IER] = PWDATA[7:0];
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end
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LCR:
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regs_n[LCR] = PWDATA[7:0];
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FCR: // write only register, fifo control register
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begin
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rx_fifo_clr_n = PWDATA[1];
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tx_fifo_clr_n = PWDATA[2];
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trigger_level_n = PWDATA[7:6];
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end
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default: ;
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endcase
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end
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end
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// register read logic
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always_comb
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begin
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PRDATA = 'b0;
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apb_rx_ready = 1'b0;
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fifo_rx_ready = 1'b0;
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clr_int = 4'b0;
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if (PSEL && PENABLE && !PWRITE)
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begin
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case (register_adr)
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RBR: // either RBR or DLL
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begin
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if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
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PRDATA = {24'b0, regs_q[DLL + 'd8]};
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else
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begin
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fifo_rx_ready = 1'b1;
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PRDATA = {24'b0, fifo_rx_data[7:0]};
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clr_int = 4'b1100; // clear Received Data Available interrupt
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end
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end
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LSR: // Line Status Register
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begin
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PRDATA = {24'b0, regs_q[LSR]};
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clr_int = 4'b0110; // clear parrity interrupt error
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end
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LCR: // Line Control Register
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PRDATA = {24'b0, regs_q[LCR]};
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IER: // either IER or DLM
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begin
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if (regs_q[LCR][7]) // Divisor Latch Access Bit (DLAB)
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PRDATA = {24'b0, regs_q[DLM + 'd8]};
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else
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PRDATA = {24'b0, regs_q[IER]};
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end
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IIR: // interrupt identification register read only
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begin
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PRDATA = {24'b0, 1'b1, 1'b1, 2'b0, IIR_o};
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clr_int = 4'b0010; // clear Transmitter Holding Register Empty
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end
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default: ;
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endcase
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end
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end
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// synchronouse part
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always_ff @(posedge CLK, negedge RSTN)
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begin
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if(~RSTN)
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begin
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regs_q[IER] <= 8'h0;
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regs_q[IIR] <= 8'h1;
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regs_q[LCR] <= 8'h3;
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regs_q[MCR] <= 8'h0;
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regs_q[LSR] <= 8'h60;
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regs_q[MSR] <= 8'h0;
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regs_q[SCR] <= 8'h0;
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regs_q[DLM + 'd8] <= 8'd1; // 50e6/115200 = 434
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regs_q[DLL + 'd8] <= 8'd178;
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trigger_level_q <= 2'b00;
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tx_fifo_clr_q <= 1'b0;
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rx_fifo_clr_q <= 1'b0;
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end
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else
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begin
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regs_q <= regs_n;
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trigger_level_q <= trigger_level_n;
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tx_fifo_clr_q <= tx_fifo_clr_n;
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rx_fifo_clr_q <= rx_fifo_clr_n;
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end
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end
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assign register_adr = {PADDR[2:0]};
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// APB logic: we are always ready to capture the data into our regs
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// not supporting transfare failure
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assign PREADY = 1'b1;
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assign PSLVERR = 1'b0;
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assign rda_o = regs_q[LSR][0]; // rx data avaiable
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assign tde_o = regs_q[LSR][5]; // tx data empty
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endmodule
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