164 lines
6.6 KiB
Plaintext
164 lines
6.6 KiB
Plaintext
|
# Reading C:/questasim64_10.7/tcl/vsim/pref.tcl
|
||
|
|
# // Questa Sim-64
|
||
|
|
# // Version 10.7 win64 Dec 7 2017
|
||
|
|
# //
|
||
|
|
# // Copyright 1991-2017 Mentor Graphics Corporation
|
||
|
|
# // All Rights Reserved.
|
||
|
|
# //
|
||
|
|
# // QuestaSim and its associated documentation contain trade
|
||
|
|
# // secrets and commercial or financial information that are the property of
|
||
|
|
# // Mentor Graphics Corporation and are privileged, confidential,
|
||
|
|
# // and exempt from disclosure under the Freedom of Information Act,
|
||
|
|
# // 5 U.S.C. Section 552. Furthermore, this information
|
||
|
|
# // is prohibited from disclosure under the Trade Secrets Act,
|
||
|
|
# // 18 U.S.C. Section 1905.
|
||
|
|
# //
|
||
|
|
# sstc.preference
|
||
|
|
# invalid command name "sstc.preference"
|
||
|
|
do runone.tcl -n 1 -t 1ms
|
||
|
|
# on
|
||
|
|
# stream_tx_if.sv
|
||
|
|
# Behavioral
|
||
|
|
# sbfce
|
||
|
|
# ../../../../../../03_simlib
|
||
|
|
# c:/questasim64_10.7
|
||
|
|
# proasic3l
|
||
|
|
# questasim
|
||
|
|
# 10.7
|
||
|
|
# nt64
|
||
|
|
# libero11.8
|
||
|
|
# ../coverage
|
||
|
|
# ../wave
|
||
|
|
# ../work
|
||
|
|
# stream_tx_if
|
||
|
|
# .sv
|
||
|
|
# u0_stream_tx_if
|
||
|
|
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim
|
||
|
|
# ---->parsing the command line....argc=4,args=-n 1 -t 1ms*************************
|
||
|
|
# case number=001
|
||
|
|
# simulation time=1ms
|
||
|
|
# ---->parsing the command line complete ***************************
|
||
|
|
# func001
|
||
|
|
# func001
|
||
|
|
# ---->check if override the run.tcl commandary...............
|
||
|
|
# reading modelsim.ini
|
||
|
|
# on
|
||
|
|
# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap std c:/questasim64_10.7/std
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap ieee c:/questasim64_10.7/ieee
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# ../../../01_source/01_func
|
||
|
|
# ../../../01_source/02_timing
|
||
|
|
# false
|
||
|
|
# false
|
||
|
|
# CASE_NAME func001
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if timing {}
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if timing {} SIM_TIME 1ms
|
||
|
|
# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_tx_if+define+TOP_INSTANCE=u0_stream_tx_if+define+timing=+define+SIM_TIME=1ms
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap work ../work/func001
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# 0
|
||
|
|
# 0
|
||
|
|
# ../file_ver.f
|
||
|
|
# ../file_vhd.f
|
||
|
|
# glbl
|
||
|
|
# ---->compile verilog source files ,testbench and models using ../file_ver.f........
|
||
|
|
# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
|
||
|
|
# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
|
||
|
|
# ** Error: (vlib-13069) ../../src/stream_tx_if.sv(6): near ")": syntax error, unexpected ')'.
|
||
|
|
# ** Error: c:/questasim64_10.7/win64/vlog failed.
|
||
|
|
# Error in macro ./run.tcl line 224
|
||
|
|
# c:/questasim64_10.7/win64/vlog failed.
|
||
|
|
# while executing
|
||
|
|
# "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003"
|
||
|
|
# invoked from within
|
||
|
|
# "if {$SIM_TYPE == "timing"} {
|
||
|
|
#
|
||
|
|
# set SDF_TYPE "-sdfmax";
|
||
|
|
# set SDFCOM_TYPE "-maxdelays";
|
||
|
|
#
|
||
|
|
# puts "*************************timing simulat..."
|
||
|
|
|
||
|
|
|
||
|
|
do runone.tcl -n 1 -t 1ms
|
||
|
|
# reading modelsim.ini
|
||
|
|
# on
|
||
|
|
# stream_tx_if.sv
|
||
|
|
# Behavioral
|
||
|
|
# sbfce
|
||
|
|
# ../../../../../../03_simlib
|
||
|
|
# c:/questasim64_10.7
|
||
|
|
# proasic3l
|
||
|
|
# questasim
|
||
|
|
# 10.7
|
||
|
|
# nt64
|
||
|
|
# libero11.8
|
||
|
|
# ../coverage
|
||
|
|
# ../wave
|
||
|
|
# ../work
|
||
|
|
# stream_tx_if
|
||
|
|
# .sv
|
||
|
|
# u0_stream_tx_if
|
||
|
|
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim
|
||
|
|
# ---->parsing the command line....argc=4,args=-n 1 -t 1ms*************************
|
||
|
|
# case number=001
|
||
|
|
# simulation time=1ms
|
||
|
|
# ---->parsing the command line complete ***************************
|
||
|
|
# func001
|
||
|
|
# func001
|
||
|
|
# ---->check if override the run.tcl commandary...............
|
||
|
|
# reading modelsim.ini
|
||
|
|
# on
|
||
|
|
# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap std c:/questasim64_10.7/std
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap ieee c:/questasim64_10.7/ieee
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# ../../../01_source/01_func
|
||
|
|
# ../../../01_source/02_timing
|
||
|
|
# false
|
||
|
|
# false
|
||
|
|
# CASE_NAME func001
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if timing {}
|
||
|
|
# CASE_NAME func001 TOP_ENTITY stream_tx_if TOP_INSTANCE u0_stream_tx_if timing {} SIM_TIME 1ms
|
||
|
|
# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_tx_if+define+TOP_INSTANCE=u0_stream_tx_if+define+timing=+define+SIM_TIME=1ms
|
||
|
|
# ** Warning: (vlib-34) Library already exists at "../work/func001".
|
||
|
|
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
|
||
|
|
# vmap work ../work/func001
|
||
|
|
# Modifying modelsim.ini
|
||
|
|
# 0
|
||
|
|
# 0
|
||
|
|
# ../file_ver.f
|
||
|
|
# ../file_vhd.f
|
||
|
|
# glbl
|
||
|
|
# ---->compile verilog source files ,testbench and models using ../file_ver.f........
|
||
|
|
# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
|
||
|
|
# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
|
||
|
|
# vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf
|
||
|
|
# Start time: 17:58:22 on Nov 21,2025
|
||
|
|
# ** Note: (vsim-3812) Design is being optimized...
|
||
|
|
# ** Note: (vopt-143) Recognized 1 FSM in module "stream_tx_if(fast)".
|
||
|
|
# ** Warning: tb.sv(7): (vopt-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
|
||
|
|
# ---->checing the simulator status to decide whether to restore the wave session..................
|
||
|
|
# ---->the runstatus is :ready
|
||
|
|
# ---->trying restore to saved wave window..................
|
||
|
|
# 0
|
||
|
|
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim/func001
|
||
|
|
# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim/func001++++++++++++++++++++++++++++++++
|
||
|
|
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim/func001
|
||
|
|
# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_tx_buffer/sim/func001++++++++++++++++++++++++++++++++
|
||
|
|
run 10ms
|
||
|
|
add wave -position insertpoint sim:/func001/u0_stream_tx_if/*
|
||
|
|
# End time: 17:58:51 on Nov 21,2025, Elapsed time: 0:00:29
|
||
|
|
# Errors: 0, Warnings: 1
|