51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
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`timescale 1ns/1ps
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module
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`CASE_NAME();
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`include "../instantiate_top.sv"
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final mti_fli::mti_Cmd("do ../saveucdb.tcl");
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*to end the simulation commandary*/
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/*if you want to end the simulation case by case,just comment the line
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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// instance vip
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vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
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initial begin
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enable = 1'b1;
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burst_time_interval = 8'h10;
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tready = 1;
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buf_rdata = 0;
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doorbell = 4;
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rst_n = 0;
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#1us rst_n = 1;
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end
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always@(posedge clk) begin
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case (list_addr)
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'h0: list_rdata <= 32'h0040_0000; // len=64
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'h1: list_rdata <= 32'h0080_0100; // len=128
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'h2: list_rdata <= 32'h00C0_0200; // len=192
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'h3: list_rdata <= 32'h0100_0300; // len=256
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default: list_rdata <= 32'h0;
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endcase
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end
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initial begin
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#1ns;
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@(posedge rst_n);
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#10us;
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end
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endmodule
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