313 lines
16 KiB
Python
313 lines
16 KiB
Python
"""
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Description : The prompt script for pychecker workflow
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Author : Ruidi Qiu (r.qiu@tum.de)
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Time : 2024/3/22 10:40:43
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LastEdited : 2024/8/25 11:55:28
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"""
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from .base_script import BaseScript, BaseScriptStage
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from .legacy import script_RTLchecker0306
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from .legacy.script_RTLchecker0306 import StageChecklist
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from . import utils
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class WF_pychecker_CMB(BaseScript):
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"""
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stages: stage1, stage2, stage3, stage3b, stage4
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check: check "scenario list"(stage2) in stage 4
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"""
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def __init__(self, prob_data:dict, task_dir:str, config:object):
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super().__init__(prob_data, task_dir, config)
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self.max_check_iter = self.config.autoline.checklist.max
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self.py_code = ""
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def make_and_run_stages(self):
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# stage1
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self.stage1 = Stage1(self.prob_data, **self.gptkwargs)
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self.stage_operation(self.stage1)
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# stage2
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self.stage2 = Stage2(self.prob_data, self.stage1.response, **self.gptkwargs)
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self.stage_operation(self.stage2)
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# stage3
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self.stage3 = Stage3(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage3)
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# stage4
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self.stage4 = Stage4(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck)
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# stage5
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self.stage5 = Stage5(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5)
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# self.TB_code += "\n" + stage3b.response
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def make_and_run_reboot_stages(self, debug_dir):
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if self.reboot_mode == "TB":
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# stage4
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self.stage4 = Stage4(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4, debug_dir, reboot_en=True)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck, debug_dir, reboot_en=True)
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elif self.reboot_mode == "PY":
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# stage5
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self.stage5 = Stage5(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5, debug_dir, reboot_en=True)
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else:
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raise ValueError("invalid reboot_mode in WF_pychecker script (circuit type: CMB)")
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class Stage1(script_RTLchecker0306.Stage1):
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"""
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stage1 for pychecker, the same as RTLchecker0306.Stage1
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"""
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def __init__(self, prob_data:dict, **gptkwargs):
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super().__init__(prob_data, **gptkwargs)
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class Stage2(script_RTLchecker0306.Stage2):
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"""
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stage2 for pychecker, the same as RTLchecker0306.Stage2
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"""
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def __init__(self, prob_data:dict, response_stage1:str, **gptkwargs):
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super().__init__(prob_data, response_stage1, **gptkwargs)
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class Stage3(script_RTLchecker0306.Stage3):
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"""
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stage3 for pychecker, the same as RTLchecker0306.Stage3
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"""
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def __init__(self, prob_data:dict, response_stage1:str, response_stage2:str, **gptkwargs):
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super().__init__(prob_data, response_stage1, response_stage2, **gptkwargs)
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SIGNALTEMP_PLACEHOLDER_1 = "/* SIGNAL TEMPLATE 1 */"
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SIGNALTEMP_PLACEHOLDER_1A = "/* SIGNAL TEMPLATE 1A */"
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SIGNALTEMP_PLACEHOLDER_1B = "/* SIGNAL TEMPLATE 1B */"
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STAGE4_TXT1 = """
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1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is
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- 1.1. the problem description that guides student to write the RTL code (DUT) and the header of the "DUT".
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- 1.2. the module header.
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- 1.3. the technical specification of testbench
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- 1.4. test scenarios which determines value and sequential information of test vectors
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2. you are in section 4. in this section, our target is to generate the verilog testbench for the DUT. This testbench can export the input and output signals of DUT at the important time points. The exported data will be send to a python script to check the correctness of DUT.
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ATTENTION: The testbench does not need to check the DUT's output but only export the signals of DUT.
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Instruction of saving signals to file:
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(1) you should use $fopen and $fdisplay to export the important signals in testbench. the file name is "TBout.txt".
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(2) When running testbench, for one time point, you should export 1 line. the example of the printed line is "%s". There could be multiple $fdisplay statements under one scenario, which means multiple test stimuli in one scenario.
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(3) Attention: before $fdisplay, you should always have a delay statement to make sure the signals are stable.
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(4) the signals you save is the input and output of DUT, you should determine the signals according to DUT's header:
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"""%(SIGNALTEMP_PLACEHOLDER_1)
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STAGE4_TXT2 = """
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The testbench does not need to check the DUT's output but only export the signals of DUT.
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Instruction of saving signals to file:
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(1) you should use $fopen and $fdisplay to export the important signals in testbench. the file name is "TBout.txt".
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(2) When running testbench, for one time point, you should export 1 line. the example of the printed line is "%s"; There could be multiple $fdisplay statements under one scenario, which means multiple test stimuli in one scenario.
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(3) Attention: before $fdisplay, you should always have a delay statement (#10) to make sure the signals are stable.
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(4) the signals you save is the input and output of DUT, you should determine the signals according to DUT's header.
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please only generate the verilog codes, no other words.
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"""%(SIGNALTEMP_PLACEHOLDER_1)
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class Stage4(BaseScriptStage):
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"""stage 4: generate the testbench that export the signals of DUT to a file"""
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def __init__(self, prob_data, response_stage1, response_stage2, **gptkwargs) -> None:
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super().__init__("stage_4", **gptkwargs)
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self.prob_data = prob_data
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self.response_stage1 = response_stage1
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self.response_stage2 = response_stage2
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self.txt1 = STAGE4_TXT1
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self.txt2 = STAGE4_TXT2
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self.txt1 = self.txt1.replace(SIGNALTEMP_PLACEHOLDER_1, header_to_SignalTxt_template(prob_data["header"]))
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self.txt2 = self.txt2.replace(SIGNALTEMP_PLACEHOLDER_1, header_to_SignalTxt_template(prob_data["header"]))
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def make_prompt(self):
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self.prompt = ""
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self.add_prompt_line(self.txt1)
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# DUT header
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self.add_prompt_line(self.prob_data["header"])
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# other information:
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self.add_prompt_line("Your other information:")
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# problem description
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self.add_prompt_line("RTL circuit problem description:")
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self.add_prompt_line(self.prob_data["description"])
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# specification
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self.add_prompt_line("RTL testbench specification:")
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self.add_prompt_line(self.response_stage1)
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# rules
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self.add_prompt_line("IMPORTANT - test scenario:")
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self.add_prompt_line(self.response_stage2)
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# end
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self.add_prompt_line(self.txt2)
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def postprocessing(self):
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# verilog codes
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self.response = self.extract_code(self.response, "verilog")[-1]
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self.TB_code_out = self.response
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# newly added
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self.TB_code_out = utils.pychecker_CMB_TB_standardization(self.TB_code_out, self.prob_data["header"])
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STAGEPYGEN_PYFORMAT = """Your current task is: write a python class "GoldenDUT". This python class can represent the golden DUT (the ideal one). In your "GoldenDUT", you should do the following things:
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- a. Write a method "def __init__(self)". Set the inner states/values of the golden DUT. The "__init__" method has no input parameters except "self".
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- b. Write a method "def load(self, signal_vector)". This method is to load the important input signals and get the expected output signals. it should return the expected output values. It can call other methods to help computing the expected output. It will be called by other inner methods later.
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- c. Write a method "def check(self, signal_vector)". This method is to call "load" to get the expected output values, and compare them with output signals from DUT. It should return True or False only. It can call other methods to help checking.
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- d. write other methods you need, they can be called by "__init__", "load" or "check".
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- e. the input of "load" and "check" is the signal vector. The signal vector is a dictionary, the key is the signal name, the value is the signal value.
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You can use binary (like 0x1101), hexadecimal (like 0x1a) or normal number format in python. But the signal vector input to GoldenDUT is always in decimal format""" # TODO: later this function will also show the failed scenario idx
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# STAGEPYGEN_TXT1 = """
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# 1. background: Your task is to verify the functional correctness of a verilog RTL module code (we call it as "DUT", device under test). Our plan is to first export the signals (input and output) of the DUT under test scenarios. Then, we will use a python script to check the correctness of DUT.
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# 2. You are in the last stage. In this stage, we already export the signals of DUT. Your task is to write a python script. The python script contains one main function "check_dut" and other functions to be called by "check_dut" (this is optional). The input of "check_dut" is the signals of DUT in the format below: (the signal names are real, but the values are just for example)
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# %s
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# The main function "check_dut" should check the correctness according to the input signals. The input signals are all in decimal format. It will be called by other codes later.
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# 3. %s
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# 4. You have the information below to help you check the correctness of DUT:
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# """%(SIGNALTEMP_PLACEHOLDER_1, STAGEPYGEN_PYFORMAT)
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STAGEPYGEN_TXT1 = """
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1. background: Your task is to verify the functional correctness of a verilog RTL module code (we call it as "DUT", device under test). Our plan is to first export the signals (input and output) of the DUT under test scenarios. Then, we will use a python script to check the correctness of DUT.
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2. You are in the last stage. In this stage, we already export the signals of DUT. The signals of DUT are in the format below: (the signal names are real, but the values are just for example)
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%s
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The input signals are all in decimal format. The "scenario" is not DUT's signal but to tell you the current scenario index.
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3. %s
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4. You have the information below to help you check the correctness of DUT:
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"""%(SIGNALTEMP_PLACEHOLDER_1, STAGEPYGEN_PYFORMAT)
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STAGEPYGEN_TXT2 = """
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[IMPORTANT] %s
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Optional: You can also use functions from numpy and scipy to help you check the correctness of DUT.
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you can use binary (like 0b1011), hexadeciaml (like 0x1a) or normal number format in python for convenience.
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please only generate the python codes, no other words.
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"""%(STAGEPYGEN_PYFORMAT)
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STAGEPYGEN_TAIL1 = """
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def check_dut(vectors_in):
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golden_dut = GoldenDUT()
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failed_scenarios = []
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for vector in vectors_in:
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check_pass = golden_dut.check(vector)
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if check_pass:
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print(f"Passed; vector: {vector}")
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else:
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print(f"Failed; vector: {vector}")
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failed_scenarios.append(vector["scenario"])
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return failed_scenarios
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"""
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STAGEPYGEN_TAIL2 = """
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def SignalTxt_to_dictlist(txt:str):
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lines = txt.strip().split("\\n")
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signals = []
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for line in lines:
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signal = {}
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line = line.strip().split(", ")
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for item in line:
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if "scenario" in item:
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item = item.split(": ")
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signal["scenario"] = item[1]
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else:
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item = item.split(" = ")
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key = item[0]
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value = item[1]
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if "x" not in value and "z" not in value:
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signal[key] = int(value)
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else:
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signal[key] = value
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signals.append(signal)
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return signals
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with open("TBout.txt", "r") as f:
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txt = f.read()
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vectors_in = SignalTxt_to_dictlist(txt)
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tb_pass = check_dut(vectors_in)
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print(tb_pass)
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"""
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class Stage5(BaseScriptStage):
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"""stage 5: generate the pychecker that receive the signals from testbench and check the correctness of DUT"""
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def __init__(self, prob_data, response_stage1, response_stage3, **gptkwargs) -> None:
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super().__init__("stage_5", **gptkwargs)
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self.prob_data = prob_data
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self.response_stage1 = response_stage1
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self.response_stage3 = response_stage3 # currently not used
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self.txt1 = STAGEPYGEN_TXT1.replace(SIGNALTEMP_PLACEHOLDER_1, utils.signal_dictlist_template(prob_data["header"], use_check_en=False))
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self.txt2 = STAGEPYGEN_TXT2
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self.pycode_tail = STAGEPYGEN_TAIL1 + STAGEPYGEN_TAIL2
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def make_prompt(self):
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self.prompt = ""
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# introduction
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self.add_prompt_line(self.txt1)
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# problem description
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self.add_prompt_line("RTL circuit problem description:")
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self.add_prompt_line(self.prob_data["description"])
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# specification
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self.add_prompt_line("Checker specification:")
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self.add_prompt_line(self.response_stage1)
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# python rules (optional)
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self.add_prompt_line("Here is the basic rules in python for the module. It is generated in previous stage. You can use it as a reference, but you should write your own python script. This is just for your better understanding:")
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self.add_prompt_line(self.response_stage3)
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# end
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self.add_prompt_line(self.txt2)
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def postprocessing(self):
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# python codes
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self.response = self.extract_code(self.response, "python")[-1]
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self.Pychecker_code_out = self.response + self.pycode_tail
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# @staticmethod
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# def signal_dictlist_template(header:str) -> str:
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# """
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# for the automatic generation of signals in testbench
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# target: given the DUT header, generate the signal output template
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# eg: if we have a DUT header like "module DUT(input a, b, c, output d, e);", the signal output template should be like "[{"scenario": "1", "a": 1, "b": 0, "c":1, "d": 0, "e": 0}, {"scenario": "2", "a": 0, "b": 0, "c":1, "d": 0, "e": 0}]"
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# """
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# signals1 = header_to_SignalTxt_template(header, "1")
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# signals2 = header_to_SignalTxt_template(header, "2")
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# signals_dictlist1 = SignalTxt_to_dictlist(signals1)
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# signals_dictlist2 = SignalTxt_to_dictlist(signals2)
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# signals_dictlist = signals_dictlist1 + signals_dictlist2
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# return str(signals_dictlist)
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def header_to_SignalTxt_template(header:str):
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"""
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- header: the header of DUT
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- from header to signals in txt
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- for the automatic generation of signals in testbench
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- target: given the DUT header, generate the signal output template
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- eg: if we have a DUT header like "module DUT(input clk, load, data, output q);", the signal output template should be like "$fdisplay(file, "scenario: %d, clk = %d, load = %d, data = %d, q = %d", scenario, clk, load, data, q);"
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"""
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signals = utils.extract_signals(header)
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# generate ", clk = %d, load = %d, data = %d, q = %d"
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signal_form1 = ""
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signal_form2 = ""
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for signal in signals:
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signal_form1 += f", {signal['name']} = %d"
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signal_form2 += f", {signal['name']}"
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txt = r'$fdisplay(file, "scenario: %d' + signal_form1 + r'", scenario' + signal_form2 + r');'
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return txt
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# def SignalTxt_to_dictlist(txt:str) -> list:
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# """
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# - from txt to list of dicts
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# - this function is used to extract signals and scenario information from a out.txt file.
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# - the TBout.txt file is generated by testbench, which is in the pychecker workflow
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# - the format of each line in TBout.txt is like:
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# - "scenario: x, a = x, b = x, c = x, d = x, e = x"
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# - we want: [{"scenario": x, "a": x, ...}, {...}]
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# """
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# lines = txt.strip().split("\n")
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# signals = []
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# for line in lines:
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# signal = {}
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# line = line.strip().split(", ")
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# for item in line:
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# if "scenario" in item:
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# item = item.split(": ")
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# signal["scenario"] = item[1]
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# else:
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# item = item.split(" = ")
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# key = item[0]
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# value = item[1]
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# if "x" not in value and "z" not in value:
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# signal[key] = int(value)
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# else:
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# signal[key] = value
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# signals.append(signal)
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# return signals |