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zice6688
2026-03-30 16:46:48 +08:00
parent 8c2008c738
commit 35c99bac58
110 changed files with 23243 additions and 0 deletions
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30
output/example_mul/example_mul/1_TBgen/TBgen_codes/TBout.txt Normal file
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scenario: 1, clk = 0, rst = 1, a = 0, b = 0, y = z
[check]scenario: 1, clk = 1, rst = 1, a = 0, b = 0, y = z
scenario: 2, clk = 1, rst = 0, a = 1, b = 1, y = z
[check]scenario: 2, clk = 1, rst = 0, a = 1, b = 1, y = z
scenario: 3, clk = 1, rst = 0, a = 0, b = 255, y = z
[check]scenario: 3, clk = 1, rst = 0, a = 0, b = 255, y = z
scenario: 4, clk = 1, rst = 0, a = 255, b = 0, y = z
[check]scenario: 4, clk = 1, rst = 0, a = 255, b = 0, y = z
scenario: 5, clk = 1, rst = 0, a = 255, b = 255, y = z
[check]scenario: 5, clk = 1, rst = 0, a = 255, b = 255, y = z
scenario: 6, clk = 1, rst = 0, a = 128, b = 128, y = z
[check]scenario: 6, clk = 1, rst = 0, a = 128, b = 128, y = z
scenario: 7, clk = 1, rst = 0, a = 1, b = 128, y = z
[check]scenario: 7, clk = 1, rst = 0, a = 1, b = 128, y = z
scenario: 8, clk = 1, rst = 0, a = 128, b = 1, y = z
[check]scenario: 8, clk = 1, rst = 0, a = 128, b = 1, y = z
scenario: 9, clk = 1, rst = 0, a = 10, b = 11, y = z
[check]scenario: 9, clk = 1, rst = 0, a = 10, b = 11, y = z
scenario: 10, clk = 1, rst = 0, a = 127, b = 127, y = z
[check]scenario: 10, clk = 1, rst = 0, a = 127, b = 127, y = z
scenario: 11, clk = 1, rst = 0, a = 15, b = 240, y = z
[check]scenario: 11, clk = 1, rst = 0, a = 15, b = 240, y = z
scenario: 12, clk = 1, rst = 0, a = 0, b = 0, y = z
[check]scenario: 12, clk = 1, rst = 0, a = 0, b = 0, y = z
scenario: 13, clk = 1, rst = 0, a = 15, b = 15, y = z
[check]scenario: 13, clk = 1, rst = 0, a = 15, b = 15, y = z
scenario: 14, clk = 1, rst = 0, a = 14, b = 14, y = z
[check]scenario: 14, clk = 1, rst = 0, a = 14, b = 14, y = z
scenario: 15, clk = 1, rst = 0, a = 13, b = 13, y = z
[check]scenario: 15, clk = 1, rst = 0, a = 13, b = 13, y = z

3
output/example_mul/example_mul/1_TBgen/TBgen_codes/example_mul.v Normal file
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module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
endmodule

82
output/example_mul/example_mul/1_TBgen/TBgen_codes/example_mul_tb.py Normal file
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class GoldenDUT:
def __init__(self):
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
self.rst_reg = 1
def load(self, signal_vector):
self.a_reg = signal_vector['a'] & 0xFF
self.b_reg = signal_vector['b'] & 0xFF
self.rst_reg = signal_vector['rst']
if self.rst_reg == 1:
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
else:
self.y_reg = self.multiply_8bit(self.a_reg, self.b_reg)
def check(self, signal_vector):
expected_y = self.multiply_8bit(self.a_reg, self.b_reg)
observed_y = signal_vector['y'] & 0xFFFF
if expected_y != observed_y:
print(f"Scenario: {signal_vector['scenario']}, expected: y=0x{expected_y:04X}, observed: y=0x{observed_y:04X}")
return False
return True
def multiply_8bit(self, a, b):
a = a & 0xFF
b = b & 0xFF
product = a * b
product = product & 0xFFFF
return product
def check_dut(vectors_in):
golden_dut = GoldenDUT()
failed_scenarios = []
for vector in vectors_in:
if vector["check_en"]:
check_pass = golden_dut.check(vector)
if check_pass:
print(f"Passed; vector: {vector}")
else:
print(f"Failed; vector: {vector}")
failed_scenarios.append(vector["scenario"])
golden_dut.load(vector)
return failed_scenarios
def SignalTxt_to_dictlist(txt:str):
signals = []
lines = txt.strip().split("\n")
for line in lines:
signal = {}
if line.startswith("[check]"):
signal["check_en"] = True
line = line[7:]
elif line.startswith("scenario"):
signal["check_en"] = False
else:
continue
line = line.strip().split(", ")
for item in line:
if "scenario" in item:
item = item.split(": ")
signal["scenario"] = item[1].replace(" ", "")
else:
item = item.split(" = ")
key = item[0]
value = item[1]
if ("x" not in value) and ("X" not in value) and ("z" not in value):
signal[key] = int(value)
else:
if ("x" in value) or ("X" in value):
signal[key] = 0 # used to be "x"
else:
signal[key] = 0 # used to be "z"
signals.append(signal)
return signals
with open("TBout.txt", "r") as f:
txt = f.read()
vectors_in = SignalTxt_to_dictlist(txt)
tb_pass = check_dut(vectors_in)
print(tb_pass)

138
output/example_mul/example_mul/1_TBgen/TBgen_codes/example_mul_tb.v Normal file
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`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule

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output/example_mul/example_mul/1_TBgen/TBgen_codes/run.vvp Normal file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
S_0x5f1b861d6b90 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x5f1b861b9000 .scope module, "testbench" "testbench" 3 2;
.timescale -9 -12;
v0x5f1b861f7200_0 .var "a", 7 0;
v0x5f1b861f72e0_0 .var "b", 7 0;
v0x5f1b861f73b0_0 .var "clk", 0 0;
v0x5f1b861f74b0_0 .var/i "file", 31 0;
v0x5f1b861f7550_0 .var "rst", 0 0;
v0x5f1b861f7640_0 .var/i "scenario", 31 0;
o0x70ab3a8a60d8 .functor BUFZ 16, C4<zzzzzzzzzzzzzzzz>; HiZ drive
v0x5f1b861f76e0_0 .net "y", 15 0, o0x70ab3a8a60d8; 0 drivers
S_0x5f1b861b9190 .scope module, "DUT" "example" 3 11, 4 1 0, S_0x5f1b861b9000;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 8 "a";
.port_info 3 /INPUT 8 "b";
.port_info 4 /OUTPUT 16 "y";
v0x5f1b861d47e0_0 .net "a", 7 0, v0x5f1b861f7200_0; 1 drivers
v0x5f1b861f6dc0_0 .net "b", 7 0, v0x5f1b861f72e0_0; 1 drivers
v0x5f1b861f6ea0_0 .net "clk", 0 0, v0x5f1b861f73b0_0; 1 drivers
v0x5f1b861f6f70_0 .net "rst", 0 0, v0x5f1b861f7550_0; 1 drivers
v0x5f1b861f7030_0 .net "y", 15 0, o0x70ab3a8a60d8; alias, 0 drivers
.scope S_0x5f1b861b9000;
T_0 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5f1b861f73b0_0, 0, 1;
T_0.0 ;
%delay 5000, 0;
%load/vec4 v0x5f1b861f73b0_0;
%inv;
%store/vec4 v0x5f1b861f73b0_0, 0, 1;
%jmp T_0.0;
%end;
.thread T_0;
.scope S_0x5f1b861b9000;
T_1 ;
%vpi_func 3 25 "$fopen" 32, "TBout.txt", "w" {0 0 0};
%store/vec4 v0x5f1b861f74b0_0, 0, 32;
%end;
.thread T_1;
.scope S_0x5f1b861b9000;
T_2 ;
%pushi/vec4 1, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5f1b861f7550_0, 0, 1;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 32 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 34 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 2, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5f1b861f7550_0, 0, 1;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 39 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 41 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 3, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 46 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 48 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 4, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 53 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 55 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 5, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 60 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 62 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 6, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 67 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 69 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 7, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 74 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 76 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 8, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 81 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 83 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 9, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 10, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 11, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 88 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 90 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 10, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 127, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 127, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 95 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 97 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 11, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 102 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 104 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 12, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 109 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 111 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 13, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 116 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 118 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 14, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 14, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 14, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 123 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 125 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 15, 0, 32;
%store/vec4 v0x5f1b861f7640_0, 0, 32;
%pushi/vec4 13, 0, 8;
%store/vec4 v0x5f1b861f7200_0, 0, 8;
%pushi/vec4 13, 0, 8;
%store/vec4 v0x5f1b861f72e0_0, 0, 8;
%vpi_call/w 3 130 "$fdisplay", v0x5f1b861f74b0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 132 "$fdisplay", v0x5f1b861f74b0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5f1b861f7640_0, v0x5f1b861f73b0_0, v0x5f1b861f7550_0, v0x5f1b861f7200_0, v0x5f1b861f72e0_0, v0x5f1b861f76e0_0 {0 0 0};
%vpi_call/w 3 134 "$fclose", v0x5f1b861f74b0_0 {0 0 0};
%vpi_call/w 3 135 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"-";
"example_mul_tb.v";
"example_mul.v";

15
output/example_mul/example_mul/1_TBgen/TBgen_codes/run_info.txt Normal file
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@@ -0,0 +1,15 @@
iverilog simulation passed!
iverilog cmd 1:
/usr/bin/iverilog -g2012 -o run.vvp example_mul.v example_mul_tb.v
iverilog cmd 1 output:
iverilog cmd 1 error:
iverilog cmd 2:
/usr/bin/vvp run.vvp
iverilog cmd 2 output:
example_mul_tb.v:135: $finish called at 290000 (1ps)
iverilog cmd 2 error:

35
output/example_mul/example_mul/1_TBgen/TBgen_codes/run_info_py.txt Normal file
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@@ -0,0 +1,35 @@
python compilation passed!
###output:
Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'rst': 1, 'a': 0, 'b': 0, 'y': 0}
Scenario: 2, expected: y=0x0001, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'rst': 0, 'a': 1, 'b': 1, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'rst': 0, 'a': 0, 'b': 255, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'rst': 0, 'a': 255, 'b': 0, 'y': 0}
Scenario: 5, expected: y=0xFE01, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'rst': 0, 'a': 255, 'b': 255, 'y': 0}
Scenario: 6, expected: y=0x4000, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'rst': 0, 'a': 128, 'b': 128, 'y': 0}
Scenario: 7, expected: y=0x0080, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'rst': 0, 'a': 1, 'b': 128, 'y': 0}
Scenario: 8, expected: y=0x0080, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'rst': 0, 'a': 128, 'b': 1, 'y': 0}
Scenario: 9, expected: y=0x006E, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'rst': 0, 'a': 10, 'b': 11, 'y': 0}
Scenario: 10, expected: y=0x3F01, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'rst': 0, 'a': 127, 'b': 127, 'y': 0}
Scenario: 11, expected: y=0x0E10, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'rst': 0, 'a': 15, 'b': 240, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '12', 'clk': 1, 'rst': 0, 'a': 0, 'b': 0, 'y': 0}
Scenario: 13, expected: y=0x00E1, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '13', 'clk': 1, 'rst': 0, 'a': 15, 'b': 15, 'y': 0}
Scenario: 14, expected: y=0x00C4, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '14', 'clk': 1, 'rst': 0, 'a': 14, 'b': 14, 'y': 0}
Scenario: 15, expected: y=0x00A9, observed: y=0x0000
Failed; vector: {'check_en': True, 'scenario': '15', 'clk': 1, 'rst': 0, 'a': 13, 'b': 13, 'y': 0}
['2', '5', '6', '7', '8', '9', '10', '11', '13', '14', '15']
###error:

2
output/example_mul/example_mul/1_TBgen/TBgen_codes/vlist.txt Normal file
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@@ -0,0 +1,2 @@
example_mul.v
example_mul_tb.v

37
output/example_mul/example_mul/1_TBgen/stage_0.txt Normal file
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@@ -0,0 +1,37 @@
############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
Please generate the verilog RTL code according to the following description and header information:
problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
RTL header:
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
please only reply verilog codes. reply_format:
```verilog
your_code_here...
```
########## assistant ##########
```verilog
module example(
input clk,
input rst,
input [7:0] a,
input [7:0] b,
output reg [15:0] y
);
always @(posedge clk or posedge rst) begin
if (rst) begin
y <= 16'b0;
end else begin
y <= a * b;
end
end
endmodule
```

42
output/example_mul/example_mul/1_TBgen/stage_1.txt Normal file
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############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
2. You are in the first stage. In this stage, please summarize the technical details of the DUT and give me a technical specification of the testbench generation task, so we can use it to design its corresponding testbench.
3. The core of testbench is the testcases. It usually include two parts logically: the input signals to the DUT and the expected result signals from DUT. The testbench will send the input signals to DUT and check if the result signals are the same as the expected result signals. If they are the same, this means the DUT is passed. Otherwise the DUT fails.
4. Your technical specification should include these sections:
- section 1: specification of the DUT, including the module header of the RTL code. If table or other detailed data is provided in the original problem description, DO repeat them in your response. They are very important!!!
5. your response should be in the form of JSON.
6. below is the information including the problem description and the DUT header:
RTL circuit problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
DUT header:
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
your response must be in JSON form. example:
{
"important data": "...", # type: string. If no table, state transition or other direct data, leave this with ""
"technical specifications": ["...", "...", ...] # each element of the list is one specification string, the starting of the string is its index
}
########## assistant ##########
```json
{
"important data": "",
"technical specifications": [
"1. The DUT is an 8-bit multiplier that takes two 8-bit unsigned numbers as inputs and produces a 16-bit product as the output.",
"2. The module header of the DUT is: `module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);`",
"3. The DUT has the following inputs and outputs:\n- Input: `clk` (clock signal)\n- Input: `rst` (reset signal)\n- Input: `a` (8-bit unsigned number, range: 0 to 255)\n- Input: `b` (8-bit unsigned number, range: 0 to 255)\n- Output: `y` (16-bit unsigned number, range: 0 to 65535)",
"4. The testbench should generate a series of test cases to verify the functionality of the DUT. Each test case should include:\n- A set of input values for `a` and `b`\n- The expected 16-bit product `y`",
"5. The testbench should initialize the DUT with a reset signal (`rst`) and then apply the clock signal (`clk`) to drive the DUT through its operation.",
"6. The testbench should compare the actual output `y` from the DUT with the expected output for each test case. If they match, the test case passes; otherwise, it fails.",
"7. The testbench should cover a wide range of test cases, including but not limited to:\n- Boundary conditions (e.g., `a = 0`, `b = 0`, `a = 255`, `b = 255`)\n- Random values within the range of 0 to 255\n- Special cases (e.g., `a = 1`, `b = 1`, `a = 128`, `b = 128`)"
]
}
```
This JSON response provides a detailed technical specification for the DUT and the requirements for the testbench generation task. It includes the necessary information about the inputs, outputs, and the expected behavior of the DUT, as well as the test cases that should be included in the testbench.

98
output/example_mul/example_mul/1_TBgen/stage_2.txt Normal file
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@@ -0,0 +1,98 @@
############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
2. you are in section 2. in this section, please give me the test scenarios. you only need to describe the stimulus in each test scenarios. If time is important, please inform the clock cycle information. we will use the stimulus description to generate the test vectors and send them to DUT. you must not tell the expected results even though you know that.
3. your information is:
RTL circuit problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
RTL testbench specification:
```json
{
"important data": "",
"technical specifications": [
"1. The DUT is an 8-bit multiplier that takes two 8-bit unsigned numbers as inputs and produces a 16-bit product as the output.",
"2. The module header of the DUT is: `module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);`",
"3. The DUT has the following inputs and outputs:\n- Input: `clk` (clock signal)\n- Input: `rst` (reset signal)\n- Input: `a` (8-bit unsigned number, range: 0 to 255)\n- Input: `b` (8-bit unsigned number, range: 0 to 255)\n- Output: `y` (16-bit unsigned number, range: 0 to 65535)",
"4. The testbench should generate a series of test cases to verify the functionality of the DUT. Each test case should include:\n- A set of input values for `a` and `b`\n- The expected 16-bit product `y`",
"5. The testbench should initialize the DUT with a reset signal (`rst`) and then apply the clock signal (`clk`) to drive the DUT through its operation.",
"6. The testbench should compare the actual output `y` from the DUT with the expected output for each test case. If they match, the test case passes; otherwise, it fails.",
"7. The testbench should cover a wide range of test cases, including but not limited to:\n- Boundary conditions (e.g., `a = 0`, `b = 0`, `a = 255`, `b = 255`)\n- Random values within the range of 0 to 255\n- Special cases (e.g., `a = 1`, `b = 1`, `a = 128`, `b = 128`)"
]
}
```
This JSON response provides a detailed technical specification for the DUT and the requirements for the testbench generation task. It includes the necessary information about the inputs, outputs, and the expected behavior of the DUT, as well as the test cases that should be included in the testbench.
DUT header:
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
you only need to describe the stimulus in each test scenarios. If time is important, please inform the clock cycle information. we will use the stimulus description to generate the test vectors and send them to DUT. you must not tell the expected results even though you know that.
your response must be in JSON form. example:
{
"scenario 1": "...", # each content is a string
"scenario 2": "...",
"scenario 3": "...",
...
}
########## assistant ##########
```json
{
"scenario 1": "Initialize the DUT with a reset signal (rst = 1) for one clock cycle. Set clk to 0, then to 1, and back to 0 to complete one clock cycle. After the reset, set rst to 0.",
"scenario 2": "Set a = 0 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 3": "Set a = 255 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 4": "Set a = 1 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 5": "Set a = 128 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 6": "Set a = 0 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 7": "Set a = 255 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 8": "Set a = 1 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 9": "Set a = 255 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 10": "Set a = 128 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 11": "Set a = 0 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 12": "Set a = 1 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 13": "Set a = 128 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 14": "Set a = 127 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 15": "Set a = 127 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 16": "Set a = 1 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 17": "Set a = 127 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 18": "Set a = 0 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 19": "Set a = 64 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 20": "Set a = 64 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 21": "Set a = 1 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 22": "Set a = 64 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 23": "Set a = 0 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 24": "Set a = 32 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 25": "Set a = 32 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 26": "Set a = 1 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 27": "Set a = 32 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 28": "Set a = 0 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 29": "Set a = 16 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 30": "Set a = 16 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 31": "Set a = 1 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 32": "Set a = 16 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 33": "Set a = 0 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 34": "Set a = 8 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 35": "Set a = 8 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 36": "Set a = 1 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 37": "Set a = 8 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 38": "Set a = 0 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 39": "Set a = 4 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 40": "Set a = 4 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 41": "Set a = 1 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 42": "Set a = 4 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 43": "Set a = 0 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 44": "Set a = 2 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 45": "Set a = 2 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 46": "Set a = 1 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 47": "Set a = 2 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 48": "Set a = 0 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 49": "Set a = 1 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 50": "Set a = 1 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 51": "Set a = 0 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0."
}
```

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############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The information we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
2. you are in stage 3; in this stage, please give me the core rules of an ideal DUT. you should give these rules in python. (For convenience, you can use binary or hexadecimal format in python, i.e. 0b0010 and 0x1a). Later we will use these ideal rules to generate expected values in each test scenario. currently you must only generate the core part of the rules. the input of these rules should be related to the test vectors from test scenario. the rule should give the expected values under test vectors. You don't need to consider the control signals like clk or reset, unless the core rules of this task are about these signals. You can use numpy, scipy or other third party python libraries to help you write the rules. Please import them if you need.
3. your information is:
RTL circuit problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
RTL testbench specification:
```json
{
"important data": "",
"technical specifications": [
"1. The DUT is an 8-bit multiplier that takes two 8-bit unsigned numbers as inputs and produces a 16-bit product as the output.",
"2. The module header of the DUT is: `module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);`",
"3. The DUT has the following inputs and outputs:\n- Input: `clk` (clock signal)\n- Input: `rst` (reset signal)\n- Input: `a` (8-bit unsigned number, range: 0 to 255)\n- Input: `b` (8-bit unsigned number, range: 0 to 255)\n- Output: `y` (16-bit unsigned number, range: 0 to 65535)",
"4. The testbench should generate a series of test cases to verify the functionality of the DUT. Each test case should include:\n- A set of input values for `a` and `b`\n- The expected 16-bit product `y`",
"5. The testbench should initialize the DUT with a reset signal (`rst`) and then apply the clock signal (`clk`) to drive the DUT through its operation.",
"6. The testbench should compare the actual output `y` from the DUT with the expected output for each test case. If they match, the test case passes; otherwise, it fails.",
"7. The testbench should cover a wide range of test cases, including but not limited to:\n- Boundary conditions (e.g., `a = 0`, `b = 0`, `a = 255`, `b = 255`)\n- Random values within the range of 0 to 255\n- Special cases (e.g., `a = 1`, `b = 1`, `a = 128`, `b = 128`)"
]
}
```
This JSON response provides a detailed technical specification for the DUT and the requirements for the testbench generation task. It includes the necessary information about the inputs, outputs, and the expected behavior of the DUT, as well as the test cases that should be included in the testbench.
DUT header:
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
test scenario: (please note the test vectors below, it will help you determine the input parameters of the rules)
{
"scenario 1": "Initialize the DUT with a reset signal (rst = 1) for one clock cycle. Set clk to 0, then to 1, and back to 0 to complete one clock cycle. After the reset, set rst to 0.",
"scenario 2": "Set a = 0 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 3": "Set a = 255 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 4": "Set a = 1 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 5": "Set a = 128 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 6": "Set a = 0 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 7": "Set a = 255 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 8": "Set a = 1 and b = 255. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 9": "Set a = 255 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 10": "Set a = 128 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 11": "Set a = 0 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 12": "Set a = 1 and b = 128. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 13": "Set a = 128 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 14": "Set a = 127 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 15": "Set a = 127 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 16": "Set a = 1 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 17": "Set a = 127 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 18": "Set a = 0 and b = 127. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 19": "Set a = 64 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 20": "Set a = 64 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 21": "Set a = 1 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 22": "Set a = 64 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 23": "Set a = 0 and b = 64. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 24": "Set a = 32 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 25": "Set a = 32 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 26": "Set a = 1 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 27": "Set a = 32 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 28": "Set a = 0 and b = 32. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 29": "Set a = 16 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 30": "Set a = 16 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 31": "Set a = 1 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 32": "Set a = 16 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 33": "Set a = 0 and b = 16. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 34": "Set a = 8 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 35": "Set a = 8 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 36": "Set a = 1 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 37": "Set a = 8 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 38": "Set a = 0 and b = 8. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 39": "Set a = 4 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 40": "Set a = 4 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 41": "Set a = 1 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 42": "Set a = 4 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 43": "Set a = 0 and b = 4. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 44": "Set a = 2 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 45": "Set a = 2 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 46": "Set a = 1 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 47": "Set a = 2 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 48": "Set a = 0 and b = 2. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 49": "Set a = 1 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 50": "Set a = 1 and b = 0. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0.",
"scenario 51": "Set a = 0 and b = 1. Apply the clock signal (clk) for one cycle. Ensure that the clock signal transitions from 0 to 1 and back to 0."
}
your response should only contain python code. For convenience, you can use binary or hexadecimal format in python. For example: 0b0010 and 0x1a
########## assistant ##########
```python
# Core rules for the 8-bit multiplier DUT
def calculate_product(a, b):
"""
Calculate the 16-bit product of two 8-bit unsigned numbers.
:param a: 8-bit unsigned number (0 to 255)
:param b: 8-bit unsigned number (0 to 255)
:return: 16-bit unsigned product (0 to 65535)
"""
return a * b
# Example usage:
# a = 0b00000001 # 1 in binary
# b = 0b00000010 # 2 in binary
# expected_product = calculate_product(a, b)
# print(f"Expected product: {expected_product} (binary: {bin(expected_product)})")
# Test scenarios
test_scenarios = [
{"a": 0x00, "b": 0x00}, # 0 * 0
{"a": 0xFF, "b": 0xFF}, # 255 * 255
{"a": 0x01, "b": 0x01}, # 1 * 1
{"a": 0x80, "b": 0x80}, # 128 * 128
{"a": 0x00, "b": 0xFF}, # 0 * 255
{"a": 0xFF, "b": 0x00}, # 255 * 0
{"a": 0x01, "b": 0xFF}, # 1 * 255
{"a": 0xFF, "b": 0x01}, # 255 * 1
{"a": 0x80, "b": 0x00}, # 128 * 0
{"a": 0x00, "b": 0x80}, # 0 * 128
{"a": 0x01, "b": 0x80}, # 1 * 128
{"a": 0x80, "b": 0x01}, # 128 * 1
{"a": 0x7F, "b": 0x7F}, # 127 * 127
{"a": 0x7F, "b": 0x01}, # 127 * 1
{"a": 0x01, "b": 0x7F}, # 1 * 127
{"a": 0x7F, "b": 0x00}, # 127 * 0
{"a": 0x00, "b": 0x7F}, # 0 * 127
{"a": 0x40, "b": 0x40}, # 64 * 64
{"a": 0x40, "b": 0x01}, # 64 * 1
{"a": 0x01, "b": 0x40}, # 1 * 64
{"a": 0x40, "b": 0x00}, # 64 * 0
{"a": 0x00, "b": 0x40}, # 0 * 64
{"a": 0x20, "b": 0x20}, # 32 * 32
{"a": 0x20, "b": 0x01}, # 32 * 1
{"a": 0x01, "b": 0x20}, # 1 * 32
{"a": 0x20, "b": 0x00}, # 32 * 0
{"a": 0x00, "b": 0x20}, # 0 * 32
{"a": 0x10, "b": 0x10}, # 16 * 16
{"a": 0x10, "b": 0x01}, # 16 * 1
{"a": 0x01, "b": 0x10}, # 1 * 16
{"a": 0x10, "b": 0x00}, # 16 * 0
{"a": 0x00, "b": 0x10}, # 0 * 16
{"a": 0x08, "b": 0x08}, # 8 * 8
{"a": 0x08, "b": 0x01}, # 8 * 1
{"a": 0x01, "b": 0x08}, # 1 * 8
{"a": 0x08, "b": 0x00}, # 8 * 0
{"a": 0x00, "b": 0x08}, # 0 * 8
{"a": 0x04, "b": 0x04}, # 4 * 4
{"a": 0x04, "b": 0x01}, # 4 * 1
{"a": 0x01, "b": 0x04}, # 1 * 4
{"a": 0x04, "b": 0x00}, # 4 * 0
{"a": 0x00, "b": 0x04}, # 0 * 4
{"a": 0x02, "b": 0x02}, # 2 * 2
{"a": 0x02, "b": 0x01}, # 2 * 1
{"a": 0x01, "b": 0x02}, # 1 * 2
{"a": 0x02, "b": 0x00}, # 2 * 0
{"a": 0x00, "b": 0x02}, # 0 * 2
{"a": 0x01, "b": 0x01}, # 1 * 1
{"a": 0x01, "b": 0x00}, # 1 * 0
{"a": 0x00, "b": 0x01}, # 0 * 1
]
# Generate expected values for each test scenario
expected_values = []
for scenario in test_scenarios:
a = scenario["a"]
b = scenario["b"]
expected_product = calculate_product(a, b)
expected_values.append({"a": a, "b": b, "expected_product": expected_product})
# Print the expected values
for i, scenario in enumerate(expected_values):
print(f"Scenario {i+1}: a = 0x{scenario['a']:02X}, b = 0x{scenario['b']:02X}, Expected Product = 0x{scenario['expected_product']:04X}")
```

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############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
1. Your task is to complete a given verilog testbench code. This testbench is for a verilog RTL module code (we call it as "DUT", device under test). This circuit is a sequential circuit. The infomation we have is
- 1.1. the problem description that guides student to write the RTL code (DUT) and the header of the "DUT".
- 1.2. the module header.
- 1.3. test scenarios which determines values and sequential information of test vectors
- 1.4. the testbench structure
- 1.5. the instruction of writing our testbench
DUT header:
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
Your other information:
RTL circuit problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
IMPORTANT - test scenario (Please determine the values of input signals according to these test scenarios.):
{
"scenario 1": "Initialize the DUT by asserting the reset signal (rst) for one clock cycle. Set both inputs a and b to 0x00.",
"scenario 2": "After de-asserting the reset signal, set both inputs a and b to 0x01 and wait for one clock cycle.",
"scenario 3": "Set input a to 0x00 and input b to 0xFF, and wait for one clock cycle.",
"scenario 4": "Set input a to 0xFF and input b to 0x00, and wait for one clock cycle.",
"scenario 5": "Set both inputs a and b to 0xFF and wait for one clock cycle.",
"scenario 6": "Set input a to 0x80 and input b to 0x80, and wait for one clock cycle.",
"scenario 7": "Set input a to 0x01 and input b to 0x80, and wait for one clock cycle.",
"scenario 8": "Set input a to 0x80 and input b to 0x01, and wait for one clock cycle.",
"scenario 9": "Set input a to 0x0A and input b to 0x0B, and wait for one clock cycle.",
"scenario 10": "Set input a to 0x7F and input b to 0x7F, and wait for one clock cycle.",
"scenario 11": "Set input a to 0x0F and input b to 0xF0, and wait for one clock cycle.",
"scenario 12": "Set input a to 0x00 and input b to 0x00, and wait for one clock cycle.",
"scenario 13": "Set input a to 0x0F and input b to 0x0F, and wait for one clock cycle.",
"scenario 14": "Set input a to 0x0E and input b to 0x0E, and wait for one clock cycle.",
"scenario 15": "Set input a to 0x0D and input b to 0x0D, and wait for one clock cycle."
}
below is the given testbench codes:
`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
top_module DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// write your scenario checking codes here, according to scenario information
$fclose(file);
$finish;
end
endmodule
The testbench does not need to check the DUT's output but only export the signals of DUT. Please export the signals of DUT to a file named "TBout.txt" at the end of each scenario. The template is given below:
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
The variables are already declared. The clock signal is already prepared. This output will be used to check the correctness of the DUT's output later.
please only use "#10" as the delay when you need. If you need longer delay, you can use multiple "#10", such as "#10; #10; #10;". Avoid meaningless long delay in your code.
If you need a loop in a scenario to check multiple time points, use "repeat" loop. for exmaple:
```
// scenario x
scenario = x;
signal_1 = 1;
repeat(5) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
end
```
Please determine the input signal's exact values according to given test scenarios.
Note: please complete the last initial code part (marked in the given testbench template). You should give me the completed full code. The testbench template above is to help you generate the code. You must use %d when exporting values.
please generate the full testbench code. please only reply verilog codes, no other words.
########## assistant ##########
```verilog
`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule
```

310
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############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
given the scenario based verilog testbench code below:
`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule
please help me to export the input of DUT module by using code below:
[IMPORTANT]:
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
you should insert the code above into scenario checking part. In each scenario, you should insert the code above after the input of DUT module changed. Don't delete the existing $display codes.
For example, for a circuit that has two input signals changed at different times in one scenario, the original code is like this:
- original code:
// scenario 1 begins
scenario = 1;
signal_1 = 1;
// insert $fdisplay here
#10;
signal_2 = 1;
// insert $fdisplay here
#10;
$fdisplay(file, "[check]scenario: %d, signal_1 = %d, signal_2 = %d", scenario, signal_1, signal_2); // this should be reserved. Never change the existing codes.
#10;
// scenario 1 ends
- after insertion:
// scenario 1 begins
scenario = 1;
signal_1 = 1;
$fdisplay(file, "scenario: %d, signal_1 = %d, signal_2 = %d", scenario, signal_1, signal_2);
#10;
signal_2 = 1;
$fdisplay(file, "scenario: %d, signal_1 = %d, signal_2 = %d", scenario, signal_1, signal_2);
#10;
$fdisplay(file, "[check]scenario: %d, signal_1 = %d, signal_2 = %d", scenario, signal_1, signal_2);
#10;
// scenario 1 ends
please insert codes according to the rules above. DO NOT modify other codes! please reply the modified full codes. please only reply verilog codes, no other words.
########## assistant ##########
```verilog
`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule
```

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############################## conversation begin ##############################
########## system ##########
You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you.
########## user ##########
1. background: Your task is to verify the functional correctness of a verilog RTL module code (we call it as "DUT", device under test). This module is a sequential circuit. Our plan is to first export the signals (input and output) of the DUT under test scenarios. Then, we will use a python script to check the correctness of DUT.
2. You are in stage 5. In this stage, we already exported the signals of DUT. The signals are like below: (the signal names are real, but the values are just for example, clock signals are not included, each vector represents a new clock cycle)
[{'check_en': False, 'scenario': 1, 'rst': 1, 'a': 1, 'b': 1, 'y': 1}, {'check_en': False, 'scenario': 1, 'rst': 1, 'a': 1, 'b': 1, 'y': 1}, {'check_en': True, 'scenario': 1, 'rst': 1, 'a': 1, 'b': 1, 'y': 1}]
Here's the explanation of some special signals in signal vectors:
- "scenario": The "scenario" is not DUT's signal but to tell you the current scenario index.
- "check_en": The "check_en" signal is not from the DUT. "Check_en" is a bool value to tell you this is the time to check the output of DUT. It is related to the class method "check" (we will explain it later). After checking the output, a new scenario will start.
3. Your current task is: write a python class "GoldenDUT". This python class can represent the golden DUT (the ideal one). In your "GoldenDUT", you should do the following things:
- 3.1. write a method "def __init__(self)". Set the inner states/values of the golden DUT. These values have suffix "_reg". The initial value of these inner values is "x", but later will be digits. The "__init__" method has no input parameters except "self".
- 3.2. write a method "def load(self, signal_vector)". This method is to load the important input signals and the inner values of "GoldenDUT" shall change according to the input signals. There is no clock signal in the input signal vector, every time the "load" method is called, it means a new clock cycle. The initial values "x" should be changed according to the input signals. This method has no return value.
- 3.3. write a method "def check(self, signal_vector)". This method is to determine the expected output values and compare them with output signals from DUT. It should return True or False only. If return false, please print the error message. Hint: you can use code like "print(f"Scenario: {signal_vector['scenario']}, expected: a={a_reg}, observed a={a_observed}")" to print, suppose "a" is the output signal's name.
- 3.4. write other methods you need, they can be called by "load" or "check".
- 3.5. the input of "load" and "check" is the signal vector. The signal vector is a dictionary, the key is the signal name, the value is the signal value.
4. Other information:
- You can use binary (like 0x1101), hexadecimal (like 0x1a) or normal number format in python.
- if the bit width of one variable is limited, use bit mask to assure the correctness of the value.
- you can import numpy, math, scipy or other python libraries to help you write the python class.
5. You have the information below to help you check the correctness of DUT:
DUT circuit problem description:
一个8位乘法器，输入两个8位无符号数，输出16位乘积
The header of DUT (note the input and output signals):
module example(input clk, input rst, input [7:0] a, input [7:0] b, output [15:0] y);
Here is the basic rules in python for the module. It was generated in previous stage. You can use it as a reference, but you should write your own python script. This is just for your better understanding. You can use them or not in your python class
import numpy as np
def multiply_8bit(a, b):
"""
This function multiplies two 8-bit unsigned integers and returns the 16-bit result.
Parameters:
a (int): 8-bit unsigned integer (0x00 to 0xFF)
b (int): 8-bit unsigned integer (0x00 to 0xFF)
Returns:
int: 16-bit unsigned integer (0x0000 to 0xFFFF)
"""
# Ensure inputs are 8-bit unsigned integers
a = a & 0xFF
b = b & 0xFF
# Perform the multiplication
product = a * b
# Ensure the result is 16-bit
product = product & 0xFFFF
return product
# Test scenarios
test_scenarios = [
(0x00, 0x00), # Scenario 1
(0x01, 0x01), # Scenario 2
(0x00, 0xFF), # Scenario 3
(0xFF, 0x00), # Scenario 4
(0xFF, 0xFF), # Scenario 5
(0x80, 0x80), # Scenario 6
(0x01, 0x80), # Scenario 7
(0x80, 0x01), # Scenario 8
(0x0A, 0x0B), # Scenario 9
(0x7F, 0x7F), # Scenario 10
(0x0F, 0xF0), # Scenario 11
(0x00, 0x00), # Scenario 12
(0x0F, 0x0F), # Scenario 13
(0x0E, 0x0E), # Scenario 14
(0x0D, 0x0D) # Scenario 15
]
# Generate expected results for each test scenario
expected_results = [multiply_8bit(a, b) for a, b in test_scenarios]
# Print the expected results
for i, (a, b) in enumerate(test_scenarios):
print(f"Scenario {i+1}: a = 0x{a:02X}, b = 0x{b:02X} -> Expected y = 0x{expected_results[i]:04X}")
[IMPORTANT]
I will repeat the important information:
3. Your current task is: write a python class "GoldenDUT". This python class can represent the golden DUT (the ideal one). In your "GoldenDUT", you should do the following things:
- 3.1. write a method "def __init__(self)". Set the inner states/values of the golden DUT. These values have suffix "_reg". The initial value of these inner values should be digits. You can set the initial values according to information or just "0"s. The "__init__" method has no input parameters except "self".
- 3.2. write a method "def load(self, signal_vector)". This method is to load the important input signals and the inner values of "GoldenDUT" shall change according to the input signals. There is no clock signal in the input signal vector, every time the "load" method is called, it means a new clock cycle. The initial values "x" should be changed according to the input signals. This method has no return value.
- 3.3. write a method "def check(self, signal_vector)". This method is to determine the expected output values and compare them with output signals from DUT. It should return True or False only. If return false, please print the error message. Hint: you can use code like "print(f"Scenario: {signal_vector['scenario']}, expected: a={a_reg}, observed a={a_observed}")" to print, suppose "a" is the output signal's name.
- 3.4. write other methods you need, they can be called by "load" or "check".
- 3.5. the input of "load" and "check" is the signal vector. The signal vector is a dictionary, the key is the signal name, the value is the signal value.
4. Other information:
- You can use binary (like 0x1101), hexadecimal (like 0x1a) or normal number format in python.
- if the bit width of one variable is limited, use bit mask to assure the correctness of the value.
- you can import numpy, math, scipy or other python libraries to help you write the python class.
please only reply the python codes of the python class. no other words.
########## assistant ##########
```python
class GoldenDUT:
def __init__(self):
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
self.rst_reg = 1
def load(self, signal_vector):
self.a_reg = signal_vector['a'] & 0xFF
self.b_reg = signal_vector['b'] & 0xFF
self.rst_reg = signal_vector['rst']
if self.rst_reg == 1:
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
else:
self.y_reg = self.multiply_8bit(self.a_reg, self.b_reg)
def check(self, signal_vector):
expected_y = self.multiply_8bit(self.a_reg, self.b_reg)
observed_y = signal_vector['y'] & 0xFFFF
if expected_y != observed_y:
print(f"Scenario: {signal_vector['scenario']}, expected: y=0x{expected_y:04X}, observed: y=0x{observed_y:04X}")
return False
return True
def multiply_8bit(self, a, b):
a = a & 0xFF
b = b & 0xFF
product = a * b
product = product & 0xFFFF
return product
```

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output/example_mul/example_mul/1_TBgen/stage_checklist.txt Normal file
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[SYSTEM PRECHECK] All scenarios are included in the testbench code. You can continue to the next stage.

30
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/TBout.txt Normal file
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scenario: 1, clk = 0, rst = 1, a = 0, b = 0, y = 0
[check]scenario: 1, clk = 1, rst = 1, a = 0, b = 0, y = 0
scenario: 2, clk = 1, rst = 0, a = 1, b = 1, y = 1
[check]scenario: 2, clk = 1, rst = 0, a = 1, b = 1, y = 1
scenario: 3, clk = 1, rst = 0, a = 0, b = 255, y = 0
[check]scenario: 3, clk = 1, rst = 0, a = 0, b = 255, y = 0
scenario: 4, clk = 1, rst = 0, a = 255, b = 0, y = 0
[check]scenario: 4, clk = 1, rst = 0, a = 255, b = 0, y = 0
scenario: 5, clk = 1, rst = 0, a = 255, b = 255, y = 65025
[check]scenario: 5, clk = 1, rst = 0, a = 255, b = 255, y = 65025
scenario: 6, clk = 1, rst = 0, a = 128, b = 128, y = 16384
[check]scenario: 6, clk = 1, rst = 0, a = 128, b = 128, y = 16384
scenario: 7, clk = 1, rst = 0, a = 1, b = 128, y = 128
[check]scenario: 7, clk = 1, rst = 0, a = 1, b = 128, y = 128
scenario: 8, clk = 1, rst = 0, a = 128, b = 1, y = 128
[check]scenario: 8, clk = 1, rst = 0, a = 128, b = 1, y = 128
scenario: 9, clk = 1, rst = 0, a = 10, b = 11, y = 110
[check]scenario: 9, clk = 1, rst = 0, a = 10, b = 11, y = 110
scenario: 10, clk = 1, rst = 0, a = 127, b = 127, y = 16129
[check]scenario: 10, clk = 1, rst = 0, a = 127, b = 127, y = 16129
scenario: 11, clk = 1, rst = 0, a = 15, b = 240, y = 3600
[check]scenario: 11, clk = 1, rst = 0, a = 15, b = 240, y = 3600
scenario: 12, clk = 1, rst = 0, a = 0, b = 0, y = 0
[check]scenario: 12, clk = 1, rst = 0, a = 0, b = 0, y = 0
scenario: 13, clk = 1, rst = 0, a = 15, b = 15, y = 225
[check]scenario: 13, clk = 1, rst = 0, a = 15, b = 15, y = 225
scenario: 14, clk = 1, rst = 0, a = 14, b = 14, y = 196
[check]scenario: 14, clk = 1, rst = 0, a = 14, b = 14, y = 196
scenario: 15, clk = 1, rst = 0, a = 13, b = 13, y = 169
[check]scenario: 15, clk = 1, rst = 0, a = 13, b = 13, y = 169

10
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/example_mul.v Normal file
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module example(
input clk,
input rst,
input [7:0] a,
input [7:0] b,
output [15:0] y
);
assign y = a * b;
endmodule

82
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/example_mul_tb.py Normal file
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class GoldenDUT:
def __init__(self):
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
self.rst_reg = 1
def load(self, signal_vector):
self.a_reg = signal_vector['a'] & 0xFF
self.b_reg = signal_vector['b'] & 0xFF
self.rst_reg = signal_vector['rst']
if self.rst_reg == 1:
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
else:
self.y_reg = self.multiply_8bit(self.a_reg, self.b_reg)
def check(self, signal_vector):
expected_y = self.multiply_8bit(self.a_reg, self.b_reg)
observed_y = signal_vector['y'] & 0xFFFF
if expected_y != observed_y:
print(f"Scenario: {signal_vector['scenario']}, expected: y=0x{expected_y:04X}, observed: y=0x{observed_y:04X}")
return False
return True
def multiply_8bit(self, a, b):
a = a & 0xFF
b = b & 0xFF
product = a * b
product = product & 0xFFFF
return product
def check_dut(vectors_in):
golden_dut = GoldenDUT()
failed_scenarios = []
for vector in vectors_in:
if vector["check_en"]:
check_pass = golden_dut.check(vector)
if check_pass:
print(f"Passed; vector: {vector}")
else:
print(f"Failed; vector: {vector}")
failed_scenarios.append(vector["scenario"])
golden_dut.load(vector)
return failed_scenarios
def SignalTxt_to_dictlist(txt:str):
signals = []
lines = txt.strip().split("\n")
for line in lines:
signal = {}
if line.startswith("[check]"):
signal["check_en"] = True
line = line[7:]
elif line.startswith("scenario"):
signal["check_en"] = False
else:
continue
line = line.strip().split(", ")
for item in line:
if "scenario" in item:
item = item.split(": ")
signal["scenario"] = item[1].replace(" ", "")
else:
item = item.split(" = ")
key = item[0]
value = item[1]
if ("x" not in value) and ("X" not in value) and ("z" not in value):
signal[key] = int(value)
else:
if ("x" in value) or ("X" in value):
signal[key] = 0 # used to be "x"
else:
signal[key] = 0 # used to be "z"
signals.append(signal)
return signals
with open("TBout.txt", "r") as f:
txt = f.read()
vectors_in = SignalTxt_to_dictlist(txt)
tb_pass = check_dut(vectors_in)
print(tb_pass)

138
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/example_mul_tb.v Normal file
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`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule

226
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/run.vvp Normal file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
S_0x5cd5353522d0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x5cd535352460 .scope module, "testbench" "testbench" 3 2;
.timescale -9 -12;
v0x5cd535391920_0 .var "a", 7 0;
v0x5cd535391a00_0 .var "b", 7 0;
v0x5cd535391ad0_0 .var "clk", 0 0;
v0x5cd535391bd0_0 .var/i "file", 31 0;
v0x5cd535391c70_0 .var "rst", 0 0;
v0x5cd535391d10_0 .var/i "scenario", 31 0;
v0x5cd535391db0_0 .net "y", 15 0, L_0x5cd535392170; 1 drivers
S_0x5cd535318490 .scope module, "DUT" "example" 3 11, 4 2 0, S_0x5cd535352460;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 8 "a";
.port_info 3 /INPUT 8 "b";
.port_info 4 /OUTPUT 16 "y";
v0x5cd535368690_0 .net *"_ivl_0", 15 0, L_0x5cd535391ea0; 1 drivers
L_0x7475544ce018 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
v0x5cd535391160_0 .net *"_ivl_3", 7 0, L_0x7475544ce018; 1 drivers
v0x5cd535391240_0 .net *"_ivl_4", 15 0, L_0x5cd535392010; 1 drivers
L_0x7475544ce060 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
v0x5cd535391330_0 .net *"_ivl_7", 7 0, L_0x7475544ce060; 1 drivers
v0x5cd535391410_0 .net "a", 7 0, v0x5cd535391920_0; 1 drivers
v0x5cd535391540_0 .net "b", 7 0, v0x5cd535391a00_0; 1 drivers
v0x5cd535391620_0 .net "clk", 0 0, v0x5cd535391ad0_0; 1 drivers
v0x5cd5353916e0_0 .net "rst", 0 0, v0x5cd535391c70_0; 1 drivers
v0x5cd5353917a0_0 .net "y", 15 0, L_0x5cd535392170; alias, 1 drivers
L_0x5cd535391ea0 .concat [ 8 8 0 0], v0x5cd535391920_0, L_0x7475544ce018;
L_0x5cd535392010 .concat [ 8 8 0 0], v0x5cd535391a00_0, L_0x7475544ce060;
L_0x5cd535392170 .arith/mult 16, L_0x5cd535391ea0, L_0x5cd535392010;
.scope S_0x5cd535352460;
T_0 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5cd535391ad0_0, 0, 1;
T_0.0 ;
%delay 5000, 0;
%load/vec4 v0x5cd535391ad0_0;
%inv;
%store/vec4 v0x5cd535391ad0_0, 0, 1;
%jmp T_0.0;
%end;
.thread T_0;
.scope S_0x5cd535352460;
T_1 ;
%vpi_func 3 25 "$fopen" 32, "TBout.txt", "w" {0 0 0};
%store/vec4 v0x5cd535391bd0_0, 0, 32;
%end;
.thread T_1;
.scope S_0x5cd535352460;
T_2 ;
%pushi/vec4 1, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5cd535391c70_0, 0, 1;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 32 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 34 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 2, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5cd535391c70_0, 0, 1;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 39 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 41 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 3, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 46 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 48 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 4, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 53 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 55 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 5, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 60 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 62 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 6, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 67 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 69 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 7, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 74 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 76 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 8, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 81 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 83 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 9, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 10, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 11, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 88 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 90 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 10, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 127, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 127, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 95 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 97 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 11, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 102 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 104 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 12, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 109 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 111 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 13, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 15, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 116 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 118 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 14, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 14, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 14, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 123 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 125 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%pushi/vec4 15, 0, 32;
%store/vec4 v0x5cd535391d10_0, 0, 32;
%pushi/vec4 13, 0, 8;
%store/vec4 v0x5cd535391920_0, 0, 8;
%pushi/vec4 13, 0, 8;
%store/vec4 v0x5cd535391a00_0, 0, 8;
%vpi_call/w 3 130 "$fdisplay", v0x5cd535391bd0_0, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%delay 10000, 0;
%vpi_call/w 3 132 "$fdisplay", v0x5cd535391bd0_0, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", v0x5cd535391d10_0, v0x5cd535391ad0_0, v0x5cd535391c70_0, v0x5cd535391920_0, v0x5cd535391a00_0, v0x5cd535391db0_0 {0 0 0};
%vpi_call/w 3 134 "$fclose", v0x5cd535391bd0_0 {0 0 0};
%vpi_call/w 3 135 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"-";
"example_mul_tb.v";
"example_mul.v";

15
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/run_info.txt Normal file
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@@ -0,0 +1,15 @@
iverilog simulation passed!
iverilog cmd 1:
/usr/bin/iverilog -g2012 -o run.vvp example_mul.v example_mul_tb.v
iverilog cmd 1 output:
iverilog cmd 1 error:
iverilog cmd 2:
/usr/bin/vvp run.vvp
iverilog cmd 2 output:
example_mul_tb.v:135: $finish called at 290000 (1ps)
iverilog cmd 2 error:

24
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/run_info_py.txt Normal file
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@@ -0,0 +1,24 @@
python compilation passed!
###output:
Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'rst': 1, 'a': 0, 'b': 0, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'rst': 0, 'a': 1, 'b': 1, 'y': 1}
Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'rst': 0, 'a': 0, 'b': 255, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'rst': 0, 'a': 255, 'b': 0, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'rst': 0, 'a': 255, 'b': 255, 'y': 65025}
Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'rst': 0, 'a': 128, 'b': 128, 'y': 16384}
Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'rst': 0, 'a': 1, 'b': 128, 'y': 128}
Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'rst': 0, 'a': 128, 'b': 1, 'y': 128}
Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'rst': 0, 'a': 10, 'b': 11, 'y': 110}
Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'rst': 0, 'a': 127, 'b': 127, 'y': 16129}
Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'rst': 0, 'a': 15, 'b': 240, 'y': 3600}
Passed; vector: {'check_en': True, 'scenario': '12', 'clk': 1, 'rst': 0, 'a': 0, 'b': 0, 'y': 0}
Passed; vector: {'check_en': True, 'scenario': '13', 'clk': 1, 'rst': 0, 'a': 15, 'b': 15, 'y': 225}
Passed; vector: {'check_en': True, 'scenario': '14', 'clk': 1, 'rst': 0, 'a': 14, 'b': 14, 'y': 196}
Passed; vector: {'check_en': True, 'scenario': '15', 'clk': 1, 'rst': 0, 'a': 13, 'b': 13, 'y': 169}
[]
###error:

2
output/example_mul/example_mul/3_TBeval/eval1_GoldenRTL/vlist.txt Normal file
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@@ -0,0 +1,2 @@
example_mul.v
example_mul_tb.v

10
output/example_mul/example_mul/DUT.v Normal file
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@@ -0,0 +1,10 @@
module example(
input clk,
input rst,
input [7:0] a,
input [7:0] b,
output [15:0] y
);
assign y = a * b;
endmodule

82
output/example_mul/example_mul/final_TB.py Normal file
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@@ -0,0 +1,82 @@
class GoldenDUT:
def __init__(self):
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
self.rst_reg = 1
def load(self, signal_vector):
self.a_reg = signal_vector['a'] & 0xFF
self.b_reg = signal_vector['b'] & 0xFF
self.rst_reg = signal_vector['rst']
if self.rst_reg == 1:
self.a_reg = 0
self.b_reg = 0
self.y_reg = 0
else:
self.y_reg = self.multiply_8bit(self.a_reg, self.b_reg)
def check(self, signal_vector):
expected_y = self.multiply_8bit(self.a_reg, self.b_reg)
observed_y = signal_vector['y'] & 0xFFFF
if expected_y != observed_y:
print(f"Scenario: {signal_vector['scenario']}, expected: y=0x{expected_y:04X}, observed: y=0x{observed_y:04X}")
return False
return True
def multiply_8bit(self, a, b):
a = a & 0xFF
b = b & 0xFF
product = a * b
product = product & 0xFFFF
return product
def check_dut(vectors_in):
golden_dut = GoldenDUT()
failed_scenarios = []
for vector in vectors_in:
if vector["check_en"]:
check_pass = golden_dut.check(vector)
if check_pass:
print(f"Passed; vector: {vector}")
else:
print(f"Failed; vector: {vector}")
failed_scenarios.append(vector["scenario"])
golden_dut.load(vector)
return failed_scenarios
def SignalTxt_to_dictlist(txt:str):
signals = []
lines = txt.strip().split("\n")
for line in lines:
signal = {}
if line.startswith("[check]"):
signal["check_en"] = True
line = line[7:]
elif line.startswith("scenario"):
signal["check_en"] = False
else:
continue
line = line.strip().split(", ")
for item in line:
if "scenario" in item:
item = item.split(": ")
signal["scenario"] = item[1].replace(" ", "")
else:
item = item.split(" = ")
key = item[0]
value = item[1]
if ("x" not in value) and ("X" not in value) and ("z" not in value):
signal[key] = int(value)
else:
if ("x" in value) or ("X" in value):
signal[key] = 0 # used to be "x"
else:
signal[key] = 0 # used to be "z"
signals.append(signal)
return signals
with open("TBout.txt", "r") as f:
txt = f.read()
vectors_in = SignalTxt_to_dictlist(txt)
tb_pass = check_dut(vectors_in)
print(tb_pass)

138
output/example_mul/example_mul/final_TB.v Normal file
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@@ -0,0 +1,138 @@
`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule

29
output/example_mul/example_mul/run_info.json Normal file
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@@ -0,0 +1,29 @@
{
"task_id": "example_mul",
"task_number": 1,
"time": 372.62,
"prompt_tokens": 8593,
"completion_tokens": 6050,
"token_cost": 0.5348599999999999,
"ERROR(incomplete)": false,
"op_record": [
"gen",
"syncheck",
"eval"
],
"reboot_times": 0,
"max_iter": 10,
"coverage": 0.0,
"circuit_type": "SEQ",
"checklist_worked": false,
"scenario_num": 15,
"Eval0_pass": true,
"Eval0_iv_pass": true,
"debug_iter_iv": 0,
"iv_runing_time": 0.03,
"Eval0_py_pass": true,
"debug_iter_py": 0,
"py_runing_time": 0.02,
"Eval1_pass": true,
"full_pass": null
}

8
output/example_mul/example_mul/run_info_short.json Normal file
View File

@@ -0,0 +1,8 @@
{
"task_id": "example_mul",
"eval_progress": "Eval1 - passed",
"TB_corrected": null,
"reboot_times": 0,
"time": 372.62,
"cost": 0.5348599999999999
}

16
output/example_mul/example_mul/task_log.log Normal file
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@@ -0,0 +1,16 @@
2026-03-30 15:50:24 | INFO | [example_mul] [TBgen] stage_0 ends (5.68s used)
2026-03-30 15:50:48 | INFO | [example_mul] [TBgen] stage_1 ends (24.62s used)
2026-03-30 15:51:23 | INFO | [example_mul] [TBgen] stage_2 ends (34.70s used)
2026-03-30 15:51:53 | INFO | [example_mul] [TBgen] stage_3 ends (29.57s used)
2026-03-30 15:53:48 | INFO | [example_mul] [TBgen] stage_4 ends (115.37s used)
2026-03-30 15:53:48 | INFO | [example_mul] [TBgen] stage_checklist ends (0.00s used)
2026-03-30 15:56:14 | INFO | [example_mul] [TBgen] stage_4b ends (146.02s used)
2026-03-30 15:56:31 | INFO | [example_mul] [TBgen] stage_5 ends (16.58s used)
2026-03-30 15:56:31 | INFO | [example_mul]
2026-03-30 15:56:31 | INFO | [example_mul] [TBsim] iverilog compilation : passed!
2026-03-30 15:56:31 | INFO | [example_mul] [TBsim] python simulation : passed!
2026-03-30 15:56:31 | INFO | [example_mul] [TBsim] TBsim finished : True!
2026-03-30 15:56:31 | INFO | [example_mul]
2026-03-30 15:56:31 | INFO | [example_mul] [TBeval] Eval 1: Golden RTL checking begins
2026-03-30 15:56:31 | POSITIVE | [example_mul] [TBeval] Eval 1: Golden RTL checking passed!
2026-03-30 15:56:31 | INFO | [example_mul]

138
output/example_mul_tb.v Normal file
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`timescale 1ns / 1ps
module testbench;
reg clk;
reg rst;
reg [7:0] a;
reg [7:0] b;
wire [15:0] y;
integer file, scenario;
// DUT instantiation
example DUT (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.y(y)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// scenario 1
scenario = 1;
rst = 1; a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 2
scenario = 2;
rst = 0; a = 8'b0000_0001; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 3
scenario = 3;
a = 8'b0000_0000; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 4
scenario = 4;
a = 8'b1111_1111; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 5
scenario = 5;
a = 8'b1111_1111; b = 8'b1111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 6
scenario = 6;
a = 8'b1000_0000; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 7
scenario = 7;
a = 8'b0000_0001; b = 8'b1000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 8
scenario = 8;
a = 8'b1000_0000; b = 8'b0000_0001;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 9
scenario = 9;
a = 8'b0000_1010; b = 8'b0000_1011;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 10
scenario = 10;
a = 8'b0111_1111; b = 8'b0111_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 11
scenario = 11;
a = 8'b0000_1111; b = 8'b1111_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 12
scenario = 12;
a = 8'b0000_0000; b = 8'b0000_0000;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 13
scenario = 13;
a = 8'b0000_1111; b = 8'b0000_1111;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 14
scenario = 14;
a = 8'b0000_1110; b = 8'b0000_1110;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y); #10;
// scenario 15
scenario = 15;
a = 8'b0000_1101; b = 8'b0000_1101;
$fdisplay(file, "scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
#10;
$fdisplay(file, "[check]scenario: %d, clk = %d, rst = %d, a = %d, b = %d, y = %d", scenario, clk, rst, a, b, y);
$fclose(file);
$finish;
end
endmodule