311 lines
17 KiB
Python
311 lines
17 KiB
Python
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"""
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Description : The prompt script for pychecker workflow
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Author : Ruidi Qiu (r.qiu@tum.de)
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Time : 2024/3/22 10:40:43
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LastEdited : 2024/8/25 00:05:24
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"""
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import json
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from . import utils
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from .base_script import BaseScript, BaseScriptStage
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from .script_pychecker_CMB_new import Stage4 as Stage4_CMB, Stage5 as Stage5_CMB
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from .script_pychecker_SEQ import Stage4_SEQ, Stage4b_SEQ, Stage5_SEQ
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class WF_pychecker(BaseScript):
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"""
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stages: stage1, stage2, stage3, stage3b, stage4
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check: check "scenario list"(stage2) in stage 4
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"""
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def __init__(self, prob_data:dict, task_dir:str, config:object):
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super().__init__(prob_data, task_dir, config)
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self.max_check_iter = self.config.autoline.checklist.max
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self.py_debug_focus = True
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def make_and_run_stages(self):
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# stage0
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self.stage0 = Stage0(self.prob_data, **self.gptkwargs)
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self.stage_operation(self.stage0)
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self.circuit_type = self.stage0.circuit_type
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# stage1
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self.stage1 = Stage1(self.prob_data, **self.gptkwargs)
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self.stage_operation(self.stage1)
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# stage2
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self.stage2 = Stage2(self.prob_data, self.stage1.response, **self.gptkwargs)
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self.stage_operation(self.stage2)
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self.scenario_num = self.stage2.scenario_num
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self.scenario_dict = self.stage2.scenario_dict
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# stage3
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self.stage3 = Stage3(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage3)
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# split into CMB and SEQ
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if self.circuit_type == "CMB":
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self.make_and_run_stages_CMB()
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else:
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self.make_and_run_stages_SEQ()
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def make_and_run_stages_CMB(self):
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# stage4
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self.stage4 = Stage4_CMB(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck)
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# we perform pychecker_CMB_TB_standardization after stagechecklist because there is no stage 4b
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# self.TB_code = utils.pychecker_CMB_TB_standardization(self.TB_code, self.prob_data["header"])
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# stage5
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self.stage5 = Stage5_CMB(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5)
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def make_and_run_stages_SEQ(self):
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# stage4
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self.stage4 = Stage4_SEQ(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck)
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# stage4b
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self.stage4b = Stage4b_SEQ(self.prob_data, self.TB_code, **self.gptkwargs)
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self.stage_operation(self.stage4b)
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# stage5
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self.stage5 = Stage5_SEQ(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5)
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def make_and_run_reboot_stages(self, debug_dir):
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if self.circuit_type == "CMB":
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self.make_and_run_reboot_stages_CMB(debug_dir)
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else:
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self.make_and_run_reboot_stages_SEQ(debug_dir)
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def make_and_run_reboot_stages_CMB(self, debug_dir):
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if self.reboot_mode == "TB":
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# stage4
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self.stage4 = Stage4_CMB(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4, debug_dir, reboot_en=True)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck, debug_dir, reboot_en=True)
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# pychecker_CMB_TB_standardization
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# self.TB_code = utils.pychecker_CMB_TB_standardization(self.TB_code, self.prob_data["header"])
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elif self.reboot_mode == "PY":
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# stage5
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self.stage5 = Stage5_CMB(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5, debug_dir, reboot_en=True)
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else:
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raise ValueError("invalid reboot_mode in WF_pychecker script (circuit type: CMB)")
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def make_and_run_reboot_stages_SEQ(self, debug_dir):
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if self.reboot_mode == "TB":
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# stage4
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self.stage4 = Stage4_SEQ(self.prob_data, self.stage1.response, self.stage2.response, **self.gptkwargs)
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self.stage_operation(self.stage4, debug_dir, reboot_en=True)
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# stagechecklist
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self.stagecheck = StageChecklist(self.TB_code, self.stage2.response, self.max_check_iter, **self.gptkwargs)
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self.stage_operation(self.stagecheck, debug_dir, reboot_en=True)
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# stage4b
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self.stage4b = Stage4b_SEQ(self.prob_data, self.TB_code, **self.gptkwargs)
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self.stage_operation(self.stage4b, debug_dir, reboot_en=True)
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elif self.reboot_mode == "PY":
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# stage5
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self.stage5 = Stage5_SEQ(self.prob_data, self.stage1.response, self.stage3.response, **self.gptkwargs)
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self.stage_operation(self.stage5, debug_dir, reboot_en=True)
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else:
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raise ValueError("invalid reboot_mode in WF_pychecker script (circuit type: SEQ)")
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SIGNALTEMP_PLACEHOLDER_1 = "/* SIGNAL TEMPLATE 1 */"
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SIGNALTEMP_PLACEHOLDER_1A = "/* SIGNAL TEMPLATE 1A */"
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SIGNALTEMP_PLACEHOLDER_1B = "/* SIGNAL TEMPLATE 1B */"
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class Stage0(BaseScriptStage):
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def __init__(self, prob_data, **gptkwargs) -> None:
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super().__init__("stage_0", **gptkwargs)
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self.prob_data = prob_data
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self.circuit_type = None
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def make_prompt(self):
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self.add_prompt_line("Please generate the verilog RTL code according to the following description and header information:")
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self.add_prompt_line("problem description:")
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self.add_prompt_line(self.prob_data["description"])
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self.add_prompt_line("RTL header:")
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self.add_prompt_line(self.prob_data["header"])
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self.add_prompt_line("please only reply verilog codes. reply_format:\n```verilog\nyour_code_here...\n```")
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def postprocessing(self):
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self.response = self.extract_code(self.response, "verilog")[-1]
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self.circuit_type = utils.circuit_type_by_code(self.response)
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STAGE1_TXT1="""1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
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2. You are in the first stage. In this stage, please summarize the technical details of the DUT and give me a technical specification of the testbench generation task, so we can use it to design its corresponding testbench.
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3. The core of testbench is the testcases. It usually include two parts logically: the input signals to the DUT and the expected result signals from DUT. The testbench will send the input signals to DUT and check if the result signals are the same as the expected result signals. If they are the same, this means the DUT is passed. Otherwise the DUT fails.
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4. Your technical specification should include these sections:
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- section 1: specification of the DUT, including the module header of the RTL code. If table or other detailed data is provided in the original problem description, DO repeat them in your response. They are very important!!!
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5. your response should be in the form of JSON.
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6. below is the information including the problem description and the DUT header:"""
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STAGE1_TXT2="""your response must be in JSON form. example:
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{
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"important data": "...", # type: string. If no table, state transition or other direct data, leave this with ""
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"technical specifications": ["...", "...", ...] # each element of the list is one specification string, the starting of the string is its index
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}
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"""
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class Stage1(BaseScriptStage):
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def __init__(self, prob_data, **gptkwargs):
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gptkwargs["json_mode"] = True
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super().__init__("stage_1", **gptkwargs)
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self.prob_data = prob_data
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self.txt1 = STAGE1_TXT1
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self.txt2 = STAGE1_TXT2
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def make_prompt(self):
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self.prompt = ""
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self.add_prompt_line(self.txt1)
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# problem description
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self.add_prompt_line("RTL circuit problem description:")
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self.add_prompt_line(self.prob_data["description"])
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# DUT header
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self.add_prompt_line("DUT header:")
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self.add_prompt_line(self.prob_data["header"])
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# template
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self.add_prompt_line(self.txt2)
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# def postprocessing(self):
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# self.spec_dict = json.loads(self.response)
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STAGE2_TXT1="""1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
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2. you are in section 2. in this section, please give me the test scenarios. you only need to describe the stimulus in each test scenarios. If time is important, please inform the clock cycle information. we will use the stimulus description to generate the test vectors and send them to DUT. you must not tell the expected results even though you know that.
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3. your information is:"""
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STAGE2_TXT2="""
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you only need to describe the stimulus in each test scenarios. If time is important, please inform the clock cycle information. we will use the stimulus description to generate the test vectors and send them to DUT. you must not tell the expected results even though you know that.
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your response must be in JSON form. example:
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{
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"scenario 1": "...", # each content is a string
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"scenario 2": "...",
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"scenario 3": "...",
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...
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}"""
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class Stage2(BaseScriptStage):
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def __init__(self, prob_data, response_stage1, **gptkwargs) -> None:
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gptkwargs["json_mode"] = True
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super().__init__("stage_2", **gptkwargs)
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self.prob_data = prob_data
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self.response_stage1 = response_stage1
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self.txt1 = STAGE2_TXT1
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self.txt2 = STAGE2_TXT2
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def make_prompt(self):
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self.prompt = ""
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self.add_prompt_line(self.txt1)
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# problem description
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self.add_prompt_line("RTL circuit problem description:")
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self.add_prompt_line(self.prob_data["description"])
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# specification
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self.add_prompt_line("RTL testbench specification:")
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self.add_prompt_line(self.response_stage1)
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# DUT header
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self.add_prompt_line("DUT header:")
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self.add_prompt_line(self.prob_data["header"])
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# template
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self.add_prompt_line(self.txt2)
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def postprocessing(self):
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if "```json" in self.response:
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self.response = self.extract_code(self.response, "json")[-1]
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try:
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self.scenario_dict = json.loads(self.response)
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self.scenario_num = len(self.scenario_dict.keys())
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except:
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self.scenario_dict = None
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self.scenario_num = None
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STAGE3_TXT1="""1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The information we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements of the problem description.
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2. you are in stage 3; in this stage, please give me the core rules of an ideal DUT. you should give these rules in python. (For convenience, you can use binary or hexadecimal format in python, i.e. 0b0010 and 0x1a). Later we will use these ideal rules to generate expected values in each test scenario. currently you must only generate the core part of the rules. the input of these rules should be related to the test vectors from test scenario. the rule should give the expected values under test vectors. You don't need to consider the control signals like clk or reset, unless the core rules of this task are about these signals. You can use numpy, scipy or other third party python libraries to help you write the rules. Please import them if you need.
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3. your information is:"""
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class Stage3(BaseScriptStage):
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def __init__(self, prob_data, response_stage1, response_stage2, **gptkwargs) -> None:
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super().__init__("stage_3", **gptkwargs)
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self.prob_data = prob_data
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self.response_stage1 = response_stage1
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self.response_stage2 = response_stage2
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self.txt1 = STAGE3_TXT1
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def make_prompt(self):
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self.prompt = ""
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self.add_prompt_line(self.txt1)
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# problem description
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self.add_prompt_line("RTL circuit problem description:")
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self.add_prompt_line(self.prob_data["description"])
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# specification
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self.add_prompt_line("RTL testbench specification:")
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self.add_prompt_line(self.response_stage1)
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# DUT header
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self.add_prompt_line("DUT header:")
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self.add_prompt_line(self.prob_data["header"])
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# test scenarios
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self.add_prompt_line("test scenario: (please note the test vectors below, it will help you determine the input parameters of the rules)")
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self.add_prompt_line(self.response_stage2)
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# end
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self.add_prompt_line("your response should only contain python code. For convenience, you can use binary or hexadecimal format in python. For example: 0b0010 and 0x1a")
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def postprocessing(self):
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# extract python codes; codes may be more than one
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python_codes = self.extract_code(self.response, "python")
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response = ""
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for python_code in python_codes:
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response += python_code + "\n"
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self.response = response
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class StageChecklist(BaseScriptStage):
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def __init__(self, TB_code:str, checklist_str:str, max_iter:int, **gptkwargs) -> None:
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super().__init__("stage_checklist", **gptkwargs)
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self.checklist = checklist_str # {"scenario 1": "xxx", "scenario 2": "xxx", ...}
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self.checklist_dict = json.loads(checklist_str)
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self.missing_scenarios = []
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self.max_iter = max_iter
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self.TB_code_out = TB_code
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self.exit = False
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self.iter = 0
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self.TB_modified = False
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def make_prompt(self):
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self.prompt = ""
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self.add_prompt_line("please check the if the testbench code contains all the items in the checklist:")
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self.add_prompt_line("testbench code here...\n")
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self.add_prompt_line(self.TB_code_out + "\n")
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self.add_prompt_line("please check the if the testbench code above contains all the scenarios in the checklist:")
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self.add_prompt_line(self.checklist)
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self.add_prompt_line("please reply 'YES' if all the items are included. If some of the items are missed in testbench, please add the missing items and reply the modified testbench code (full code).")
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self.add_prompt_line("HINT: the missing scenarios may be: " + str(self.missing_scenarios))
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self.add_prompt_line("VERY IMPORTANT: please ONLY reply 'YES' or the full code modified. NEVER remove other irrelevant codes!!!")
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def postprocessing(self):
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self.iter += 1
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if "YES" in self.response or "Yes" in self.response or "yes" in self.response:
|
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|
|
self.exit = True
|
||
|
|
else:
|
||
|
|
self.TB_modified = True
|
||
|
|
self.TB_code_out = self.extract_code(self.response, "verilog")[-1]
|
||
|
|
|
||
|
|
def pre_check(self):
|
||
|
|
"""this function is called at the beginning of run() so that the stage can be skipped if needed"""
|
||
|
|
self.missing_scenarios = []
|
||
|
|
for key in self.checklist_dict.keys():
|
||
|
|
if key.replace(" ", " = ") not in self.TB_code_out:
|
||
|
|
self.missing_scenarios.append(key)
|
||
|
|
|
||
|
|
def run(self):
|
||
|
|
self.TB_modified = False
|
||
|
|
while (not self.exit) and (self.iter < self.max_iter):
|
||
|
|
self.pre_check()
|
||
|
|
if self.missing_scenarios == []:
|
||
|
|
self.exit = True
|
||
|
|
self.conversation_message += "\n[SYSTEM PRECHECK] All scenarios are included in the testbench code. You can continue to the next stage."
|
||
|
|
else:
|
||
|
|
self.make_prompt()
|
||
|
|
self.call_gpt()
|
||
|
|
self.postprocessing()
|
||
|
|
|
||
|
|
# more stages see script_pychecker_CMB and script_pychecker_SEQ
|