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TBgen_App/prompt_scripts/__pycache__/utils.cpython-312.pyc

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2026-03-30 16:46:48 +08:00
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Description : some tool functions for prompt scripts and their stages
Author : Ruidi Qiu (r.qiu@tum.de)
Time : 2024/4/25 13:26:06
LastEdited : 2024/9/3 20:55:11
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- given the header of a module, extract the signals
- output format: [{"name": "signal_name", "width": "[x:x]", "type": "input/output"}, ...]
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- input: head, like:
module top_module(
input clk,
input reset,
output reg [3:0] q);
- return:
- no check: $fdisplay(file, "scenario: %d, clk = %d, reset = %d, q = %d", scenario, clk, reset, q);
- check: $fdisplay(file, "[check]scenario: %d, clk = %d, reset = %d, q = %d", scenario, clk, reset, q);
z$fdisplay(file, "<22>);<3B>[check]r z scenario: %dz
, scenarioz
, %s = %%drz, %s<>"<22>r) r<00>ckeck_enr<00>begining<6E>ending<6E>check<63>middle1<65>middle2<65>middle1_signals<6C>middle2_signalsrs r<00>fdisplay_code_genr+s<><00><00><1E>f<EFBFBD>%<25>G<EFBFBD>"<22>H<EFBFBD> <11>F<EFBFBD>!<21>I<EFBFBD>r<EFBFBD>E<EFBFBD><13>n<EFBFBD>$<24>G<EFBFBD><1A>G<EFBFBD><18>O<EFBFBD><18>O<EFBFBD><19>3<><06><17><<3C>&<26><16>.<2E>8<>8<><0F><17>6<EFBFBD>F<EFBFBD>6<EFBFBD>N<EFBFBD>2<>2<><0F>3<> <0C><EFBFBD><13>$<24>$<24>G<EFBFBD> <0B><EFBFBD><1E>G<EFBFBD> <13>g<EFBFBD> <1D><07> '<27>&<26> 0<>0r<00>)<01>timeoutc<00><><00>t|<00>}t||<01>}t|<00>}t||<01>}t |<00>}t |<00>}t ||<01>}|S)a6
- refine the TB code
- 1. patch the weird bug of gpt generated verilog code
- 2. add $fdisplay in the repeat block if not exist
- 3. split the delay to multiple #10
- 4. add #10 in front of the second $display if there are two $display and no delay between them
- 5. add $fdisplay in front of the second #10 if there are two #10 and no $display between them
- 6. find the repeat block and change from repeat-#10-$fdisplay-#10 to #10-repeat-$fdisplay-#10
- 7. find all the $fdisplay sentence and rewrite them in a standard format
)<07> verilog_patch<63>add_fdisplay_to_repeat<61>split_delay_to_delays<79>find_and_rewrite_fdisplay<61>%add_delay_into_2displays_or_scenarios<6F>refine_repeat_fdisplay<61>add_display_into_2delays<79><02>coders r<00> pychecker_SEQ_TB_standardizationr89sU<00><00> <19><14> <1E>D<EFBFBD> !<21>$<24><06> /<2F>D<EFBFBD> <20><14> &<26>D<EFBFBD> $<24>T<EFBFBD>6<EFBFBD> 2<>D<EFBFBD> 0<><14> 6<>D<EFBFBD> !<21>$<24> '<27>D<EFBFBD> #<23>D<EFBFBD>&<26> 1<>D<EFBFBD> <0F>Krc<00>4<00>t|<00>}t||<01>}|S)z[
different from pychecker_SEQ_TB_standardization, there is no timing issues in CMB
)r/r2r6s r<00> pychecker_CMB_TB_standardizationr:Ns<00><00>
<19><14> <1E>D<EFBFBD> $<24>T<EFBFBD>6<EFBFBD> 2<>D<EFBFBD> <0F>Krr7rc<00><00>t|d<01><02>}t|d<03><02>}d}d}|}d}d} ||djd<07>}|dk(rnH||djd <09>|zd
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This function is used to find all the $fdisplay sentence and rewrite them in a standard format
T<>r#Frr N<> $fdisplayrrr
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z}d}||djd<04>}||djd<03>}|d k(r||z } |S|d k(s ||kr|}d}||z }|||} |r ||d|z }nd | vr ||d|d zz }n||d|z }||d}n||z } |S<00><>)aD
- is there are two $display and there is no delay between them, add #10 at the front of the second $display
- three cases:
- two displays: if no delay, insert
- display and scenario: if no delay, insert
- scenario and display: delete the delay (not sure if we should do, to be continue)
r Tr=z
scenario =N<>;r
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- good repeat block: $display->#10->repeat{$display->#10}n->$display->#10
- bad repeat block: $display->repeat{#10->$display->#10}n->$display->#10
- this code standardization is newly added in AutoBench2
r rINrE<00>#10r=r
rJz #10;
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|vs<01> ||xx|d zz cc<<00>dj |<05>S) ziif there are two #10 and there is no $fdisplay between them, add $fdisplay at the front of the second #10r7c<00><><00>d}d}|jd<02>}||djd<03>|z}|||dzdz}d|vr|}|jdd<01>}||fS|}|jdd<08>}||fS) Nr r=rr
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here is a patch for a weird bug of gpt generated verilog code
the bug is "initial begin ... }" or "initial { ... }"
z{\nzbegin\nrJFrr <00>}rE<00> endmoduleT)ror rtru)r<><00> vcode_linesr<73><00>i<>line<6E> line_temps rr/r/Es<><00><00>
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dvr ||d zd
}<00>-||d zd vr=||d zd k(r)||||d
jd <0A>|z}|dk(s|dk(rd} |S||d zd
}<00>t||d
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}<00><01><>|dk(r |S||<08>}d|vrd}|dk(r |S||d
}<00><01><>|S)z4
- input: code
- output: "CMB" or "SEQ"
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|_y ) z<>
1. initialize sim time, module testbench and signals
2. initialize "integer file, scenario;"
3. instantiate the DUT
4. clock generation (if have)
5. scenario based test
6. endmodule
r z'`timescale 1ns / 1ps
module testbench;
rJzinteger file, scenario;
z// DUT instantiation
<EFBFBD>
top_module<EFBFBD>DUTz8
initial begin
file = $fopen("TBout.txt", "w");
end
z<EFBFBD>// Scenario Based Test
initial begin
// write your scenario checking codes here, according to scenario information
$fclose(file);
$finish;
end
z
endmodule
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initial begin
[clk] = 0;
forever #5 [clk] = ~[clk];
end
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z?
- this function is used to initialize signals
r r<00>inputzreg rrrz;
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- this function is used to instantiate a module by signals
- the signals should be like [{"name": "a", "width": "[3:0]", "type": "input"}, ...]
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for the automatic generation of signals in testbench
target: given the DUT header, generate the signal output template
eg: if we have a DUT header like "module DUT(input a, b, c, output d, e);", the signal output template should be like "[{"check_en": 0, "scenario": 1, "a": 1, "b": 0, "c":1, "d": 0, "e": 0}, {"check_en": 1, "scenario": 1, "a": 0, "b": 0, "c":1, "d": 0, "e": 0}]"
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}|||d<<00> | Scc}w)<05><>
- header: the header of DUT
- template_scenario_idx: the scenario index in the template
- signal_value: the value of the signal in the template
- only: None: both input signal and output signal; "input": only input signal; "output": only output signal
- from header to signals in txt
- for the automatic generation of signals in testbench
- target: given the DUT header, generate the signal output template
- eg: if we have a DUT header like "module DUT(input clk, load, data, output q);", the signal output template should be like "$fdisplay(file, "scenario: %d, clk = %d, load = %d, data = %d, q = %d", scenario, clk, load, data, q);"
rr<>rGrzr")
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`timescale 1ns / 1ps
module testbench;
reg clk;
reg areset;
reg x;
wire z;
integer file, scenario;
// DUT instantiation
top_module DUT (
.clk(clk),
.areset(areset),
.x(x),
.z(z)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
file = $fopen("TBout.txt", "w");
end
// Scenario Based Test
initial begin
// Scenario 1
scenario = 1;
areset = 1;
x = 0;
repeat(2) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
areset = 0;
repeat(4) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 1, clk, areset, x, z);
#10;
end
// Scenario 2
scenario = 2;
areset = 1;
x = 0;
repeat(3) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
areset = 0;
repeat(8) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 2, clk, areset, x, z);
#10;
end
areset = 1;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 2, clk, areset, x, z);
#10;
areset = 0;
repeat(4) begin
x = 1;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 2, clk, areset, x, z);
#10;
end
// Scenario 3
scenario = 3;
areset = 0;
repeat(3) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 3, clk, areset, x, z);
#10;
end
areset = 1;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 3, clk, areset, x, z);
#10;
areset = 0;
repeat(3) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 3, clk, areset, x, z);
#10;
end
// Scenario 4
scenario = 4;
areset = 1;
x = 0;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
areset = 0;
repeat(3) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 4, clk, areset, x, z);
#10;
end
x = 0;
repeat(2) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 4, clk, areset, x, z);
#10;
end
scenario = 25; // 11001 in binary
repeat(5) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 4, clk, areset, x, z);
#10;
end
// Scenario 5
scenario = 5;
areset = 0;
repeat(8) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 5, clk, areset, x, z);
#10;
end
areset = 1;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 5, clk, areset, x, z);
#10;
areset = 0;
scenario = 170; // 10101010 in binary
repeat(8) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 5, clk, areset, x, z);
#10;
end
// Scenario 6
scenario = 6;
areset = 1;
x = 0;
repeat(4) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
areset = 0;
repeat(8) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 6, clk, areset, x, z);
#10;
end
x = 1;
repeat(5) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 6, clk, areset, x, z);
#10;
end
// Scenario 7
scenario = 7;
areset = 0;
x = 0;
repeat(5) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
x = 1;
repeat(5) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
areset = 1;
repeat(2) begin
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
end
areset = 0;
scenario = 10; // 01010 in binary
repeat(5) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 7, clk, areset, x, z);
#10;
end
// Scenario 8
scenario = 8;
areset = 1;
x = 0;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", scenario, clk, areset, x, z);
#10;
areset = 0;
scenario = 455; // 111000111 in binary
repeat(9) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 8, clk, areset, x, z);
#10;
end
areset = 1;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 8, clk, areset, x, z);
#10;
areset = 0;
scenario = 56; // 000111000 in binary
repeat(9) begin
x = scenario % 2;
scenario = scenario / 2;
$fdisplay(file, "[check]scenario: %d, clk = %d, areset = %d, x = %d, z = %d", 8, clk, areset, x, z);
#10;
end
$fclose(file);
$finish;
end
endmodulezEmodule top_module (
input clk,
input areset,
input x,
output z
);)Tr<54>)FT)r
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