TBgen_App/prompt_scripts/__pycache__/script_directgen.cpython-312.pyc

<EFBFBD>
P<>Yi	<00><00>P<00>dZd
dl
mZmZmZ
Gd<03>de<02>ZdZdZGd<07>de<03>Zy	)
z<EFBFBD>
Description :   "directgen" script for prompt scripts
Author      :   Ruidi Qiu (r.qiu@tum.de)
Time        :   2024/3/30 17:40:38
LastEdited  :   2024/5/1 17:44:05
<EFBFBD>
)<03>
BaseScript<EFBFBD>BaseScriptStage<67>TESTBENCH_TEMPLATEc<00><<00><00>eZ
dZd
Zdededef<06>f
d<05>Zd<06>Zd<07>Z	<09>x
Z
S)<08>WF_directgenz
    stages: stage1
    <20>	prob_data<74>task_dir<69>configc<00>(<00>
<01>t<00>|<00>|
||<03>
y<00>
N)<02>super<65>__init__)<05>selfrr	r
<00>	__class__s    <20><>E/home/zhang/CorrectBench/TBgen_App/prompt_scripts/script_directgen.pyrzWF_directgen.__init__s<00><><00>
<0A><07><18><19>H<EFBFBD>f<EFBFBD>5<>c
<00>f<00>t
|jf
i|j<00>
<01>
}
|j|
<01>

yr<00><04>Stage1r<00>	gptkwargs<67>stage_operation)r<00>stage1s  r<00>make_and_run_stagesz WF_directgen.make_and_run_stagess'<00><00><17><04><0E><0E>9<>$<24>.<2E>.<2E>9<><06><0C><1C><1C>V<EFBFBD>$rc<00>l<00>t
|jf
i|j<00>
<01>
}|j||
d
<01><02>
y)NT)
<01>	reboot_enr)r<00>	debug_dirrs   r<00>make_and_run_reboot_stagesz'WF_directgen.make_and_run_reboot_stagess.<00><00><17><04><0E><0E>9<>$<24>.<2E>.<2E>9<><06><0C><1C><1C>V<EFBFBD>Y<EFBFBD>$<24><1C>?r)<0B>__name__<5F>
__module__<EFBFBD>__qualname__<5F>__doc__<5F>dict<63>str<74>objectrrr<00>
__classcell__<5F>
rs
@rrr
s-<00><><00><08>
6<><14>
6<><03>
6<>F<EFBFBD>
6<>%<25>
@
rrz<>
Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT".
a

very very IMPORTANT: If all the test cases pass, the testbench should display "all test cases passed". If any one of the test cases fails, testbench should not display "all test caess passed". DO NOT generate any .vcd file.
please don't reply other words except the testbench codes.
c<00>,<00><00>eZ
dZd<04>f
d
<01>Zd<02>Zd<03>Z<05>x
ZS)rc<00>l<00>
<01>t
<00>|<00>di|<02>
<01>

|
|_t|_t
|_d
|_y)N<>)
<01>stage_1)r
rr<00>STAGE1_TXT1<54>txt1<74>STAGE1_TXT2<54>txt2<74>TB_code_out)rrrrs   <20>rrzStage1.__init__#s0<00><><00>
<0A><07><18>0<>i<EFBFBD>0<>"<22><04><0E><1F><04>	<09><1F><04>	<09><1D><04>rc
<00><>
<00>d
|_|j|j<00>

|jd<02>

|jt<00>

|jd<03>

|j|jd<00>

|jd<05>

|j|jd<00>

|j|j
<00>

y)Nr)zyour testbench template is:zproblem description:<3A>descriptionzDUT header:<3A>header)<06>prompt<70>add_prompt_liner,rrr.<00>
rs
 r<00>make_promptzStage1.make_prompt*s<><00><00><18><04><0B><0C><1C><1C>T<EFBFBD>Y<EFBFBD>Y<EFBFBD>'<27><0C><1C><1C>:<3A>;<3B><0C><1C><1C>/<2F>0<><0C><1C><1C>3<>4<><0C><1C><1C>T<EFBFBD>^<5E>^<5E>M<EFBFBD>:<3A>;<3B><0C><1C><1C>]<5D>+<2B><0C><1C><1C>T<EFBFBD>^<5E>^<5E>H<EFBFBD>5<>6<><0C><1C><1C>T<EFBFBD>Y<EFBFBD>Y<EFBFBD>'rc
<00>n<00>|j
|jd
<01>d|_
|j|_y)N<>verilog<6F><67><EFBFBD><EFBFBD><EFBFBD>)<03>extract_code<64>responser/r5s
 r<00>postprocessingzStage1.postprocessing9s+<00><00><1C>)<29>)<29>$<24>-<2D>-<2D><19>C<>B<EFBFBD>G<><04>
<0A><1F>=<3D>=<3D><04>r)<02>returnN)rrr rr6r<r%r&s
@rrr"s<00><><00><1E>
(<28>)rrN)	r!<00>base_scriptrrrrr+r-r<00>rr<00><module>r@
s;<00>


<01>
<04>
I
<01>H<>
@
<01>:<3A>
@
<01>"<04><0B><04><0B>
)<29>_<EFBFBD>
)r