TBgen_App/autoline/__pycache__/TB3_funccheck.cpython-312.pyc

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Description :   The functionality checking of the generated TB, the submodule of Autoline
Author      :   Ruidi Qiu (r.qiu@tum.de)
Time        :   2024/7/22 10:36:06
LastEdited  :   2025/2/25 22:11:13
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    ### description
    - this is the self-checking stage of our pipeline; This is the main contribution of AutoBench2。
    - This stage is to check the functional correctness of the testbench generated by AutoBench.
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        - input:
            - task_dir: the root directory of the taskTBcheck
            - task_id: the name of the problem
            - description: the description of the problem
            - module_header: the header of the module
            - TB_code_v: the generated verilog testbench code
            - TB_code_py (opt.): the generated python testbench code, if None, the tb is in a pure verilog mode
            - rtl_list (opt.): the list of llm-generated RTL codes, if None, will generate 20 RTL codes using LLM
            - rtl_num (opt.): the number of RTL codes to generate, only used when rtl_list is None
            - scenario_num (opt.): the number of scenarios in the testbench, if None, will be calculated from the failed scenarios (not accurate but won't impact the results)
            - correct_max (opt.): the maximum number of correction iterations
            - runfiles_save (opt.): whether to save the compilation files in TB_discrimination
            - discriminator_mode (default: col_full_wrong): the mode of the discriminator
            - corrector_mode (default: naive): the mode of the corrector
            - circuit_type (opt.): the type of the circuit, used in the corrector (better performance if provided)
            - rtl_compens_max_iter (default: 3): the maximum number of iterations of RTL compensation
            - rtl_compens_en (default: True): whether to enable RTL compensation
            - **LLM_kwargs: the keyword arguments for LLM (used in corrector and rtl generation), including:
                - "main_model": the main llm name used in TB_generation and correction
                - "rtlgen_model": the llm naem used in RTL generation
                - "api_key_path": the path of the api key
                - "temperature": the temperature of LLM
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        - the main function of TaskTBcheck
        - the TB check stage contains several sub-stages:
            - 1. TB discriminating
            - 2. TB correcting
        - output: will update the next action of the task, including:
            - "pass": the TB already passed the selfcheck, will go to the evaluation stage
            - "reboot": the whole pipeline will start from the very beginning
        - workflow: inital discrimination -> correction-discrimination lloop -> pass or reboot
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        - check the correctness of the testbench and return the rtl analysis results in matrix form
        - important data: the rtl list, the TB code 
        - update the following data: `scenario_matrix`, `tb_pass`, `wrong_col_index`, `correct_col_index`, `unsure_col_index`, `wrong_scen_num`
        <20>RTL_<4C>discrim<69>discrim_z!Discriminating the testbench, NO.z discriminationTrJ<00><><EFBFBD><EFBFBD><EFBFBD>FzRTL(s) z( have syntax error during discriminationN)<02>max_scen_idx<64>taskidzscenario_matrix.csv<73>
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the testbench code is consisted of both verilog and python code. The verilog code aims to generate test stimulus (under test scenarios) and drive the DUT to generate the output signal; the python code aims to check if the output vector from the DUT is correct. 
ATTENTION: The python code contains error, and your target is to find it and tell me how to correct it (you don't need to give me the code in this stage).
a	
Hints - explaination of the given python code:
the python class "GoldenDUT": This python class can represent the golden DUT (the ideal one). In "GoldenDUT", following methods are defined:
- 1. a method "def __init__(self)": Set the inner states/values of the golden DUT. These values have suffix "_reg". The initial value of these inner values is "x", but later will be digits. The "__init__" method has no input parameters except "self".
- 2. a method "def load(self, signal_vector)": This method is to load the important input signals and the inner values of "GoldenDUT" shall change according to the input signals. There is no clock signal in the input signal vector, every time the "load" method is called, it means a new clock cycle. The initial values "x" should be changed according to the input signals. This method has no return value.
- 3. a method "def check(self, signal_vector)": This method is to determine the expected output values and compare them with output signals from DUT. It should return True or False only.
a<EFBFBD>
Hints - explaination of the given python code:
The given python code contains one class "GoldenDUT". this python class can represent the golden DUT (the ideal one). By calling the inner method "check", the signal vector from DUT will be checked. The details of the golden DUT are as follows:

- a. a method "def __init__(self)". Set the inner states/values of the golden DUT. The "__init__" method has no input parameters except "self".
- b. a method "def load(self, signal_vector)". This method is to load the important input signals and get the expected output signals. it should return the expected output values. It can call other methods to help computing the expected output. It will be called by other inner methods later.
- c. a method "def check(self, signal_vector)". This method is to call "load" to get the expected output values, and compare them with output signals from DUT. It should return True or False only. It can call other methods to help checking.
- d. other methods, they can be called by "__init__", "load" or "check".
- e. the input of "load" and "check" is the signal vector. The signal vector is a dictionary, the key is the signal name, the value is the signal value.
a<EFBFBD>

please correct the python code according to the following rules:

PYTHON code rule: please do not change the original high level structure of the python code. i.e., if python code only contains one class and several functions such as init, load, check and more, only modify the implementation of the function, but do not change the name or delete the functions/class methods. you can add new class methods or functions if needed. you can use python libraries such as numpy or math.

a<EFBFBD>

i.e., your python code format in response should still be like:

class <class_name>:
    def __init__(self):
        ...(omitted)

    def load(self, ...):
        ...

    def check(self, ...):
        ...

    def <other_functions>(self, ...):
        ...

ATTENTION: please give me the corrected python code according to our previous conversation and the hints above. please give me the corrected full python code (not the part but the whole python code like I give you in our previous conversation).
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Here is the testbench code:
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z!the circuit type of this task is z<>Here is the verilog code. it contains the meaning of each scenario. you can combine the wong scenario info above and the following code to better understand the reason of failing:
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Here is the python code, it contains error, please combine it with the wrong scenario info and the verilog code to understand:
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Here is some hints for your better understanding of the python codes above:z*
please reply me with the following steps:z{
1. please analyze the reason of the failed scenarios. If possible, please find the in common between the failed scenarios.zZ
2. please analyze which part of the python code is related to the failed test scenarios (z).z<>
3. please tell me how to correct the wrong part (in natural language, do not give me the complete code implementation. please explain it in English.)z!
here is an example of the reply:z<>
1. the failed scenarios are all related to the same signal x
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The information we have the is original RTL description, the testbench code. The testbench code includes the verilog code for test scenario generation, and the python code for checking the output vector.The verilog code aims to generate test stimulus (under test scenarios) and drive the DUT to generate the output signal; the python code aims to check if the output vector from the DUT is correct.
Attention: the testbench we provide is not the perfect one, and it contains error. However, we already know the test scenarios where the testbench works correctly and the scenarios where the testbench has problem. We will provide you the scenarios index later. 
Here, firstly, is the problem description to be imporved:

z***description begins***z***description ends***a<>

please reply me with the following steps:
1. please analyze which part of the testbench (especially the python checker code) is correct and can be used to improve the description.
2. please analyze how can we improve the descriptin. for example, which part of the technical details can be more detailed, which part can be more clear, which part can be more concise.
3. please provide the improved complete description. We will directly use it in the later stages.
the format of description should be like:
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ATTENTION: please know that the provided testbench is not perfect and may contains many errors. Thus, your modification on the description should not change the function of the original description. When there are conflicts between the testbench and the description, always believe the description is correct. Do not delete the information in the description, but you can rewrite it in a better way. You can also add more details to it. But NEVER mention any scenario index because the scenarios will not be the same at the next stage.
when you answer the last question (provide the improved complete description), the descriptino should start with "z" and end with "z?". Only in this way can we recognize the improved description.
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