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TBgen_App/autoline/__pycache__/TB3_funccheck.cpython-312.pyc

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2026-03-30 16:46:48 +08:00
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Description : The functionality checking of the generated TB, the submodule of Autoline
Author : Ruidi Qiu (r.qiu@tum.de)
Time : 2024/7/22 10:36:06
LastEdited : 2025/2/25 22:11:13
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autologger)<01>log_localprefixc#<00><><00>eZdZdZd5dededededededzd eed
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d)<29><05>Zed8d*eed+edzd,efd-<2D><05>Zed.ej,ded/efd0<64><04>Zdefd1<64>Zd2efd3<64>Zd4<64>Zy)9<> TaskTBchecku<6B>
### description
- this is the self-checking stage of our pipeline; This is the main contribution of AutoBench2。
- This stage is to check the functional correctness of the testbench generated by AutoBench.
N<>task_dir<69>task_id<69> description<6F> module_header<65> TB_code_v<5F>
TB_code_py<EFBFBD>rtl_list<73>rtl_num<75> correct_max<61> runfiles_save<76>discriminator_mode<64>corrector_mode<64> circuit_type<70>rtl_compens_max_iter<65>rtl_compens_en<65> desc_improve<76>returnc <00>l<00>||_|j|_||_||_||_||_||_|du|_||_| |_ |
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| |_ |jdd<01>|_ |jdd<01>|_|jdd<05>|_|jdd<01>|_||_||_||_||_d|_d|_| |_| |_t3| <0C>|_t7|j0|j|j"<00>|_t;|d |j|j|j"<00>|_d|_|j<00>"|jA|<08>|jC<00>n$|jAtE|j<00><00>d|_#d|_$d
|_%d |_&d|_'d|_(d|_)d|_*d|_+d|_,d |_-|j<00>t]j^d <0C>g|_0y) a
- input:
- task_dir: the root directory of the taskTBcheck
- task_id: the name of the problem
- description: the description of the problem
- module_header: the header of the module
- TB_code_v: the generated verilog testbench code
- TB_code_py (opt.): the generated python testbench code, if None, the tb is in a pure verilog mode
- rtl_list (opt.): the list of llm-generated RTL codes, if None, will generate 20 RTL codes using LLM
- rtl_num (opt.): the number of RTL codes to generate, only used when rtl_list is None
- scenario_num (opt.): the number of scenarios in the testbench, if None, will be calculated from the failed scenarios (not accurate but won't impact the results)
- correct_max (opt.): the maximum number of correction iterations
- runfiles_save (opt.): whether to save the compilation files in TB_discrimination
- discriminator_mode (default: col_full_wrong): the mode of the discriminator
- corrector_mode (default: naive): the mode of the corrector
- circuit_type (opt.): the type of the circuit, used in the corrector (better performance if provided)
- rtl_compens_max_iter (default: 3): the maximum number of iterations of RTL compensation
- rtl_compens_en (default: True): whether to enable RTL compensation
- **LLM_kwargs: the keyword arguments for LLM (used in corrector and rtl generation), including:
- "main_model": the main llm name used in TB_generation and correction
- "rtlgen_model": the llm naem used in RTL generation
- "api_key_path": the path of the api key
- "temperature": the temperature of LLM
N<>
main_model<EFBFBD> rtlgen_model<65> api_key_pathzconfig/key_API.json<6F> temperature<72>r<00>naivei'Fz:main_model not found, may have trouble while correcting tb)1r<00> working_dirrr r
r r <00> pychecker_enr <00> scenario_numrr<00>getrr<00>llm_api_key_path<74>llm_temperaturerrrr<00>tolerance_for_same_wrong_scen<65>same_wrong_scen_timesrr<00>TB_discriminator<6F> discriminator<6F> TB_corrector<6F> corrector<6F> SPEC_improver<65>improver<65>rtl_newly_gen_num<75> set_rtl_num<75> rtl_list_gen<65>len<65>scenario_matrix<69>wrong_scen_num<75>previous_wrong_scen_num<75>TB_syntax_error<6F>tb_pass<73>wrong_col_index<65>correct_col_index<65>unsure_col_index<65> next_action<6F>iter_now<6F> corrected<65>logger<65>warning<6E> op_record)<13>selfrrr r
r r r rr!rrrrrrrr<00>
LLM_kwargss <20></home/zhang/CorrectBench/TBgen_App/autoline/TB3_funccheck.py<70>__init__zTaskTBcheck.__init__s<00><00>2!<21><04> <0A><1F>=<3D>=<3D><04><18><1E><04> <0C>&<26><04><18>*<2A><04><1A>"<22><04><0E>$<24><04><0F>&<26>d<EFBFBD>2<><04><19> <20><04> <0A>(<28><04><19>&<26><04><18>*<2A><04><1A>$<24>.<2E>.<2E><1C>t<EFBFBD><<3C><04><0F>&<26>N<EFBFBD>N<EFBFBD>><3E>4<EFBFBD>@<40><04><19> *<2A><0E><0E>~<7E>?T<> U<><04><1D>)<29>~<7E>~<7E>m<EFBFBD>T<EFBFBD>B<><04><1C>(<28><04><19>$8<><04>!<21>,<2C><04><1B>(<28><04><19>-.<2E><04>*<2A>%&<26><04>"<22>"4<><04><1F>,<2C><04><1B>-<2D>.@<40>A<><04><1A>%<25>d<EFBFBD>&9<>&9<>4<EFBFBD>;L<>;L<>d<EFBFBD>N_<4E>N_<4E>`<60><04><0E>%<25>k<EFBFBD>7<EFBFBD>D<EFBFBD><M<><M<>t<EFBFBD><EFBFBD><EFBFBD>`d<>`q<>`q<>r<><04> <0A>!"<22><04><1E> <0F>=<3D>=<3D> <20> <10> <1C> <1C>W<EFBFBD> %<25> <10> <1D> <1D> <1F> <11> <1C> <1C>S<EFBFBD><14><1D><1D>/<2F> 0<>#<23><04><1C><1F><04><1B>'+<2B><04>$<24>$<24><04><1C><1B><04> <0C>#<23><04><1C>!%<25><04><1E> $<24><04><1D><1F><04><18><19><04> <0A><1E><04><0E> <0F>?<3F>?<3F> "<22> <12>N<EFBFBD>N<EFBFBD>W<> X<><1B><04><0E>c<00><00>|jS)zOprotected attr. rtl_num is initialized at the beginning and will not be changed<65><01>_rtl_num<75>r?s rArzTaskTBcheck.rtl_numls<00><00><14>}<7D>}<7D>rC<00>TBcheckc
<00>p<00>d}d}|j<00>|jr tjd<03>d}d|_<00>n<>|j
rtj d<06>d|_<00>nq|jdk(rtjd <09>d|_td|jdz<00>D<00>])|_ |jdkDrU|j|jkDr<|s:tjd
|j<00>d |j<00>d <0C><05>d|_<00>n<>|jdkDr<>|j|jk(r<>|s<>|xjdz c_ |j|jk\rGtj d |j<00>d|j<00>d|j<00>d <0C><07>d|_<00>n!tj d |j<00>d|j<00>d|j<00>d<10><07>|j<00>|j<00>|j
rtj d<11>d|_n<>|jri|dkDrDtjd|<01>d<13><03>|j|j c|_|_|dz}d}n tjd<14>d|_d}n%|j|jk(rdnd|_<00><02>,|jdk(r|s|j&r|j)<00>tj d|j<00>d<17><03>|jS)a<>
- the main function of TaskTBcheck
- the TB check stage contains several sub-stages:
- 1. TB discriminating
- 2. TB correcting
- output: will update the next action of the task, including:
- "pass": the TB already passed the selfcheck, will go to the evaluation stage
- "reboot": the whole pipeline will start from the very beginning
- workflow: inital discrimination -> correction-discrimination lloop -> pass or reboot
<20>Fz?Testbench has syntax error, I give up. Reboot the whole processT<73>rebootzTestbench passed the funccheck<63>passrzFNo correction is allowed, I give up. Reboot the whole autoline processzwrong scenarios increased (z > z,), I give up, quiting the funccheck stage...z"wrong scenarios not decreased for z times (z = z), continue the correctionz/Testbench passed the funccheck after correctionzXTestbench has syntax error after correction, I still have tolerance for that (tolerance=z+). roll back and retry the self correction.zqTestbench has syntax error after correction, I don't have tolerance. I give up. Reboot the whole autoline processNz'self funccheck finished. Next Action: [<5B>])<15>discriminate_TBr4r<<00>negativer9r5<00>infor<00>ranger:r2r3r&r%<00>
correct_TB<EFBFBD>TB_code_v_before_cor<6F>TB_code_py_before_corr r r<00> improve_SPEC)r?<00> tolerance<63> syntax_errors rA<00>runzTaskTBcheck.runqsS<00><00><16> <09><1C> <0C> <0C><1C><1C><1E> <0F> <1F> <1F> <12>O<EFBFBD>O<EFBFBD>]<5D> ^<5E><1F>L<EFBFBD>'<27>D<EFBFBD> <1C> <11>\<5C>\<5C> <12>K<EFBFBD>K<EFBFBD>8<> 9<>%<25>D<EFBFBD> <1C><14><1F><1F>1<EFBFBD>$<24><16><0F><0F> h<>i<>#+<2B><04> <20>!&<26>q<EFBFBD>$<24>*:<3A>*:<3A>1<EFBFBD>*<<3C>!=<3D> [<01><04> <0A><18>M<EFBFBD>M<EFBFBD>A<EFBFBD>%<25>D<EFBFBD>,?<3F>,?<3F>$<24>B^<5E>B^<5E>,^<5E>iu<69><1A>O<EFBFBD>O<EFBFBD>&A<>$<24>BU<42>BU<42>AV<41>VY<56>Z^<5E>Zv<5A>Zv<5A>Yw<59>xd<02>%e<02>f<02>'/<2F>D<EFBFBD>$<24><19><1A>m<EFBFBD>m<EFBFBD>a<EFBFBD>'<27>d<EFBFBD>.A<>.A<>T<EFBFBD>Ea<45>Ea<45>.a<>lx<6C><18>.<2E>.<2E>!<21>3<>.<2E><1B>1<>1<>T<EFBFBD>5W<35>5W<35>W<><1E> <0B> <0B>&H<><14>Ik<49>Ik<49>Hl<48>lt<6C>uy<75>vI<02>vI<02>uJ<02>JM<02>NR<02>Nj<02>Nj<02>Mk<02>kW<03>%X<03>Y<03>+3<><04>(<28><1D><1E> <0B> <0B>&H<><14>Ic<49>Ic<49>Hd<48>dl<64>mq<6D>nA<02>nA<02>mB<02>BE<02>FJ<02>Fb<02>Fb<02>Ec<02>c}<02>%~<02><02><14><0F><0F>!<21><14>$<24>$<24>&<26><17><<3C><<3C><1A>K<EFBFBD>K<EFBFBD> Q<>R<>'-<2D>D<EFBFBD>$<24><19><19>)<29>)<29> <20>1<EFBFBD>}<7D><1E><0F><0F>+C<02>DM<02>CN<02>Ny<02>)z<02>{<02>:><3E>:S<>:S<>UY<55>Uo<55>Uo<55>7<><04><0E><04><0F>!<21>Q<EFBFBD><0E> <09>'+<2B> <0C><1E><0F><0F>)\<02>]<02>+3<><04>(<28>'+<2B> <0C><1D>/3<>}<7D>}<7D><04>@P<>@P<>/P<>8<EFBFBD>VZ<56><04> <20>A [<01>B <11> <1C> <1C><08> (<28><<3C>d<EFBFBD>FW<46>FW<46> <10> <1D> <1D> <1F><0E> <0B> <0B>=<3D>d<EFBFBD>>N<>>N<>=O<>q<EFBFBD>Q<>R<><13><1F><1F>rCr(<00> no_any_filesc <00>B
<00>d}|jjd<02>tjj |j
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} | dgk7s<01> |
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|_|D<00> cgc] } | dgk7s<01>
| <0B><02> }} t9|j<00>d|j:zk<00>r<>tjdt9|j<00><00>d|j:<00>d<16><05>|j=|j:t9|j<00>z
|j>|j@|jB|j<00>\|_} |xjD| z c_"tjF|j<00>D]<5D>} | jI|<02>s<01>tjjKtjj |j| <0A><00>s<01>]tjLdtjj |j| <0A><00><00><02><00><>tjd<18>||jdz
k(s<02><03><>tjd<19><00><03><>n|jNjQ|j.<00>\|_|_)|_*|_+|jX|_-t9|jR<00>|_,|j&|jR|jT|jVfScc} }
wcc} w)a2
- check the correctness of the testbench and return the rtl analysis results in matrix form
- important data: the rtl list, the TB code
- update the following data: `scenario_matrix`, `tb_pass`, `wrong_col_index`, `correct_col_index`, `unsure_col_index`, `wrong_scen_num`
<20>RTL_<4C>discrim<69>discrim_z!Discriminating the testbench, NO.z discriminationTrJ<00><><EFBFBD><EFBFBD><EFBFBD>FzRTL(s) z( have syntax error during discriminationN)<02> max_scen_idx<64>taskidzscenario_matrix.csv<73>,z%d)<02> delimiter<65>fmtzscenario_matrix.png<6E><00>?z%too few RTL passed the syntax check (<28>/z<), I will generate more and recheck. This is not TB's fault.<2E>rm -rf z3re-discriminate the testbench with updated RTL listz4no re-discrimination since the max iteration reached).r><00>append<6E>os<6F>path<74>joinrr:rr<rPrQrr4<00> enumerater <00> run_testbenchr r rr5<00> failed_scenarios_to_onehot_arrayr!rr1<00>np<6E>savetxt<78>draw_scenario_matrix<69>zipr0r<00>gen_rtlr r
rr-<00>listdir<69>
startswith<EFBFBD>isdir<69>systemr(<00> discriminater6r7r8r2r3)r?rY<00>rtl_dir_prefix<69>i<>failed_scenario_matrix<69>syntax_error_rtl<74>rtl_idx<64>rtl_code<64>rtl_dir<69>scenario_vector<6F>rtl<74>scen<65>gen_num<75>subdirs rArNzTaskTBcheck.discriminate_TB<54>s<><00><00> <20><0E> <0C><0E><0E><1D><1D>i<EFBFBD>(<28><1D>7<EFBFBD>7<EFBFBD><<3C><<3C><04> <0A> <0A><18>$<24>-<2D>-<2D><1F>7Q<37>R<><04><18><0E> <0B> <0B>7<><04> <0A> <0A><EFBFBD>o<EFBFBD>V<>W<><16>t<EFBFBD>0<>0<>1<>0 <16>A<EFBFBD>%'<27> "<22>#'<27>D<EFBFBD> <20>!<21> <1C>%.<2E>t<EFBFBD>}<7D>}<7D>%=<3D> 7<>!<21><07><18><1C>'<27>'<27>,<2C>,<2C>t<EFBFBD>'7<>'7<>N<EFBFBD>;K<>G<EFBFBD>TU<54>I<EFBFBD>;<3B>9W<39>X<><07>"&<26>"4<>"4<>W<EFBFBD>d<EFBFBD>n<EFBFBD>n<EFBFBD>h<EFBFBD>X\<5C>Xg<58>Xg<58>ip<69>qr<71>ir<69>tx<74>uG<02>uG<02>u^<02>Q]<02>M]<02>#_<02><0F>&<26>-<2D>-<2D>o<EFBFBD>><3E>"<22>r<EFBFBD>d<EFBFBD>*<2A>+0<>D<EFBFBD>(<28>$<24>+<2B>+<2B>G<EFBFBD>A<EFBFBD>I<EFBFBD>6<> 7<> <20>2<EFBFBD>%<25><16> <0B> <0B>g<EFBFBD>&6<>%7<>7_<37>`<60>a<><13>#<23>#<23> %<25><04> <0C><1B>$(<28>#H<>#H<>I_<49>nr<6E>n<6E>n<6E>IM<02>IU<02>IU<02>#H<>$V<02>D<EFBFBD> <20><1F><12>
<EFBFBD>
<EFBFBD>2<EFBFBD>7<EFBFBD>7<EFBFBD><<3C><<3C><04>(8<>(8<>:O<>P<>RV<52>Rf<52>Rf<52>ru<72>{<>A<02><14>)<29>)<29>$<24>*><3E>*><3E><04> <0C> <0C>b<EFBFBD>g<EFBFBD>g<EFBFBD>l<EFBFBD>l<EFBFBD>[_<>[k<>[k<>nC<02>OD<02>E<02>36<33>d<EFBFBD>m<EFBFBD>m<EFBFBD>E[<5B>2\<5C>m<>Y<EFBFBD>S<EFBFBD>$<24>`d<>ik<69>hl<68>`l<>S<EFBFBD>m<>D<EFBFBD>M<EFBFBD>7M<37>%^<5E>t<EFBFBD>QU<51>Z\<5C>Y]<5D>Q]<5D>d<EFBFBD>%^<5E> "<22>%^<5E><12>4<EFBFBD>=<3D>=<3D>!<21>C<EFBFBD><04> <0C> <0C>$4<>4<><16> <0B> <0B>C<>C<EFBFBD><04> <0A> <0A>DV<44>CW<43>WX<57>Y]<5D>Ye<59>Ye<59>Xf<58>gc<02>d<02>e<02>)-<2D><1C><1C>d<EFBFBD>l<EFBFBD>l<EFBFBD>3<EFBFBD>t<EFBFBD>}<7D>}<7D>CU<43>6U<36>W[<5B>Wg<57>Wg<57>im<69>i{<7B>i{<7B>~B<02>~O<02>~O<02>QU<02>Q^<02>Q^<02>*_<02>&<26><04> <0A>w<EFBFBD><14>&<26>&<26>'<27>1<>&<26> <20>j<EFBFBD>j<EFBFBD><14>)9<>)9<>:<3A>V<01>F<EFBFBD><1D>(<28>(<28><1E>8<>R<EFBFBD>W<EFBFBD>W<EFBFBD>]<5D>]<5D>2<EFBFBD>7<EFBFBD>7<EFBFBD><<3C><<3C>X\<5C>Xh<58>Xh<58>jp<6A>Kq<4B>=r<><1A> <09> <09>G<EFBFBD>B<EFBFBD>G<EFBFBD>G<EFBFBD>L<EFBFBD>L<EFBFBD><14>9I<39>9I<39>6<EFBFBD>,R<>+S<>"T<>U<>V<01><17> <0B> <0B>Q<>S<><14><04>1<>1<>!<21>3<>3<><1A>K<EFBFBD>K<EFBFBD>"V<>X<><15>a0 <16>f]a<01>\n<>\n<>\{<7B>\{<7B>}A<02>}Q<02>}Q<02>]R<02>Y<><04> <0C>d<EFBFBD>*<2A>D<EFBFBD>,B<>D<EFBFBD>DY<44>'+<2B>':<3A>':<3A><04>$<24>!<21>$<24>"6<>"6<>7<><04><1B><13>|<7C>|<7C>T<EFBFBD>1<>1<>4<EFBFBD>3I<33>3I<33>4<EFBFBD>K`<60>K`<60>`<60>`<60><>+n<01><>%^s<00>3T<08>T<08> T<06>Tr*c<00><><00>|jjd<01>tjj |j
d|j <00><00><02>|_|j|jc|_
|_ |jj|j|j|j|j |j|j<00>\|_|_ d|_y)zK
- correct the testbench by using the RTL analysis results
<20>correct<63>correct_TN)r>rgrhrirjrr:rr r rSrTr*r<>r r6rr;rGs rArRzTaskTBcheck.correct_TB<54>s<><00><00>
<0A><0E><0E><1D><1D>i<EFBFBD>(<28><1D>7<EFBFBD>7<EFBFBD><<3C><<3C><04> <0A> <0A><18>$<24>-<2D>-<2D><1F>7Q<37>R<><04><18>@D<><0E><0E>PT<50>P_<50>P_<50>=<3D><04>!<21>4<EFBFBD>#=<3D>*.<2E>.<2E>.<2E>*@<40>*@<40><14>AQ<41>AQ<41>SW<53>Sg<53>Sg<53>im<69>iw<69>iw<69>y}<7D>zI<02>zI<02>KO<02>KZ<02>KZ<02>\`<02>\l<02>\l<02>+m<02>'<27><04><0E><04><0F><1D><04>rCr,c<00>F<00>|jjd<01>tjj |j
d<02>|_|jj|j|j|j|j|j <00><03>|_ y)zp
- improve the specification of the task according to the discrimination and correction results
<20>improve<76> improve_Desc)rN)r>rgrhrirjrrr,r<>r6r7r r r rGs rArUzTaskTBcheck.improve_SPEC s<><00><00>
<0A><0E><0E><1D><1D>i<EFBFBD>(<28><1D>7<EFBFBD>7<EFBFBD><<3C><<3C><04> <0A> <0A>~<7E>F<><04><18><1F>=<3D>=<3D>0<>0<><14>1E<31>1E<31>t<EFBFBD>G]<5D>G]<5D>_c<5F>_m<5F>_m<5F>os<6F>o~<7E>o~<7E>MQ<02>M]<02>M]<02>0<>^<02><04>rC<00> driver_code<64>DUT_code<64> checker_code<64> rtl_index<65>save_enc <00><><00>tj|d<01><02>tjj|d<03>}tjj|d<04>}tjj|d<05>}t |d<06>5} | j |<01>ddd<07>t |d<06>5} | j |<02>ddd<07>t j|d<01><08>}
|
d sd
gSt |d<06>5} | j |<03>ddd<07>tj|d<01> <0B>} | d sd
gS| d d } | jd<0E>} | jd<0F>}| |d zk(rgS| |d z| jdd<11>jd<12>}|D<00><10>cgc];}tdj|D<00>cgc]}|j<00>s<01>|<11><02>c}<11><00><00><02>=}}}tt!t|<0F><00>}|stj"d|<00><00><02>tt%|<0F><00>S#1swY<00><01>~xYw#1swY<00><01>exYw#1swY<00><01>-xYwcc}wcc}}w)a<>
- modified from autoline.py TBEval.run_testbench
- it has two mode: pychecker mode or verilog testbench mode
-input:
- dir: the dir to save the TB, DUT and pychecker code
- driver_code: str; the testbench code
- DUT_code: str; the DUT code
- checker_code: str; the pychecker code
- output:
- a list of failed scenarios (if rtl has syntax error, return [-1])
T<><01>exist_okzdriver.vz
checker.pyzDUT.v<>wN)<01>silentrr^)<02>pypathr<68>rJ<00>outrM<00>[<5B>'<27>rarf)rh<00>makedirsrirj<00>open<65>write<74>iv<69>iverilog_call_and_save<76>py<70>python_call_and_save<76>rfind<6E>replace<63>split<69>int<6E>isdigit<69>list<73>maprv<00>set)<12>dirr<72>r<>r<>r<>r<><00> v_driver_path<74>py_checker_path<74>dut_path<74>f<> iv_run_info<66> py_run_info<66>python_info_out<75>last_bracket_end<6E>last_bracket_start<72>failed_scenarios<6F>scenario<69>chars rArlzTaskTBcheck.run_testbenchs<00><00> <0B> <0B> <0B>C<EFBFBD>$<24>'<27><1A><07><07> <0C> <0C>S<EFBFBD>*<2A>5<> <0A><1C>'<27>'<27>,<2C>,<2C>s<EFBFBD>L<EFBFBD>9<><0F><15>7<EFBFBD>7<EFBFBD><<3C><<3C><03>W<EFBFBD>-<2D><08> <11>-<2D><13> %<25> !<21><11> <0A>G<EFBFBD>G<EFBFBD>K<EFBFBD> <20> !<21> <11>(<28>C<EFBFBD> <20> <1E>A<EFBFBD> <0A>G<EFBFBD>G<EFBFBD>H<EFBFBD> <1D> <1E><18>/<2F>/<2F><03>D<EFBFBD>A<> <0B><1A>1<EFBFBD>~<7E><17>4<EFBFBD>K<EFBFBD> <11>/<2F>3<EFBFBD> '<27> "<22>1<EFBFBD> <0A>G<EFBFBD>G<EFBFBD>L<EFBFBD> !<21> "<22><18>-<2D>-<2D>_<EFBFBD>T<EFBFBD>R<> <0B><1A>1<EFBFBD>~<7E><17>4<EFBFBD>K<EFBFBD>%<25>a<EFBFBD>.<2E><15>/<2F><0F>+<2B>0<>0<><13>5<><18>,<2C>2<>2<>3<EFBFBD>7<><1A> <1B>1<>!<21>3<> 3<><15>I<EFBFBD>*<2A>+=<3D>a<EFBFBD>+?<3F>@P<>Q<>Y<>Y<>Z]<5D>_a<5F>b<>h<>h<>il<69>m<><18>hx<68>y<>\d<>C<EFBFBD><02><07><07>(<28>(U<>$<24>d<EFBFBD>l<EFBFBD>l<EFBFBD>n<EFBFBD><14>(U<> V<>W<>y<><18>y<><1F><03>C<EFBFBD>)9<> :<3A>;<3B><18><16> <0E>I<EFBFBD>I<EFBFBD><07><03>u<EFBFBD>o<EFBFBD> &<26><13>C<EFBFBD>(<28>)<29>*<2A>*<2A>C !<21> !<21><> <1E> <1E><> "<22> "<22><>&)V<01><>ysB<00>H<03>*H<03>/H,<03>H><06>!H9<14>7H9<14>; H><06>H<07>H)<07>,H6<07>9H>c<00><><00>g|_tjd<01>|j|j|j
|j |j|j<00>\|_}|xj|z c_tjj|jd<02>}tj|jd<03><04>tj|j |jd<05>g|<02>y)z<>
- generate the RTL list using LLM, will empty the old rtl list
- attr needed: description, module_header, rtl_num, llm_model
- attr changed: rtl_list
z@rtl list not found, generating naive rtls for testbench checkingz rtl_list.jsonTr<54>)r<00>
llmgen_RTLN)r r<rPrrrr r
rr-rhrirjrr<><00>ls<6C>save_json_linesr)r?r<><00> save_paths rAr/zTaskTBcheck.rtl_list_genLs<><00><00> <1B><04> <0A><0E> <0B> <0B>V<>X<>!%<25><1C><1C>d<EFBFBD>l<EFBFBD>l<EFBFBD>D<EFBFBD><L<><L<>d<EFBFBD>N`<60>N`<60>bf<62>bs<62>bs<62>uy<75>vC<02>vC<02>"D<02><1E><04> <0A>w<EFBFBD> <0C><1E><1E>'<27>)<29><1E><16>G<EFBFBD>G<EFBFBD>L<EFBFBD>L<EFBFBD><14><1D><1D><0F>@<40> <09>
<EFBFBD> <0B> <0B>D<EFBFBD>M<EFBFBD>M<EFBFBD>D<EFBFBD>1<>
<EFBFBD><1A><1A><04> <0C> <0C>D<EFBFBD>M<EFBFBD>M<EFBFBD>R<>S<>U^<5E>_rC<00>num<75>header<65>llm_modec<00><00>d}d}||z }|dz }||z }|dz }t|<00>D]J}tj||<03>d}tj|d<05>d} |j | <09>|dz }<05>Lt j d|z<00>||fS)a<>
- input:
- num (int): the number of RTLs to generate
- description (str): the description of the rtl problem
- header (str): the header of the module
- llm (str): the llm model to use (official model name)
- rtl_list (list) [optional]: the newly generated RTLs will be appended to this list, can be empty
- output:
- rtl_list (list): the list of the newly generated RTLs (and the old ones, if have)
rz<>Your task is to write a verilog RTL design according to the design specification. The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the desired module. here is the problem description:
z+
Here is the header of the desired module:
zr
Please only return the module code (header should be included) in verilog, please do not include any other words.<2E>verilogrJz%d naive rtls generated)rQ<00>llm<6C>llm_call<6C> extract_codergr<rP)
r<EFBFBD>r r<>r<>r <00> rtl_gen_num<75>promptry<00>answer<65> module_codes
rArrzTaskTBcheck.gen_rtl[s<><00><00><18> <0B>P<04><06><0E>+<2B><1D><06><0E>A<>A<><06><0E>&<26><18><06><0E>H<02> H<02><06><16>s<EFBFBD><1A> <1D>A<EFBFBD><18>\<5C>\<5C>&<26>(<28>3<>A<EFBFBD>6<>F<EFBFBD><1D>*<2A>*<2A>6<EFBFBD>9<EFBFBD>=<3D>a<EFBFBD>@<40>K<EFBFBD> <14>O<EFBFBD>O<EFBFBD>K<EFBFBD> (<28> <17>1<EFBFBD> <1C>K<EFBFBD> <1D> <0F> <0B> <0B>-<2D>{<7B>;<3B><<3C><17><1B>$<24>$rCr<>r_r`c <00><><00>t|<00>}|<01>|nd}ttd<02>|<00><00>}|dvrd}|ttd<04>t |<03><00><00>k(rd}t||<04>}t |<03>D<00>cgc]}dg|z<00><02>
}}t |<00>D]'\} }
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- input: [failed_scenarios:list[int]] (for example: [[1,2,3], [2,3,4], [1,3,4], [-1]]), if one failed scenario list is [-1], it means the rtl has syntax error, should be skipped
- output (np.array): a onehot array (for example: [[0,0,0,1], [1,0,0,0], [0,1,0,0], [-1,-1,-1,-1]]) (1 denots pass, 0 denotes fail, -1 means syntax error)
rJc<00>&<00>|gk7r t|<00>SdS)Nr)<01>max<61><01>xs rA<00><lambda>z>TaskTBcheck.failed_scenarios_to_onehot_array.<locals>.<lambda><3E>s<00><00>!<21>r<EFBFBD>'<27><03>A<EFBFBD><06><00>q<EFBFBD>rC)r^rc<00><00>gS<00>N<>r<>s rAr<>z>TaskTBcheck.failed_scenarios_to_onehot_array.<locals>.<lambda><3E>s<00><00>"<22>rCr^r)r0r<>r<>r<>rQrkrn<00>array) r<>r_r`<00>listlen<65> max_idx_given<65> max_idx_cal<61>max_idx<64>_<>grid_mapr|<00> failed_scens<6E>scen_idxs rArmz,TaskTBcheck.failed_scenarios_to_onehot_arrayxs<><00><00><16>&<26>'<27><07>(4<>(@<40> <0C>a<EFBFBD> <0A><19>#<23>@<40>BR<42>S<>T<> <0B> <16>'<27> !<21><1C>K<EFBFBD> <1B>t<EFBFBD>C<EFBFBD> <0C>e<EFBFBD>G<EFBFBD>n<EFBFBD>$E<>F<> F<><1B>K<EFBFBD><15>k<EFBFBD>=<3D>1<><07>*/<2F>w<EFBFBD><1E>8<>A<EFBFBD>Q<EFBFBD>C<EFBFBD><07>K<EFBFBD>8<><08>8<>%.<2E>/?<3F>%@<40> 2<> !<21>G<EFBFBD>\<5C><1B><02>t<EFBFBD>#<23>%'<27>D<EFBFBD><17>L<EFBFBD><08><17>!<21><18>(<28> 2<><08>01<30><08><17>!<21>(<28>1<EFBFBD>*<2A>-<2D> 2<>  2<> <12>x<EFBFBD>x<EFBFBD><08>!<21>!<21><>9s<00>+ Cr1<00> saving_pathc <00><00>t|<00>dk(rtjdgg<01>}tjtj|dk(tj|dk(|dk(<00><00>|d<02>}t j d<04>}t j d<05>}t j d<06>}|||d<07>}tj|D<00><07>cgc]}|D<00>cgc]}||<00><02> c}<08><02>c}}<07>} |j<00>D] \}}
|
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- draw the 2D failed scenario array. The element in the array can only be 0, 1, -1. We use red for 0, green for 1, and gray for -1.
- if the scenario is empty, will return a gray color block.
rr^rJ<00>salmon<6F>grey<65>mediumseagreen)rrJr^z RTL indexzScenario indexr<78>z)] - Matrix of RTL-TB Scenario CorrectnessN)r0rnr<><00>where<72>
logical_or<EFBFBD>mcolors<72>to_rgb<67>items<6D>plt<6C>imshow<6F>ylabel<65>xlabel<65>arange<67>shape<70>xticks<6B>yticks<6B>title<6C>savefig<69>close) r1rr<>r<>r<>r<><00> color_mapping<6E>row<6F>value<75> rgb_image<67>color<6F>current_xticks<6B>current_ytickss rArpz TaskTBcheck.draw_scenario_matrix<69>s<><00><00> <0F><EFBFBD> <1F>1<EFBFBD> $<24> <20>h<EFBFBD>h<EFBFBD><12><04>v<EFBFBD>.<2E>O<EFBFBD><1C>(<28>(<28>2<EFBFBD>=<3D>=<3D><1F>A<EFBFBD>1E<31>r<EFBFBD>}<7D>}<7D>Ud<55>hi<68>Ui<55>kz<6B>A<02>lA<02>HB<02>$C<02>ET<02>VX<02>Y<02><0F><18><1E><1E><08>)<29><06><16>~<7E>~<7E>f<EFBFBD>%<25><04> <20><1E><1E>(8<>9<><0E><15><1D><14>
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<EFBFBD>><3E>><3E>A<EFBFBD>#5<>6<> <0B> <09> <09>A<EFBFBD>g<EFBFBD>Y<EFBFBD>G<>H<>I<> <0B> <0B> <0B>K<EFBFBD> <20> <0B> <09> <09> <0B><>F<01><>as<00> H
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- will modify the description of the task according to the descrimination and correction results
z&the description of the task is updated)r<rPr rGs rA<00>update_descriptionzTaskTBcheck.update_description<6F>s<00><00> <0F> <0B> <0B><<3C>=<3D><13><1F><1F>rCr<>c<00><00>||_yr<>rE)r?r<>s rAr.zTaskTBcheck.set_rtl_num<75>s <00><00><1D><04> rCc<00>"<00>|j<00>Sr<>)rX)r?<00>args<67>kwdss rA<00>__call__zTaskTBcheck.__call__<5F>s<00><00><13>x<EFBFBD>x<EFBFBD>z<EFBFBD>rC) NN<4E>N<>T<>col_full_wrongrNr<4E>TF)F)T)Nr<4E>)<1B>__name__<5F>
__module__<EFBFBD> __qualname__<5F>__doc__<5F>strr<72>r<><00>boolrB<00>propertyrrrXrNrRrU<00> staticmethodrlr/rrrmrn<00>ndarrayrpr<>r.r<>r<>rCrArrsv<00><00><08> N<1C><03>N<1C>S<EFBFBD>N<1C>c<EFBFBD>N<1C>QT<51>N<1C>`c<>N<1C>ps<70>tx<74>px<70>N<1C>IM<02>NQ<02>IR<02>N<1C>ad<02>N<1C>HK<03>N<1C>]a<03>N<1C>{~<03>N<1C>`c<04>N<1C>z}<04>N<1C>Y\<05>N<1C>os<05>N<1C>GK<06>N<1C>dh<06>N<1C>`<0E><1D><0E><1D><15>Y<EFBFBD><1F>A <20> <20>A <20>F<15>_<EFBFBD>%<25>@a<01>4<EFBFBD>@a<01>&<26>@a<01>D<15>[<5B>!<21><1E>"<22><1E>$<15>Z<EFBFBD> <20>^<02>!<21>^<02><12>3+<2B>s<EFBFBD>3+<2B>S<EFBFBD>3+<2B>s<EFBFBD>3+<2B>VY<56>3+<2B>cg<63>3+<2B><12>3+<2B>j `<01>D<EFBFBD><13>I<EFBFBD> `<01><12>RT<52>%<25>C<EFBFBD>%<25>S<EFBFBD>%<25><13>%<25>s<EFBFBD>%<25>T<EFBFBD>%<25><12>%<25>8<12>"<22>$<24>t<EFBFBD>*<2A>"<22>SV<53>W[<5B>S[<5B>"<22>il<69>"<22><12>"<22>><12><14>R<EFBFBD>Z<EFBFBD>Z<EFBFBD><14><13><14>RU<52><14><12><14>B <20>#<23> <20><1E><03><1E>rCrc <00>d<00>eZdZdZdeddfd<05>Zdejdee e
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this class is used to discriminate the testbench according to the failing matrix
<20>moderNc<00><><00>||_|jxdk(ryxdk(ryxdk(ryxdk(ryxdk(ryxdk(ryxdk(ryxdk(ryxd k(ryxd
k(ryd k(ry tjd <0C>y) Nr<4E><00> col_80_wrong<6E> col_90_wrong<6E> col_70_wrong<6E> col_60_wrong<6E> col_50_wrong<6E> col_40_wrong<6E>col_70_wrong_row_25_correct<63>col_50_wrong_row_25_correct<63>col_70_wrong_row_1_correct<63>col_70_wrong_row_10_correctz'class discriminator - mode not found!!!)rr<<00>critical)r?rs rArBzTB_discriminator.__init__<5F>sd<00><00><18><04> <09><12>i<EFBFBD>i<EFBFBD>!<21><15><1F><14><1F><14><1F><14><1F><14><1F><14><1F><14>.<2E><14>.<2E><14>-<2D><14>.<2E><14><12><16><0F><0F> I<>JrC<00> failed_matrixc<00>:<00>tj|dk(<00>rdgggfS|tj|dk(d<03><04>}|jxdk(<00>r,tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtj
|dk(d<06><04>tj
|dk(d<06><04>z<00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>rHtjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>rHtjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>rHtjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>r<>tjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tjtj|dk(d<03><04><00>dt |<01>zk\rd}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>r<>tjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tjtj|dk(d<03><04><00>dt |<01>zk\rd}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>r<>tjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tjtj|dk(d<03><04><00>dt |<01>zk\rd}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>rHtjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxdk(<00>rHtjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSxd k(<00>r<>tjtj|dk(d<06><04>dt |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>dt |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tjtj|dk(d<03><04><00>dt |<01>zk\rd}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fSd!k(<00>rGtjtj|dk(d<06><04>d"t |<01>zk\<00>ddz}tjtjtj|ddg<02>d<06><04><00>ddz}tjtjtj|dk(d<06><04>d"t |<01>zktj
|dk(d<06><04><00><00>ddz}t |<02>dk(}tj|ddd |rd
nd <0B>d |<02>d t |<03><00>dt |d<00><00><00><08>||||fS tjd#<23>td#<23><00>)$a<>
- input: the failed matrix of the testbench in onehot form
- output:
- the idexes in the scen list are starting from 1
- bool: whether the testbench is correct
- list[int]: the list of the wrong scenarios
- list[int]: the list of the correct scenarios
- list[int]: the list of the scenarios that discriminator are not sure
- the -1 row will not be considered here. See function 'failed_scenarios_to_onehot_array'
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<EFBFBD>Fe<EFBFBD>ry<EFBFBD>fn<EFBFBD>@H<02>fI<02>I\<02>]l<02>\m<02>mD<03>EH<03>IZ<03>E[<03>D\<03>\]<03>^a<03>bo<03>pq<03>br<03>^s<03>]t<03>Eu<03>v<03><1E><0F>1B<31>DT<44>T<>T<><12><16><0F><0F> F<>G<>"<22>#I<>J<>JrC) r<>r<>rrrrBrnr<00>tuplerr<>r<>rwr<>rCrAr'r'<00>sY<00><00><08>'K<01>C<EFBFBD>'K<01>D<EFBFBD>'K<01>RtK<01><12><1A><1A>tK<01>e<EFBFBD>D<EFBFBD>$<24>s<EFBFBD>)<29>T<EFBFBD>RU<52>Y<EFBFBD>X\<5C>]`<60>Xa<58><a<>6b<36>tKrCr'aeYour task is to correct the testbench according to the failing scenarios. the information we have is the failed/passed scenarios of the testbench, the problem description and the testbench code.
the testbench code is consisted of both verilog and python code. The verilog code aims to generate test stimulus (under test scenarios) and drive the DUT to generate the output signal; the python code aims to check if the output vector from the DUT is correct.
ATTENTION: The python code contains error, and your target is to find it and tell me how to correct it (you don't need to give me the code in this stage).
a 
Hints - explaination of the given python code:
the python class "GoldenDUT": This python class can represent the golden DUT (the ideal one). In "GoldenDUT", following methods are defined:
- 1. a method "def __init__(self)": Set the inner states/values of the golden DUT. These values have suffix "_reg". The initial value of these inner values is "x", but later will be digits. The "__init__" method has no input parameters except "self".
- 2. a method "def load(self, signal_vector)": This method is to load the important input signals and the inner values of "GoldenDUT" shall change according to the input signals. There is no clock signal in the input signal vector, every time the "load" method is called, it means a new clock cycle. The initial values "x" should be changed according to the input signals. This method has no return value.
- 3. a method "def check(self, signal_vector)": This method is to determine the expected output values and compare them with output signals from DUT. It should return True or False only.
a<EFBFBD>
Hints - explaination of the given python code:
The given python code contains one class "GoldenDUT". this python class can represent the golden DUT (the ideal one). By calling the inner method "check", the signal vector from DUT will be checked. The details of the golden DUT are as follows:
- a. a method "def __init__(self)". Set the inner states/values of the golden DUT. The "__init__" method has no input parameters except "self".
- b. a method "def load(self, signal_vector)". This method is to load the important input signals and get the expected output signals. it should return the expected output values. It can call other methods to help computing the expected output. It will be called by other inner methods later.
- c. a method "def check(self, signal_vector)". This method is to call "load" to get the expected output values, and compare them with output signals from DUT. It should return True or False only. It can call other methods to help checking.
- d. other methods, they can be called by "__init__", "load" or "check".
- e. the input of "load" and "check" is the signal vector. The signal vector is a dictionary, the key is the signal name, the value is the signal value.
a<EFBFBD>
please correct the python code according to the following rules:
PYTHON code rule: please do not change the original high level structure of the python code. i.e., if python code only contains one class and several functions such as init, load, check and more, only modify the implementation of the function, but do not change the name or delete the functions/class methods. you can add new class methods or functions if needed. you can use python libraries such as numpy or math.
a<EFBFBD>
i.e., your python code format in response should still be like:
class <class_name>:
def __init__(self):
...(omitted)
def load(self, ...):
...
def check(self, ...):
...
def <other_functions>(self, ...):
...
ATTENTION: please give me the corrected python code according to our previous conversation and the hints above. please give me the corrected full python code (not the part but the whole python code like I give you in our previous conversation).
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z }||z }|d z }||z }|d z }||z }|d z }|dz }|dt|<02><00>d<10>z }|dz }|dz }|dz }tjd<14>tj||<04>d} t|ztz}
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d<17>g} tj| |<04>\} } tj| d<19>d}|j|d<1A><03>}|<06>ktj | dt"j$j'|d<1C><00>tj(|t"j$j'|d<1D><00>|<05>4tj(|t"j$j'|d<1E><00>tjd<1F>||fStj*d <20>t-d <20><00> tj*d!<21>t-d!<21><00>)"NrT)<01>beforer%z!Here is the problem description:
z
Here is the testbench code:
<EFBFBD>.ATTENTION: the following scenarios are wrong: <20>
z!the circuit type of this task is z<>Here is the verilog code. it contains the meaning of each scenario. you can combine the wong scenario info above and the following code to better understand the reason of failing:
z<EFBFBD>
Here is the python code, it contains error, please combine it with the wrong scenario info and the verilog code to understand:
zL
Here is some hints for your better understanding of the python codes above:z*
please reply me with the following steps:z{
1. please analyze the reason of the failed scenarios. If possible, please find the in common between the failed scenarios.zZ
2. please analyze which part of the python code is related to the failed test scenarios (z).z<>
3. please tell me how to correct the wrong part (in natural language, do not give me the complete code implementation. please explain it in English.)z!
here is an example of the reply:z<>
1. the failed scenarios are all related to the same signal x
2. the mid part of the function_X is related to the failed scenarios
3. the correct logic of signal x should be y.znaive corrector mode beginsr<00>user<65><02>role<6C>content<6E> assistant<6E>pythonF<6E>messages<65>conversation.txtzTB.vzTB.pyz7naive corrector mode ends; conversation and codes savedz$TB_corrector - pychecker not enabledz TB_corrector - mode not found!!!)rr <00> _py_focusr<00>HINT_CMB<4D>HINT_SEQ<45> COR_PROMPT_1rr<rPr<>r<><00>COR_PROMPT_2_PART1<54>COR_PROMPT_2_PART2r<32>r<><00>save_messages_to_txtrhrirj<00> save_coderr!)r?r r<>r r,r r<00> py_code_hintr<74>r<><00>prompt_2<5F>message<67>answer_2<5F> more_infos rAr<>zTB_corrector.correct<63>s<><00><00><12>i<EFBFBD>i<EFBFBD><18><17>$<24>$<24>!%<25><1E><1E>
<EFBFBD>4<EFBFBD><1E>!H<>J<EFBFBD>/3<>/@<40>/@<40>O<EFBFBD>/S<>8<EFBFBD>Ya<59>L<EFBFBD>)<29>F<EFBFBD><1A>B<>B<>F<EFBFBD><1A>k<EFBFBD>)<29>F<EFBFBD><1A>?<3F>?<3F>F<EFBFBD><1A>N<>QT<51>Ue<55>Qf<51>f<>im<69>m<>m<>F<EFBFBD><1A> A<>$<24>BS<42>BS<42>AT<41>TV<54>W<>W<>F<EFBFBD><1A>V<03>V<03>F<EFBFBD><1A>i<EFBFBD>'<27>F<EFBFBD><1A>c<02>c<02>F<EFBFBD><1A>j<EFBFBD>(<28>F<EFBFBD><1A>m<>m<>F<EFBFBD><1A>l<EFBFBD>*<2A>F<EFBFBD><1A>K<>K<>F<EFBFBD><1A>]<02>]<02>F<EFBFBD><1A> {<7B>|<>AQ<02>}R<02>|S<02>SU<02>V<02>V<02>F<EFBFBD><1A>x<02>x<02>F<EFBFBD><1A>B<>B<>F<EFBFBD><1A>T<03>T<03>F<EFBFBD><1A>K<EFBFBD>K<EFBFBD> =<3D>><3E> <20>\<5C>\<5C>&<26>)<29><<3C>Q<EFBFBD>?<3F>F<EFBFBD>1<>L<EFBFBD>@<40>CU<43>U<>H<EFBFBD>(.<2E>6<EFBFBD>B<>[<5B>ek<65>Dl<44>w}<7D>KS<02>oT<02>U<02>G<EFBFBD>*-<2D>,<2C>,<2C>w<EFBFBD> <09>*J<>'<27>H<EFBFBD>i<EFBFBD>
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<EFBFBD>5<EFBFBD><1E>!I<>J<EFBFBD>"<22>.<2E><1A>/<2F>/<2F> <09>*<2A>0E<30>r<EFBFBD>w<EFBFBD>w<EFBFBD>|<7C>|<7C>T_<54>as<61>Gt<47>u<><1A> <0C> <0C>Y<EFBFBD><02><07><07> <0C> <0C>[<5B>&<26>0Q<30>R<>!<21>-<2D><1A> <0C> <0C>Z<EFBFBD><12><17><17><1C><1C>k<EFBFBD>7<EFBFBD>1S<31>T<><1A>K<EFBFBD>K<EFBFBD> Y<>Z<>!<21>*<2A>,<2C>,<2C><1B>O<EFBFBD>O<EFBFBD>$J<>K<>&<26>'M<>N<>N<><12><16><0F><0F> B<>C<>"<22>#E<>F<>FrC<00>coder.c<00><><00>d}d}|rI||vr|n|}||vr |}d|_|S|j|<05>d}||j|<05>dz|_|S||jzS)z<>
- imigrated from TB2_syncheck.py
- code: the code under debug / after debug
- before: True, if before debug, will split the code; False, if after debug, will restore the code
zQdef check_dut(vectors_in):
golden_dut = GoldenDUT()
failed_scenarios = []z
def SignalTxt_to_dictlistr<74>rrJ)<02>_py_code_nofocusr<73>)r?rFr.<00> KEY_WORDs_1<5F> KEY_WORDs_2<5F> key_words<64> py_code_focuss rAr9zTB_corrector._py_focus<75>s<><00><00> l<01> <0B>3<> <0B> <11>'2<>d<EFBFBD>':<3A> <0B> <0B>I<EFBFBD><18><04>$<24> $<24> <0A>(*<2A><04>%<25>!<21> <20>!%<25>
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<EFBFBD>9<EFBFBD> 5<>a<EFBFBD> 8<> <0A>(1<>D<EFBFBD>J<EFBFBD>J<EFBFBD>y<EFBFBD>4I<34>!<21>4L<34>(L<><04>%<25> <20> <20><17>$<24>/<2F>/<2F>/<2F> /rC<00>r<><00>NN) r<>r<>rrrrBr"r<>r9r<>rCrAr)r)<00>s<><00><00> J<01>C<EFBFBD> J<01>d<EFBFBD> J<01><13> J<01>D<EFBFBD> J<01>0G<01>s<EFBFBD>0G<01>c<EFBFBD>0G<01>^a<>bf<62>^f<>0G<01>y|<7C>0G<01>GL<02>MP<02>RU<02>MU<02>GV<02>0G<01>d0<>S<EFBFBD>0<><14>0rCr)aYour task is to improve the quality of an RTL problem description using the following given information. Our final target is using the description to generate a testbench for the RTL design. Currently we already have the testbench but it is not perfect correct. Now in this stage the target is to generate a better description.
The information we have the is original RTL description, the testbench code. The testbench code includes the verilog code for test scenario generation, and the python code for checking the output vector.The verilog code aims to generate test stimulus (under test scenarios) and drive the DUT to generate the output signal; the python code aims to check if the output vector from the DUT is correct.
Attention: the testbench we provide is not the perfect one, and it contains error. However, we already know the test scenarios where the testbench works correctly and the scenarios where the testbench has problem. We will provide you the scenarios index later.
Here, firstly, is the problem description to be imporved:
z***description begins***z***description ends***a<>
please reply me with the following steps:
1. please analyze which part of the testbench (especially the python checker code) is correct and can be used to improve the description.
2. please analyze how can we improve the descriptin. for example, which part of the technical details can be more detailed, which part can be more clear, which part can be more concise.
3. please provide the improved complete description. We will directly use it in the later stages.
the format of description should be like:
z4
... (the improved description, should be complete)
r0a<>
ATTENTION: please know that the provided testbench is not perfect and may contains many errors. Thus, your modification on the description should not change the function of the original description. When there are conflicts between the testbench and the description, always believe the description is correct. Do not delete the information in the description, but you can rewrite it in a better way. You can also add more details to it. But NEVER mention any scenario index because the scenarios will not be the same at the next stage.
when you answer the last question (provide the improved complete description), the descriptino should start with "z" and end with "z?". Only in this way can we recognize the improved description.
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Y<00><>xYw#1swY<00>dxYw)Nrz&naive description improver mode beginsr<73>r0z
Here is the testbench codes:
r/zlATTENTION: the following scenarios are correct, you can rely on these scenarios to improve the description: zx
Here is the python code (python checker). please note that the python checker has correct function under the scenarios z , but wrong under the scenarios z:
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