TBgen_App/__pycache__/iverilog_call.cpython-312.pyc

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Description :   This file is related to iverilog calling. Some codes are modified from autosim.py v0.2 by Rain Bellinsky.
Author      :   Ruidi Qiu (r.qiu@tum.de)
Time        :   2023/12/9 23:22:51
LastEdited  :   2025/2/22 16:13:21
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    - dir: the name of the directory that contains all verilog files; can end with or without "/"
    - task_id: the name of the task, will be used as the name of the vvp file

    #### output:
    return a list of 5 elements:
    - [0] (pass or not):    bool, whether the simulation is successful
    - [1] (cmd1):           str, the iverilog compiling command
    - [2] (run1_info):      dict, the iverilog compiling result {"out": out_reg, "err": err_reg, "haserror": error_exist}
    - [3] (cmd2):           str, the vvp running command
    - [4] (run2_info):      dict, the vvp running result {"out": out_reg, "err": err_reg, "haserror": error_exist}
    - [5]/[-1] (error_msg): str, the error message if there is any error; This is for convenience, the error message is also included in [2] or [4]

    #### functionality:
    given the name of the directory that contains all verilog files, create a vvp file and run it.

    #### iverilog command explanation:
    - -o + file_path: output file name (.vvp's name)
    - -c + list_file_path: read file list from file
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