11 lines
132 B
Verilog
11 lines
132 B
Verilog
module top_module(
|
|
input clk,
|
|
input load,
|
|
input ena,
|
|
input [1:0] amount,
|
|
input [63:0] data,
|
|
output reg [63:0] q);
|
|
|
|
|
|
endmodule
|