38 lines
780 B
Verilog
38 lines
780 B
Verilog
module top_module (
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input clk,
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input [7:0] in,
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input reset,
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output [23:0] out_bytes,
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output done
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);
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parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
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reg [1:0] state;
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reg [1:0] next;
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wire in3 = in[3];
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always_comb begin
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case (state)
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BYTE1: next = in3 ? BYTE2 : BYTE1;
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BYTE2: next = BYTE3;
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BYTE3: next = DONE;
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DONE: next = in3 ? BYTE2 : BYTE1;
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endcase
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end
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always @(posedge clk) begin
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if (reset) state <= BYTE1;
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else state <= next;
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end
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assign done = (state==DONE);
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reg [23:0] out_bytes_r;
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always @(posedge clk)
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out_bytes_r <= {out_bytes_r[15:0], in};
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// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.
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assign out_bytes = done ? out_bytes_r : 'x;
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endmodule
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