396 lines
20 KiB
Plaintext
396 lines
20 KiB
Plaintext
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---------------custom config--------------
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run:
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mode: autoline
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save:
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en: True
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pub:
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prefix: MyProjectCleanI2C
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subdir: MyExperimentsClean
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gpt:
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model: qwen-max
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rtlgen_model: qwen-max
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autoline:
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result_path: results/myproject_clean_i2c
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 100.0
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probset:
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path: data/myproject/i2c_controller_clean.jsonl
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mutant_path: None
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more_info_paths: []
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only: ['i2c_controller']
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promptscript: pychecker
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timeout: 300
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save_compile: False
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debug:
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max: 3
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itermax: 10
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update_desc: False
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TBcheck:
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discrim_mode: col_70_wrong_row_25_correct
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------------------------------------------
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------config info (custom + default)------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: 20260424_002634
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custom_path: config/myproject_clean_i2c.yaml
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mode: autoline
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hostname: localhost
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pid: 2155
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pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0]
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save:
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en: True
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root: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/
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pub:
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prefix: MyProjectCleanI2C
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dir: saves/0420~0426/
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subdir: MyExperimentsClean/
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: qwen-max
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: qwen-max
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results/myproject_clean_i2c
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 100.0
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probset:
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path: data/myproject/i2c_controller_clean.jsonl
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['i2c_controller']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 3
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: pychecker
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_70_wrong_row_25_correct
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: False
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save_finalcodes: True
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error_interruption: False
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stage3:
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rtl_mode: auto
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max_inline_chars: 5000
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save_rtl_file: True
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multi_tb:
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enabled: False
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auto_threshold_lines: 500
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strategy: functional
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max_tb_count: 5
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parallel: False
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merge_coverage: True
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_initialized: True
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------------------------------------------
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--------------default config--------------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: None
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custom_path: None
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mode: qwen-max
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save:
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en: True
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root: None
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pub:
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prefix: None
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dir: saves/$weekrange$/
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subdir:
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: 4o
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: None
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results
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cga:
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enabled: True
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max_iter: 10
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target_coverage: 100.0
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probset:
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path: None
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['review2015_fancytimer', 'fsm_ps2data', 'bugs_case', 'review2015_fsmonehot', 'review2015_fsmseq', 'lemmings4', 'ece241_2013_q8']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 5
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: None
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_full_wrong
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: True
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save_finalcodes: True
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error_interruption: False
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stage3:
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rtl_mode: auto
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max_inline_chars: 5000
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save_rtl_file: True
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multi_tb:
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enabled: False
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auto_threshold_lines: 500
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strategy: functional
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max_tb_count: 5
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parallel: False
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merge_coverage: True
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------------------------------------------
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2026-04-24 00:26:34 | INFO | all configurations are loaded, starting the main process...
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2026-04-24 00:26:34 | INFO |
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2026-04-24 00:26:34 | INFO | ######################### task 1/1 [i2c_controller] #########################
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2026-04-24 00:29:01 | INFO | [i2c_controller] [TBgen] stage_0 ends (146.60s used)
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2026-04-24 00:30:17 | INFO | [i2c_controller] [TBgen] stage_1 ends (76.33s used)
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2026-04-24 00:31:34 | INFO | [i2c_controller] [TBgen] stage_2 ends (76.21s used)
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2026-04-24 00:35:36 | INFO | [i2c_controller] [TBgen] stage_3 ends (242.24s used)
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2026-04-24 00:37:35 | INFO | [i2c_controller] [TBgen] stage_4 ends (119.27s used)
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2026-04-24 00:37:35 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used)
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2026-04-24 00:41:05 | INFO | [i2c_controller] [TBgen] stage_4b ends (210.45s used)
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2026-04-24 00:42:59 | INFO | [i2c_controller] [TBgen] stage_5 ends (113.13s used)
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2026-04-24 00:42:59 | INFO | [i2c_controller]
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2026-04-24 00:42:59 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1)
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2026-04-24 00:45:58 | INFO | [i2c_controller] [TBsim] verilog iter - 1/3, total - 1/6: verilog DEBUG finished (179.47s used)
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2026-04-24 00:45:58 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Rebooting... (debug_iter = 2)
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2026-04-24 00:46:54 | INFO | [i2c_controller] [TBsim] stage_4 ends (55.40s used)
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2026-04-24 00:46:54 | INFO | [i2c_controller] [TBsim] stage_checklist ends (0.00s used)
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2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] stage_4b ends (123.45s used)
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2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] verilog iter - 2/3, total - 2/6: verilog REBOOT finished (178.86s used)
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2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 3)
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2026-04-24 00:51:50 | INFO | [i2c_controller] [TBsim] verilog iter - 3/3, total - 3/6: verilog DEBUG finished (173.07s used)
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2026-04-24 00:51:50 | INFO | [i2c_controller] [TBsim] iverilog compilation : failed! exceeded max debug iteration (3)
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2026-04-24 00:51:50 | ERROR | [i2c_controller] Error when running TBsim, iter: 1. Message: TBsim: iverilog failed, python simulation is not allowed. | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 00:51:50 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 00:52:59 | INFO | [i2c_controller] [TBgen] stage_0 ends (53.97s used)
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2026-04-24 00:53:30 | INFO | [i2c_controller] [TBgen] stage_1 ends (30.50s used)
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2026-04-24 00:53:55 | INFO | [i2c_controller] [TBgen] stage_2 ends (25.69s used)
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2026-04-24 00:54:52 | INFO | [i2c_controller] [TBgen] stage_3 ends (57.18s used)
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2026-04-24 00:59:34 | INFO | [i2c_controller] [TBgen] stage_4 ends (281.22s used)
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2026-04-24 02:19:14 | INFO | [i2c_controller] [TBgen] stage_checklist ends (4780.37s used)
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2026-04-24 02:21:44 | INFO | [i2c_controller] [TBgen] stage_4b ends (150.28s used)
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2026-04-24 02:23:14 | INFO | [i2c_controller] [TBgen] stage_5 ends (89.53s used)
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2026-04-24 02:23:14 | INFO | [i2c_controller]
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2026-04-24 02:23:14 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1)
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2026-04-24 03:42:27 | ERROR | [i2c_controller] Error when running TBsim, iter: 2. Message: list index out of range | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 03:42:27 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 03:44:01 | INFO | [i2c_controller] [TBgen] stage_0 ends (76.34s used)
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2026-04-24 03:44:38 | INFO | [i2c_controller] [TBgen] stage_1 ends (36.47s used)
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2026-04-24 03:45:10 | INFO | [i2c_controller] [TBgen] stage_2 ends (32.50s used)
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2026-04-24 03:47:09 | INFO | [i2c_controller] [TBgen] stage_3 ends (118.95s used)
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2026-04-24 03:54:04 | INFO | [i2c_controller] [TBgen] stage_4 ends (415.05s used)
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2026-04-24 03:54:04 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used)
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2026-04-24 04:08:10 | INFO | [i2c_controller] [TBgen] stage_4b ends (845.96s used)
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2026-04-24 04:09:32 | INFO | [i2c_controller] [TBgen] stage_5 ends (81.62s used)
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2026-04-24 04:09:32 | INFO | [i2c_controller]
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2026-04-24 04:09:32 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1)
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2026-04-24 04:13:43 | INFO | [i2c_controller] [TBsim] verilog iter - 1/3, total - 1/6: verilog DEBUG finished (250.84s used)
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2026-04-24 04:13:43 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Rebooting... (debug_iter = 2)
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2026-04-24 04:14:23 | INFO | [i2c_controller] [TBsim] stage_4 ends (40.11s used)
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2026-04-24 04:14:23 | INFO | [i2c_controller] [TBsim] stage_checklist ends (0.00s used)
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2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] stage_4b ends (129.94s used)
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2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] verilog iter - 2/3, total - 2/6: verilog REBOOT finished (170.06s used)
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2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 3)
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2026-04-24 04:19:08 | INFO | [i2c_controller] [TBsim] verilog iter - 3/3, total - 3/6: verilog DEBUG finished (155.35s used)
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2026-04-24 04:19:08 | INFO | [i2c_controller] [TBsim] iverilog compilation : failed! exceeded max debug iteration (3)
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2026-04-24 04:19:08 | ERROR | [i2c_controller] Error when running TBsim, iter: 3. Message: TBsim: iverilog failed, python simulation is not allowed. | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 04:19:08 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318
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2026-04-24 04:20:20 | INFO | [i2c_controller] [TBgen] stage_0 ends (56.59s used)
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2026-04-24 04:20:38 | INFO | [i2c_controller] [TBgen] stage_1 ends (17.86s used)
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2026-04-24 04:21:01 | INFO | [i2c_controller] [TBgen] stage_2 ends (23.04s used)
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2026-04-24 04:21:51 | INFO | [i2c_controller] [TBgen] stage_3 ends (49.92s used)
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2026-04-24 04:22:39 | INFO | [i2c_controller] [TBgen] stage_4 ends (48.02s used)
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2026-04-24 04:22:39 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used)
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2026-04-24 04:25:09 | INFO | [i2c_controller] [TBgen] stage_4b ends (150.12s used)
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBgen] stage_5 ends (61.25s used)
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2026-04-24 04:26:10 | INFO | [i2c_controller]
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] iverilog compilation : passed!
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] python simulation : passed!
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] TBsim finished : True!
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2026-04-24 04:26:10 | INFO | [i2c_controller]
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2026-04-24 04:26:10 | INFO | [i2c_controller] rtl list not found, generating naive rtls for testbench checking
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: swap_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-24 04:26:10 | INFO | [i2c_controller] 20 mutation-based RTLs generated (from reference RTL)
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Plan 2: Capturing Reference RTL outputs as ground truth...
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Capturing Reference RTL outputs as ground truth...
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Reference RTL check results: failed scenarios = [1, 2, 3, 3, 3, 3, 3, 3, 4, 5, 6, 7], passed scenarios = []
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Captured Reference RTL outputs for 7 scenarios
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Plan 2: Captured outputs for 7 scenarios
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2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination
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2026-04-24 04:26:12 | POSITIVE | [i2c_controller] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 7/7
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2026-04-24 04:26:12 | INFO | [i2c_controller] [TBcheck] Testbench passed the funccheck
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2026-04-24 04:26:12 | INFO | [i2c_controller] [TBcheck] self funccheck finished. Next Action: [pass]
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2026-04-24 04:26:12 | INFO | [i2c_controller]
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2026-04-24 04:26:12 | INFO | [i2c_controller] [i2c_controller] Starting Coverage-Guided Agent (CGA)...
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2026-04-24 04:26:12 | INFO | [i2c_controller] [i2c_controller] Running Semantic Analysis (Layer 0)...
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2026-04-24 04:26:12 | INFO | [i2c_controller] FSM detected: state (15 states)
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2026-04-24 04:26:12 | INFO | [i2c_controller] Total function points identified: 16
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2026-04-24 04:26:12 | INFO | [i2c_controller] Energy allocator initialized: 16 targets
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2026-04-24 04:26:12 | INFO | [i2c_controller] Diversity injector initialized with history file: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/test_history.json
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2026-04-24 04:26:12 | INFO | [i2c_controller] Quality evaluator initialized
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2026-04-24 04:26:12 | INFO | [i2c_controller] --- CGA Iter 0 (Baseline) ---
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2026-04-24 04:26:12 | ERROR | [i2c_controller] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1362
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2026-04-24 04:26:12 | INFO | [i2c_controller] Baseline Coverage: 0.00%
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2026-04-24 04:26:12 | INFO | [i2c_controller] --- CGA Iter 1 / 15 ---
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2026-04-24 04:26:12 | INFO | [i2c_controller] Target: FSM_state
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2026-04-24 04:26:12 | INFO | [i2c_controller] CGA Finished. Final Coverage: 0.00%
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2026-04-24 04:26:12 | INFO | [i2c_controller] No unreachable branches found in DUT.
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2026-04-24 04:26:12 | INFO | [i2c_controller] Energy report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/energy_report.txt
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2026-04-24 04:26:12 | INFO | [i2c_controller] Diversity report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/diversity_report.txt
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2026-04-24 04:26:12 | INFO | [i2c_controller] Quality evaluation report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/quality_evaluation_report.txt
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2026-04-24 04:26:12 | INFO | [i2c_controller] Semantic Coverage: 0.00%
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2026-04-24 04:26:12 | INFO | [i2c_controller] Saved optimized TB to: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/final_TB.v
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2026-04-24 04:26:12 | INFO | [i2c_controller] [TBeval] Eval 1: Golden RTL checking begins
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2026-04-24 04:26:13 | FAILED | [i2c_controller] [TBeval] Eval 1: Golden RTL checking failed!
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2026-04-24 04:26:13 | INFO | [i2c_controller] [TBeval] [i2c_controller] Eval 2/2b is skipped because Eval 1 failed
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2026-04-24 04:26:13 | INFO | [i2c_controller]
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2026-04-24 04:26:13 | INFO |
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########## Analyze of Chatbench_RunInfo ##########
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#### pass numbers:
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Eval2 : 0
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Eval1 : 0
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Eval0 : 1
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total : 1 (Failed: 0)
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passed TB by autoline reboot action (from TB3_check): 0
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passed TB by functional corrector: 0
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#### CGA Coverage Info:
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Average Coverage : 0.00%
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(No coverage data found in JSON)
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#### tokens and cost:
|
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average prompt tokens: 85605
|
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average completion tokens: 92365
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total cost: 7.2540
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average cost: 7.2540
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#### time:
|
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average time: 14378.22s
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#### debug info table:
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FUNCTIONAL debug info table:
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(debugged here means functional debugging)
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| un-func-debugged | func-debugged | total |
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failed | 0 | 0 | 0 |
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Eval0 | 0 | 1 | 1 |
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Eval1 | 0 | 0 | 0 |
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Eval2 | 0 | 0 | 0 |
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#### Eval2 ratio:
|
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|
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#### CGA Coverage Detail List:
|
|
Task ID | Coverage
|
|
----------------------------------------
|
|
i2c_controller | 0.00%
|
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loose Eval2 pass metric applied: 0.8
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