345 lines
18 KiB
Plaintext
345 lines
18 KiB
Plaintext
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---------------custom config--------------
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run:
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mode: autoline
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save:
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en: True
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pub:
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prefix: SimpleSPI
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subdir: MyExperimentsSimple
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gpt:
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model: qwen-max
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rtlgen_model: qwen-max
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autoline:
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result_path: results/myproject_simple_spi
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 85.0
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probset:
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path: data/myproject/spi_controller_simple.jsonl
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mutant_path: None
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more_info_paths: []
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only: ['spi_controller_simple']
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promptscript: pychecker
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timeout: 300
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save_compile: False
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debug:
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max: 3
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itermax: 10
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update_desc: False
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TBcheck:
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discrim_mode: col_70_wrong_row_25_correct
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------------------------------------------
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------config info (custom + default)------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: 20260406_142058
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custom_path: config/myproject_simple_spi.yaml
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mode: autoline
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hostname: localhost
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pid: 1920
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pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0]
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save:
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en: True
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root: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/
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pub:
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prefix: SimpleSPI
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dir: saves/0406~0412/
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subdir: MyExperimentsSimple/
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: qwen-max
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: qwen-max
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results/myproject_simple_spi
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 85.0
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probset:
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path: data/myproject/spi_controller_simple.jsonl
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['spi_controller_simple']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 3
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: pychecker
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_70_wrong_row_25_correct
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: False
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save_finalcodes: True
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error_interruption: False
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_initialized: True
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------------------------------------------
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--------------default config--------------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: None
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custom_path: None
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mode: qwen-max
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save:
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en: True
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root: None
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pub:
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prefix: None
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dir: saves/$weekrange$/
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subdir:
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: 4o
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: None
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results
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cga:
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enabled: True
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max_iter: 10
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target_coverage: 100.0
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probset:
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path: None
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['lemmings3', 'lemmings4', 'ece241_2013_q8', '2014_q3fsm', 'm2014_q6', 'review2015_fsm', 'rule110', 'fsm_ps2']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 5
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: None
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_full_wrong
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: True
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save_finalcodes: True
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error_interruption: False
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------------------------------------------
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2026-04-06 14:20:58 | INFO | all configurations are loaded, starting the main process...
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2026-04-06 14:20:58 | INFO |
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2026-04-06 14:20:58 | INFO | ######################### task 1/1 [spi_controller_simple] #########################
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2026-04-06 14:21:38 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (39.56s used)
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2026-04-06 14:22:02 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (23.55s used)
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2026-04-06 14:55:47 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (2025.00s used)
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2026-04-06 14:56:28 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (41.46s used)
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2026-04-06 14:59:12 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (164.09s used)
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2026-04-06 14:59:12 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used)
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2026-04-06 15:23:48 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (1475.45s used)
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2026-04-06 15:24:31 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (43.01s used)
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2026-04-06 15:24:31 | INFO | [spi_controller_simple]
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2026-04-06 15:24:31 | INFO | [spi_controller_simple] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1)
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2026-04-06 16:43:36 | ERROR | [spi_controller_simple] Error when running TBsim, iter: 1. Message: list index out of range | location: autoline/TB_autoline.py, func: run_stages_core, line: 361 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317
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2026-04-06 16:43:36 | WARNING | [spi_controller_simple] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 366 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317
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2026-04-06 16:44:20 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (26.01s used)
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2026-04-06 16:45:07 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (47.46s used)
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2026-04-06 16:46:01 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (53.87s used)
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2026-04-06 16:46:53 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (51.75s used)
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2026-04-06 16:49:35 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (162.36s used)
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2026-04-06 16:49:35 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used)
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2026-04-06 16:54:38 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (302.79s used)
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (55.60s used)
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2026-04-06 16:55:34 | INFO | [spi_controller_simple]
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] iverilog compilation : passed!
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] python simulation : passed!
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] TBsim finished : True!
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2026-04-06 16:55:34 | INFO | [spi_controller_simple]
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] rtl list not found, generating naive rtls for testbench checking
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: missing_assignment | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_bit | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] 20 mutation-based RTLs generated (from reference RTL)
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Capturing Reference RTL outputs as ground truth...
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Capturing Reference RTL outputs as ground truth...
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Reference RTL check results: failed scenarios = [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10], passed scenarios = []
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Captured Reference RTL outputs for 10 scenarios
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Captured outputs for 10 scenarios
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2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination
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2026-04-06 16:55:35 | POSITIVE | [spi_controller_simple] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 0/10
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] [TBcheck] Testbench passed the funccheck
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] [TBcheck] self funccheck finished. Next Action: [pass]
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2026-04-06 16:55:35 | INFO | [spi_controller_simple]
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] [spi_controller_simple] Starting Coverage-Guided Agent (CGA)...
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] [spi_controller_simple] Running Semantic Analysis (Layer 0)...
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] FSM detected: state (4 states)
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] Total function points identified: 8
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] Energy allocator initialized: 8 targets
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] Diversity injector initialized with history file: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/test_history.json
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] Quality evaluator initialized
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2026-04-06 16:55:35 | INFO | [spi_controller_simple] --- CGA Iter 0 (Baseline) ---
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2026-04-06 16:55:38 | INFO | [spi_controller_simple] Baseline Coverage: 77.55%
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2026-04-06 16:55:38 | INFO | [spi_controller_simple] --- CGA Iter 1 / 15 ---
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2026-04-06 16:55:38 | INFO | [spi_controller_simple] Target: Exception_DefaultCase
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2026-04-06 16:55:38 | INFO | [spi_controller_simple] Asking LLM to fix missing logic (Current: 77.55%)...
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2026-04-06 16:56:28 | ERROR | [spi_controller_simple] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1295
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2026-04-06 16:56:28 | ERROR | [spi_controller_simple] [CGA-1] Verilator compilation failed: | location: autoline/TB_cga.py, func: run, line: 1301 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-06 16:56:28 | ERROR | [spi_controller_simple] obj_dir not created - compilation failed early | location: autoline/TB_cga.py, func: run, line: 1302 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-06 16:56:28 | INFO | [spi_controller_simple] [CGA-1] Asking LLM to fix compilation errors...
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2026-04-06 16:57:11 | ERROR | [spi_controller_simple] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1324
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2026-04-06 16:57:11 | INFO | [spi_controller_simple] Quality Evaluation: diversity=1.00
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2026-04-06 16:57:11 | WARNING | [spi_controller_simple] Regression or Failure. Discarding changes. | location: autoline/TB_cga.py, func: run, line: 1416 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-06 16:57:11 | INFO | [spi_controller_simple] --- CGA Iter 2 / 15 ---
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2026-04-06 16:57:11 | INFO | [spi_controller_simple] Target: Condition_4
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2026-04-06 16:57:11 | INFO | [spi_controller_simple] Asking LLM to fix missing logic (Current: 77.55%)...
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Quality Evaluation: diversity=0.49
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2026-04-06 16:58:11 | SUCCESS | [spi_controller_simple] Coverage Improved! +16.33% (77.55% -> 93.88%)
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2026-04-06 16:58:11 | SUCCESS | [spi_controller_simple] Target coverage reached!
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] CGA Finished. Final Coverage: 93.88%
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Energy report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/energy_report.txt
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Diversity report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/diversity_report.txt
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Quality evaluation report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/quality_evaluation_report.txt
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Semantic Coverage: 72.02%
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] Saved optimized TB to: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/final_TB.v
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking begins
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2026-04-06 16:58:11 | FAILED | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking failed!
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2026-04-06 16:58:11 | INFO | [spi_controller_simple] [TBeval] [spi_controller_simple] Eval 2/2b is skipped because Eval 1 failed
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2026-04-06 16:58:11 | INFO | [spi_controller_simple]
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2026-04-06 16:58:11 | INFO |
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########## Analyze of Chatbench_RunInfo ##########
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#### pass numbers:
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Eval2 : 0
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Eval1 : 0
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Eval0 : 1
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total : 1 (Failed: 0)
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passed TB by autoline reboot action (from TB3_check): 0
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passed TB by functional corrector: 0
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#### CGA Coverage Info:
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Average Coverage : 93.88%
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Max Coverage : 93.88%
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Min Coverage : 93.88%
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#### tokens and cost:
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average prompt tokens: 30199
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average completion tokens: 25441
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total cost: 2.1304
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average cost: 2.1304
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#### time:
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average time: 9432.35s
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#### debug info table:
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FUNCTIONAL debug info table:
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(debugged here means functional debugging)
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| un-func-debugged | func-debugged | total |
|
|
failed | 0 | 0 | 0 |
|
|
Eval0 | 0 | 1 | 1 |
|
|
Eval1 | 0 | 0 | 0 |
|
|
Eval2 | 0 | 0 | 0 |
|
|
|
|
#### Eval2 ratio:
|
|
|
|
#### CGA Coverage Detail List:
|
|
Task ID | Coverage
|
|
----------------------------------------
|
|
spi_controller_simple | 93.88%
|
|
|
|
loose Eval2 pass metric applied: 0.8
|
|
|
|
|