2 lines
1.1 KiB
JSON
2 lines
1.1 KiB
JSON
{"task_number": 1, "task_id": "my_smart_controller", "description": "\u8bbe\u8ba1\u4e00\u4e2a\u98ce\u6247\u63a7\u5236\u5668\uff0c\u5f53\u6e29\u5ea6\u8d85\u8fc7\u9608\u503c\u65f6\u8f93\u51fa\u9ad8\u7535\u5e73\u3002", "prompt": "Design a module named 'my_smart_controller'.\n\n\u529f\u80fd\u63cf\u8ff0 (Function Description):\n\u8bbe\u8ba1\u4e00\u4e2a\u98ce\u6247\u63a7\u5236\u5668\uff0c\u5f53\u6e29\u5ea6\u8d85\u8fc7\u9608\u503c\u65f6\u8f93\u51fa\u9ad8\u7535\u5e73\u3002\n\nModule Interface (Standard Verilog):\nmodule my_smart_controller (\n input clk,\n input rst_n,\n // \u8bf7\u5728\u6b64\u8865\u5145\u5177\u4f53\u7684\u7aef\u53e3\u5b9a\u4e49...\n output reg result\n);", "header": "module named 'my_smart_controller'.\n\n\u529f\u80fd\u63cf\u8ff0 (Function Description):\n\u8bbe\u8ba1\u4e00\u4e2a\u98ce\u6247\u63a7\u5236\u5668\uff0c\u5f53\u6e29\u5ea6\u8d85\u8fc7\u9608\u503c\u65f6\u8f93\u51fa\u9ad8\u7535\u5e73\u3002\n\nModule Interface (Standard Verilog):\nmodule my_smart_controller (\n input clk,\n input rst_n,\n // \u8bf7\u5728\u6b64\u8865\u5145\u5177\u4f53\u7684\u7aef\u53e3\u5b9a\u4e49...\n output reg result\n);"}
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