---------------custom config-------------- run: mode: autoline save: en: True pub: prefix: MyProjectCleanI2C subdir: MyExperimentsClean gpt: model: qwen-max rtlgen_model: qwen-max autoline: result_path: results/myproject_clean_i2c cga: enabled: True max_iter: 15 target_coverage: 100.0 probset: path: data/myproject/i2c_controller_clean.jsonl mutant_path: None more_info_paths: [] only: ['i2c_controller'] promptscript: pychecker timeout: 300 save_compile: False debug: max: 3 itermax: 10 update_desc: False TBcheck: discrim_mode: col_70_wrong_row_25_correct ------------------------------------------ ------config info (custom + default)------ run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: 20260424_002634 custom_path: config/myproject_clean_i2c.yaml mode: autoline hostname: localhost pid: 2155 pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0] save: en: True root: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/ pub: prefix: MyProjectCleanI2C dir: saves/0420~0426/ subdir: MyExperimentsClean/ log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: qwen-max key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: qwen-max iverilog: dir: task_id: autoline: result_path: results/myproject_clean_i2c cga: enabled: True max_iter: 15 target_coverage: 100.0 probset: path: data/myproject/i2c_controller_clean.jsonl mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['i2c_controller'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 3 reboot: 1 py_rollback: 2 onlyrun: None promptscript: pychecker timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_70_wrong_row_25_correct correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: False save_finalcodes: True error_interruption: False stage3: rtl_mode: auto max_inline_chars: 5000 save_rtl_file: True multi_tb: enabled: False auto_threshold_lines: 500 strategy: functional max_tb_count: 5 parallel: False merge_coverage: True _initialized: True ------------------------------------------ --------------default config-------------- run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: None custom_path: None mode: qwen-max save: en: True root: None pub: prefix: None dir: saves/$weekrange$/ subdir: log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: 4o key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: None iverilog: dir: task_id: autoline: result_path: results cga: enabled: True max_iter: 10 target_coverage: 100.0 probset: path: None mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['review2015_fancytimer', 'fsm_ps2data', 'bugs_case', 'review2015_fsmonehot', 'review2015_fsmseq', 'lemmings4', 'ece241_2013_q8'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 5 reboot: 1 py_rollback: 2 onlyrun: None promptscript: None timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_full_wrong correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: True save_finalcodes: True error_interruption: False stage3: rtl_mode: auto max_inline_chars: 5000 save_rtl_file: True multi_tb: enabled: False auto_threshold_lines: 500 strategy: functional max_tb_count: 5 parallel: False merge_coverage: True ------------------------------------------ 2026-04-24 00:26:34 | INFO | all configurations are loaded, starting the main process... 2026-04-24 00:26:34 | INFO | 2026-04-24 00:26:34 | INFO | ######################### task 1/1 [i2c_controller] ######################### 2026-04-24 00:29:01 | INFO | [i2c_controller] [TBgen] stage_0 ends (146.60s used) 2026-04-24 00:30:17 | INFO | [i2c_controller] [TBgen] stage_1 ends (76.33s used) 2026-04-24 00:31:34 | INFO | [i2c_controller] [TBgen] stage_2 ends (76.21s used) 2026-04-24 00:35:36 | INFO | [i2c_controller] [TBgen] stage_3 ends (242.24s used) 2026-04-24 00:37:35 | INFO | [i2c_controller] [TBgen] stage_4 ends (119.27s used) 2026-04-24 00:37:35 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used) 2026-04-24 00:41:05 | INFO | [i2c_controller] [TBgen] stage_4b ends (210.45s used) 2026-04-24 00:42:59 | INFO | [i2c_controller] [TBgen] stage_5 ends (113.13s used) 2026-04-24 00:42:59 | INFO | [i2c_controller] 2026-04-24 00:42:59 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1) 2026-04-24 00:45:58 | INFO | [i2c_controller] [TBsim] verilog iter - 1/3, total - 1/6: verilog DEBUG finished (179.47s used) 2026-04-24 00:45:58 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Rebooting... (debug_iter = 2) 2026-04-24 00:46:54 | INFO | [i2c_controller] [TBsim] stage_4 ends (55.40s used) 2026-04-24 00:46:54 | INFO | [i2c_controller] [TBsim] stage_checklist ends (0.00s used) 2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] stage_4b ends (123.45s used) 2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] verilog iter - 2/3, total - 2/6: verilog REBOOT finished (178.86s used) 2026-04-24 00:48:57 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 3) 2026-04-24 00:51:50 | INFO | [i2c_controller] [TBsim] verilog iter - 3/3, total - 3/6: verilog DEBUG finished (173.07s used) 2026-04-24 00:51:50 | INFO | [i2c_controller] [TBsim] iverilog compilation : failed! exceeded max debug iteration (3) 2026-04-24 00:51:50 | ERROR | [i2c_controller] Error when running TBsim, iter: 1. Message: TBsim: iverilog failed, python simulation is not allowed. | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 00:51:50 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 00:52:59 | INFO | [i2c_controller] [TBgen] stage_0 ends (53.97s used) 2026-04-24 00:53:30 | INFO | [i2c_controller] [TBgen] stage_1 ends (30.50s used) 2026-04-24 00:53:55 | INFO | [i2c_controller] [TBgen] stage_2 ends (25.69s used) 2026-04-24 00:54:52 | INFO | [i2c_controller] [TBgen] stage_3 ends (57.18s used) 2026-04-24 00:59:34 | INFO | [i2c_controller] [TBgen] stage_4 ends (281.22s used) 2026-04-24 02:19:14 | INFO | [i2c_controller] [TBgen] stage_checklist ends (4780.37s used) 2026-04-24 02:21:44 | INFO | [i2c_controller] [TBgen] stage_4b ends (150.28s used) 2026-04-24 02:23:14 | INFO | [i2c_controller] [TBgen] stage_5 ends (89.53s used) 2026-04-24 02:23:14 | INFO | [i2c_controller] 2026-04-24 02:23:14 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1) 2026-04-24 03:42:27 | ERROR | [i2c_controller] Error when running TBsim, iter: 2. Message: list index out of range | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 03:42:27 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 03:44:01 | INFO | [i2c_controller] [TBgen] stage_0 ends (76.34s used) 2026-04-24 03:44:38 | INFO | [i2c_controller] [TBgen] stage_1 ends (36.47s used) 2026-04-24 03:45:10 | INFO | [i2c_controller] [TBgen] stage_2 ends (32.50s used) 2026-04-24 03:47:09 | INFO | [i2c_controller] [TBgen] stage_3 ends (118.95s used) 2026-04-24 03:54:04 | INFO | [i2c_controller] [TBgen] stage_4 ends (415.05s used) 2026-04-24 03:54:04 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used) 2026-04-24 04:08:10 | INFO | [i2c_controller] [TBgen] stage_4b ends (845.96s used) 2026-04-24 04:09:32 | INFO | [i2c_controller] [TBgen] stage_5 ends (81.62s used) 2026-04-24 04:09:32 | INFO | [i2c_controller] 2026-04-24 04:09:32 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1) 2026-04-24 04:13:43 | INFO | [i2c_controller] [TBsim] verilog iter - 1/3, total - 1/6: verilog DEBUG finished (250.84s used) 2026-04-24 04:13:43 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Rebooting... (debug_iter = 2) 2026-04-24 04:14:23 | INFO | [i2c_controller] [TBsim] stage_4 ends (40.11s used) 2026-04-24 04:14:23 | INFO | [i2c_controller] [TBsim] stage_checklist ends (0.00s used) 2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] stage_4b ends (129.94s used) 2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] verilog iter - 2/3, total - 2/6: verilog REBOOT finished (170.06s used) 2026-04-24 04:16:33 | INFO | [i2c_controller] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 3) 2026-04-24 04:19:08 | INFO | [i2c_controller] [TBsim] verilog iter - 3/3, total - 3/6: verilog DEBUG finished (155.35s used) 2026-04-24 04:19:08 | INFO | [i2c_controller] [TBsim] iverilog compilation : failed! exceeded max debug iteration (3) 2026-04-24 04:19:08 | ERROR | [i2c_controller] Error when running TBsim, iter: 3. Message: TBsim: iverilog failed, python simulation is not allowed. | location: autoline/TB_autoline.py, func: run_stages_core, line: 389 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 04:19:08 | WARNING | [i2c_controller] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 394 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 318 2026-04-24 04:20:20 | INFO | [i2c_controller] [TBgen] stage_0 ends (56.59s used) 2026-04-24 04:20:38 | INFO | [i2c_controller] [TBgen] stage_1 ends (17.86s used) 2026-04-24 04:21:01 | INFO | [i2c_controller] [TBgen] stage_2 ends (23.04s used) 2026-04-24 04:21:51 | INFO | [i2c_controller] [TBgen] stage_3 ends (49.92s used) 2026-04-24 04:22:39 | INFO | [i2c_controller] [TBgen] stage_4 ends (48.02s used) 2026-04-24 04:22:39 | INFO | [i2c_controller] [TBgen] stage_checklist ends (0.00s used) 2026-04-24 04:25:09 | INFO | [i2c_controller] [TBgen] stage_4b ends (150.12s used) 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBgen] stage_5 ends (61.25s used) 2026-04-24 04:26:10 | INFO | [i2c_controller] 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] iverilog compilation : passed! 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] python simulation : passed! 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBsim] TBsim finished : True! 2026-04-24 04:26:10 | INFO | [i2c_controller] 2026-04-24 04:26:10 | INFO | [i2c_controller] rtl list not found, generating naive rtls for testbench checking 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: swap_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | DEBUG | [i2c_controller] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-24 04:26:10 | INFO | [i2c_controller] 20 mutation-based RTLs generated (from reference RTL) 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Plan 2: Capturing Reference RTL outputs as ground truth... 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Capturing Reference RTL outputs as ground truth... 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Reference RTL check results: failed scenarios = [1, 2, 3, 3, 3, 3, 3, 3, 4, 5, 6, 7], passed scenarios = [] 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Captured Reference RTL outputs for 7 scenarios 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Plan 2: Captured outputs for 7 scenarios 2026-04-24 04:26:10 | INFO | [i2c_controller] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination 2026-04-24 04:26:12 | POSITIVE | [i2c_controller] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 7/7 2026-04-24 04:26:12 | INFO | [i2c_controller] [TBcheck] Testbench passed the funccheck 2026-04-24 04:26:12 | INFO | [i2c_controller] [TBcheck] self funccheck finished. Next Action: [pass] 2026-04-24 04:26:12 | INFO | [i2c_controller] 2026-04-24 04:26:12 | INFO | [i2c_controller] [i2c_controller] Starting Coverage-Guided Agent (CGA)... 2026-04-24 04:26:12 | INFO | [i2c_controller] [i2c_controller] Running Semantic Analysis (Layer 0)... 2026-04-24 04:26:12 | INFO | [i2c_controller] FSM detected: state (15 states) 2026-04-24 04:26:12 | INFO | [i2c_controller] Total function points identified: 16 2026-04-24 04:26:12 | INFO | [i2c_controller] Energy allocator initialized: 16 targets 2026-04-24 04:26:12 | INFO | [i2c_controller] Diversity injector initialized with history file: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/test_history.json 2026-04-24 04:26:12 | INFO | [i2c_controller] Quality evaluator initialized 2026-04-24 04:26:12 | INFO | [i2c_controller] --- CGA Iter 0 (Baseline) --- 2026-04-24 04:26:12 | ERROR | [i2c_controller] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1362 2026-04-24 04:26:12 | INFO | [i2c_controller] Baseline Coverage: 0.00% 2026-04-24 04:26:12 | INFO | [i2c_controller] --- CGA Iter 1 / 15 --- 2026-04-24 04:26:12 | INFO | [i2c_controller] Target: FSM_state 2026-04-24 04:26:12 | INFO | [i2c_controller] CGA Finished. Final Coverage: 0.00% 2026-04-24 04:26:12 | INFO | [i2c_controller] No unreachable branches found in DUT. 2026-04-24 04:26:12 | INFO | [i2c_controller] Energy report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/energy_report.txt 2026-04-24 04:26:12 | INFO | [i2c_controller] Diversity report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/diversity_report.txt 2026-04-24 04:26:12 | INFO | [i2c_controller] Quality evaluation report saved to saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/CGA/quality_evaluation_report.txt 2026-04-24 04:26:12 | INFO | [i2c_controller] Semantic Coverage: 0.00% 2026-04-24 04:26:12 | INFO | [i2c_controller] Saved optimized TB to: saves/0420~0426/MyExperimentsClean/MyProjectCleanI2C_20260424_002634/i2c_controller/final_TB.v 2026-04-24 04:26:12 | INFO | [i2c_controller] [TBeval] Eval 1: Golden RTL checking begins 2026-04-24 04:26:13 | FAILED | [i2c_controller] [TBeval] Eval 1: Golden RTL checking failed! 2026-04-24 04:26:13 | INFO | [i2c_controller] [TBeval] [i2c_controller] Eval 2/2b is skipped because Eval 1 failed 2026-04-24 04:26:13 | INFO | [i2c_controller] 2026-04-24 04:26:13 | INFO | ########## Analyze of Chatbench_RunInfo ########## #### pass numbers: Eval2 : 0 Eval1 : 0 Eval0 : 1 total : 1 (Failed: 0) passed TB by autoline reboot action (from TB3_check): 0 passed TB by functional corrector: 0 #### CGA Coverage Info: Average Coverage : 0.00% (No coverage data found in JSON) #### tokens and cost: average prompt tokens: 85605 average completion tokens: 92365 total cost: 7.2540 average cost: 7.2540 #### time: average time: 14378.22s #### debug info table: FUNCTIONAL debug info table: (debugged here means functional debugging) | un-func-debugged | func-debugged | total | failed | 0 | 0 | 0 | Eval0 | 0 | 1 | 1 | Eval1 | 0 | 0 | 0 | Eval2 | 0 | 0 | 0 | #### Eval2 ratio: #### CGA Coverage Detail List: Task ID | Coverage ---------------------------------------- i2c_controller | 0.00% loose Eval2 pass metric applied: 0.8