module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL) begin
                if (fall_counter < 20)
                    fall_counter <= fall_counter + 1;
            end else begin
                fall_counter <= 0;
            end
            if (state == LEFT || state == RIGHT)
                direction <= (state == LEFT) ? 0 : 1;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = FALL;
                    else
                        next_state = direction ? RIGHT : LEFT;
                end
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b110;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= (fall_counter == 5'd20) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            LEFT: begin
                walk_left = 1;
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
            end
            RIGHT: begin
                walk_right = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
            end
            FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter >= 5'd20)
                        next_state = SPLAT;
                    else
                        next_state = LEFT;
                end
            end
            FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter >= 5'd20)
                        next_state = SPLAT;
                    else
                        next_state = RIGHT;
                end
            end
            DIG_LEFT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_LEFT;
            end
            DIG_RIGHT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
            end
            SPLAT: begin
                // Do nothing, stay in SPLAT state
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b110;
    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            LEFT: begin
                walk_left = 1;
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
            end
            RIGHT: begin
                walk_right = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
            end
            FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = SPLAT;
                    else
                        next_state = LEFT;
                end
            end
            FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = SPLAT;
                    else
                        next_state = RIGHT;
                end
            end
            DIG_LEFT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_LEFT;
            end
            DIG_RIGHT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
            end
            SPLAT: begin
                // Do nothing, stay in SPLAT state
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b110;
    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end
            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end
            FALL_LEFT: begin
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = SPLAT;
                    else
                        next_state = LEFT;
                end else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = SPLAT;
                    else
                        next_state = RIGHT;
                end else
                    next_state = FALL_RIGHT;
            end
            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end
            SPLAT: next_state = SPLAT;
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_L = 3'b010, FALL_R = 3'b011, DIG_L = 3'b100, DIG_R = 3'b101, SPLAT = 3'b110;
    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= (fall_counter == 5'd20) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT: begin
                if (!ground) next_state = FALL_L;
                else if (dig) next_state = DIG_L;
                else if (bump_left) next_state = RIGHT;
            end
            RIGHT: begin
                if (!ground) next_state = FALL_R;
                else if (dig) next_state = DIG_R;
                else if (bump_right) next_state = LEFT;
            end
            FALL_L: begin
                if (ground) begin
                    if (fall_counter > 5'd20) next_state = SPLAT;
                    else next_state = LEFT;
                end
            end
            FALL_R: begin
                if (ground) begin
                    if (fall_counter > 5'd20) next_state = SPLAT;
                    else next_state = RIGHT;
                end
            end
            DIG_L: begin
                if (!ground) next_state = FALL_L;
            end
            DIG_R: begin
                if (!ground) next_state = FALL_R;
            end
            SPLAT: next_state = SPLAT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_L) || (state == FALL_R);
        digging = (state == DIG_L) || (state == DIG_R);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b110;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (state == FALL_LEFT || state == FALL_RIGHT)
                fall_counter <= (fall_counter == 5'd20) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = RIGHT;
            end
            RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = LEFT;
            end
            FALL_LEFT: begin
                if (ground) next_state = (fall_counter > 5'd20) ? SPLAT : LEFT;
            end
            FALL_RIGHT: begin
                if (ground) next_state = (fall_counter > 5'd20) ? SPLAT : RIGHT;
            end
            DIG_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
            end
            SPLAT: next_state = SPLAT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter WALK_LEFT = 3'b000;
    parameter WALK_RIGHT = 3'b001;
    parameter FALL_LEFT = 3'b010;
    parameter FALL_RIGHT = 3'b011;
    parameter DIG_LEFT = 3'b100;
    parameter DIG_RIGHT = 3'b101;
    parameter SPLAT = 3'b110;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (state == FALL_LEFT || state == FALL_RIGHT)
                fall_counter <= (fall_counter < 20) ? fall_counter + 1 : fall_counter;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = WALK_RIGHT;
                else next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = WALK_LEFT;
                else next_state = WALK_RIGHT;
            end
            FALL_LEFT: begin
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_LEFT;
                else next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_RIGHT;
                else next_state = FALL_RIGHT;
            end
            DIG_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else next_state = DIG_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else next_state = DIG_RIGHT;
            end
            SPLAT: next_state = SPLAT;
            default: next_state = WALK_LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL)
                fall_counter <= (fall_counter == 31) ? 31 : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT && ground);
        walk_right = (state == RIGHT && ground);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

    always @(posedge clk or posedge areset) begin
        if (areset)
            direction <= 0;
        else if ((state == LEFT || state == RIGHT) && ground)
            direction <= (state == RIGHT);
    end

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            walk_left <= 1;
            walk_right <= 0;
            aaah <= 0;
            digging <= 0;
        end else if (fall_counter > 20 && ground) begin
            walk_left <= 0;
            walk_right <= 0;
            aaah <= 0;
            digging <= 0;
        end
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL)
                fall_counter <= (fall_counter == 31) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground) begin
                    if (fall_counter > 20)
                        next_state = FALL;
                    else
                        next_state = direction ? RIGHT : LEFT;
                end
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);

        if (state == LEFT || state == RIGHT)
            direction = (state == RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL)
                fall_counter <= (fall_counter == 31) ? 31 : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT && ground);
        walk_right = (state == RIGHT && ground);
        aaah = (state == FALL);
        digging = (state == DIG);

        if (state == LEFT || state == RIGHT)
            direction = (state == RIGHT);

        if (fall_counter > 20 && ground && state == FALL) begin
            walk_left = 0;
            walk_right = 0;
            aaah = 0;
            digging = 0;
        end
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b111;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= (fall_counter == 5'd20) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            LEFT: begin
                walk_left = 1;
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
            end
            RIGHT: begin
                walk_right = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
            end
            FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter >= 5'd20)
                        next_state = SPLAT;
                    else
                        next_state = LEFT;
                end
            end
            FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    if (fall_counter >= 5'd20)
                        next_state = SPLAT;
                    else
                        next_state = RIGHT;
                end
            end
            DIG_LEFT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_LEFT;
            end
            DIG_RIGHT: begin
                digging = 1;
                if (!ground)
                    next_state = FALL_RIGHT;
            end
            SPLAT: begin
                // Do nothing, stay in SPLAT state
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL)
                fall_counter <= (fall_counter == 5'd20) ? fall_counter : fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground) begin
                    if (fall_counter > 5'd20)
                        next_state = FALL;
                    else
                        next_state = direction ? RIGHT : LEFT;
                end
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);

        if (state == LEFT || state == RIGHT)
            direction = (state == RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter WALK_LEFT = 3'd0, WALK_RIGHT = 3'd1, FALL_LEFT = 3'd2, FALL_RIGHT = 3'd3, DIG_LEFT = 3'd4, DIG_RIGHT = 3'd5, SPLAT = 3'd6;
    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (state == FALL_LEFT || state == FALL_RIGHT)
                fall_counter <= fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            WALK_LEFT:
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = WALK_RIGHT;
            WALK_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = WALK_LEFT;
            FALL_LEFT:
                if (ground) next_state = (fall_counter > 20) ? SPLAT : WALK_LEFT;
            FALL_RIGHT:
                if (ground) next_state = (fall_counter > 20) ? SPLAT : WALK_RIGHT;
            DIG_LEFT:
                if (!ground) next_state = FALL_LEFT;
            DIG_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
            SPLAT:
                next_state = SPLAT;
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter WALK_LEFT = 3'b000;
    parameter WALK_RIGHT = 3'b001;
    parameter FALL_LEFT = 3'b010;
    parameter FALL_RIGHT = 3'b011;
    parameter DIG_LEFT = 3'b100;
    parameter DIG_RIGHT = 3'b101;
    parameter SPLAT = 3'b110;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (state == FALL_LEFT || state == FALL_RIGHT) begin
                if (fall_counter < 20)
                    fall_counter <= fall_counter + 1;
            end else begin
                fall_counter <= 0;
            end
        end
    end

    always @(*) begin
        case (state)
            WALK_LEFT:
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = WALK_RIGHT;
                else next_state = WALK_LEFT;
            WALK_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = WALK_LEFT;
                else next_state = WALK_RIGHT;
            FALL_LEFT:
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_LEFT;
                else next_state = FALL_LEFT;
            FALL_RIGHT:
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_RIGHT;
                else next_state = FALL_RIGHT;
            DIG_LEFT:
                if (!ground) next_state = FALL_LEFT;
                else next_state = DIG_LEFT;
            DIG_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
                else next_state = DIG_RIGHT;
            SPLAT:
                next_state = SPLAT;
            default:
                next_state = WALK_LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 3'b000, RIGHT = 3'b001, FALL_LEFT = 3'b010, FALL_RIGHT = 3'b011, DIG_LEFT = 3'b100, DIG_RIGHT = 3'b101, SPLAT = 3'b110;
    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (aaah)
                fall_counter <= fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = RIGHT;
            end
            RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = LEFT;
            end
            FALL_LEFT: begin
                if (ground) begin
                    if (fall_counter > 20) next_state = SPLAT;
                    else next_state = LEFT;
                end
            end
            FALL_RIGHT: begin
                if (ground) begin
                    if (fall_counter > 20) next_state = SPLAT;
                    else next_state = RIGHT;
                end
            end
            DIG_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
            end
            SPLAT: next_state = SPLAT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
        digging = (state == DIG_LEFT) || (state == DIG_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg [4:0] fall_counter;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            fall_counter <= 0;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == FALL) begin
                if (fall_counter < 21) fall_counter <= fall_counter + 1;
            end else begin
                fall_counter <= 0;
            end
            if (state == LEFT || state == RIGHT) direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground) next_state = FALL;
                else if (dig) next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right)) next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground) next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground) next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT && ground);
        walk_right = (state == RIGHT && ground);
        aaah = (state == FALL);
        digging = (state == DIG);
        if (fall_counter > 20 && ground) begin
            walk_left = 0;
            walk_right = 0;
            aaah = 0;
            digging = 0;
        end
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter WALK_LEFT = 3'b000;
    parameter WALK_RIGHT = 3'b001;
    parameter FALL_LEFT = 3'b010;
    parameter FALL_RIGHT = 3'b011;
    parameter DIG_LEFT = 3'b100;
    parameter DIG_RIGHT = 3'b101;
    parameter SPLAT = 3'b110;

    reg [2:0] state, next_state;
    reg [4:0] fall_counter;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
            fall_counter <= 0;
        end else begin
            state <= next_state;
            if (state == FALL_LEFT || state == FALL_RIGHT)
                fall_counter <= fall_counter + 1;
            else
                fall_counter <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            WALK_LEFT:
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left) next_state = WALK_RIGHT;
            WALK_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right) next_state = WALK_LEFT;
            FALL_LEFT:
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_LEFT;
            FALL_RIGHT:
                if (ground && fall_counter > 20) next_state = SPLAT;
                else if (ground) next_state = WALK_RIGHT;
            DIG_LEFT:
                if (!ground) next_state = FALL_LEFT;
            DIG_RIGHT:
                if (!ground) next_state = FALL_RIGHT;
            SPLAT:
                next_state = SPLAT;
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
        digging = (state == DIG_LEFT || state == DIG_RIGHT);
    end

endmodule


module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    reg [3:0] state;
    reg [3:0] pattern;
    reg [2:0] shift_count;

    parameter IDLE = 4'd0,
              DETECT = 4'd1,
              SHIFT = 4'd2,
              COUNT = 4'd3,
              TIMEOUT = 4'd4;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            pattern <= 4'b0000;
            shift_count <= 3'd0;
            shift_ena <= 1'b0;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    pattern <= {pattern[2:0], data};
                    if (pattern == 4'b1101) begin
                        state <= SHIFT;
                        shift_ena <= 1'b1;
                        shift_count <= 3'd0;
                    end
                end
                SHIFT: begin
                    pattern <= {pattern[2:0], data};
                    shift_count <= shift_count + 1'b1;
                    if (shift_count == 3'd3) begin
                        state <= COUNT;
                        shift_ena <= 1'b0;
                        counting <= 1'b1;
                    end
                end
                COUNT: begin
                    if (done_counting) begin
                        state <= TIMEOUT;
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end
                TIMEOUT: begin
                    if (ack) begin
                        state <= IDLE;
                        done <= 1'b0;
                    end
                end
                default: state <= IDLE;
            endcase
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    reg [3:0] state;
    reg [3:0] pattern;
    reg [2:0] shift_count;

    parameter IDLE = 4'd0, CHECK_1 = 4'd1, CHECK_11 = 4'd2, CHECK_110 = 4'd3,
              SHIFT = 4'd4, WAIT_COUNT = 4'd5, NOTIFY = 4'd6;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            pattern <= 4'b0000;
            shift_count <= 3'd0;
            shift_ena <= 1'b0;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    if (data) state <= CHECK_1;
                    pattern <= {pattern[2:0], data};
                end
                CHECK_1: begin
                    if (data) state <= CHECK_11;
                    else state <= IDLE;
                    pattern <= {pattern[2:0], data};
                end
                CHECK_11: begin
                    if (!data) state <= CHECK_110;
                    else state <= CHECK_11;
                    pattern <= {pattern[2:0], data};
                end
                CHECK_110: begin
                    if (data) state <= SHIFT;
                    else state <= IDLE;
                    pattern <= {pattern[2:0], data};
                    shift_ena <= 1'b1;
                    shift_count <= 3'd0;
                end
                SHIFT: begin
                    if (shift_count == 3'd3) begin
                        state <= WAIT_COUNT;
                        shift_ena <= 1'b0;
                        counting <= 1'b1;
                    end else begin
                        shift_count <= shift_count + 1'b1;
                    end
                end
                WAIT_COUNT: begin
                    if (done_counting) begin
                        state <= NOTIFY;
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end
                NOTIFY: begin
                    if (ack) begin
                        state <= IDLE;
                        done <= 1'b0;
                    end
                end
                default: state <= IDLE;
            endcase
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    localparam IDLE = 3'd0,
               DETECT1 = 3'd1,
               DETECT11 = 3'd2,
               DETECT110 = 3'd3,
               DETECT1101 = 3'd4,
               SHIFT = 3'd5,
               COUNT = 3'd6,
               DONE = 3'd7;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (state)
            IDLE: next_state = data ? DETECT1 : IDLE;
            DETECT1: next_state = data ? DETECT11 : IDLE;
            DETECT11: next_state = data ? DETECT11 : DETECT110;
            DETECT110: next_state = data ? DETECT1101 : IDLE;
            DETECT1101: next_state = SHIFT;
            SHIFT: begin
                shift_ena = 1'b1;
                if (shift_count == 3'd3)
                    next_state = COUNT;
            end
            COUNT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE;
            end
            DONE: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 3'd0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1'b1;
        else
            shift_count <= 3'd0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, S1 = 3'd1, S11 = 3'd2, S110 = 3'd3, S1101 = 3'd4;
    parameter SHIFT = 3'd5, COUNT = 3'd6, DONE = 3'd7;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: if (data) next_state = S1;
            S1: next_state = data ? S11 : IDLE;
            S11: next_state = data ? S11 : S110;
            S110: next_state = data ? S1101 : IDLE;
            S1101: next_state = SHIFT;
            SHIFT: if (shift_count == 3) next_state = COUNT;
            COUNT: if (done_counting) next_state = DONE;
            DONE: if (ack) next_state = IDLE;
        endcase
    end

    always @(posedge clk) begin
        if (reset) begin
            shift_ena <= 0;
            counting <= 0;
            done <= 0;
            shift_count <= 0;
        end else begin
            shift_ena <= (state == SHIFT);
            counting <= (state == COUNT);
            done <= (state == DONE);

            if (state == SHIFT)
                shift_count <= shift_count + 1;
            else
                shift_count <= 0;
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0,
              DETECT_1 = 3'd1,
              DETECT_11 = 3'd2,
              DETECT_110 = 3'd3,
              SHIFT = 3'd4,
              COUNT = 3'd5,
              DONE = 3'd6;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE:
                if (data) next_state = DETECT_1;
            DETECT_1:
                if (data) next_state = DETECT_11;
                else next_state = IDLE;
            DETECT_11:
                if (data) next_state = DETECT_11;
                else next_state = DETECT_110;
            DETECT_110:
                if (data) next_state = SHIFT;
                else next_state = IDLE;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, SEQ_1 = 3'd1, SEQ_11 = 3'd2, SEQ_110 = 3'd3, SHIFT = 3'd4, COUNT = 3'd5, NOTIFY = 3'd6;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: next_state = data ? SEQ_1 : IDLE;
            SEQ_1: next_state = data ? SEQ_11 : IDLE;
            SEQ_11: next_state = data ? SEQ_11 : SEQ_110;
            SEQ_110: next_state = data ? SHIFT : IDLE;
            SHIFT: next_state = (shift_count == 3) ? COUNT : SHIFT;
            COUNT: next_state = done_counting ? NOTIFY : COUNT;
            NOTIFY: next_state = ack ? IDLE : NOTIFY;
            default: next_state = IDLE;
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            shift_ena <= 0;
            counting <= 0;
            done <= 0;
            shift_count <= 0;
        end else begin
            case (state)
                SHIFT: begin
                    shift_ena <= 1;
                    shift_count <= shift_count + 1;
                end
                COUNT: begin
                    shift_ena <= 0;
                    counting <= 1;
                end
                NOTIFY: begin
                    counting <= 0;
                    done <= 1;
                end
                default: begin
                    shift_ena <= 0;
                    counting <= 0;
                    done <= 0;
                    shift_count <= 0;
                end
            endcase
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0,
              DETECT_1 = 3'd1,
              DETECT_11 = 3'd2,
              DETECT_110 = 3'd3,
              SHIFT = 3'd4,
              COUNT = 3'd5,
              DONE = 3'd6;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE:
                if (data) next_state = DETECT_1;
            DETECT_1:
                if (data) next_state = DETECT_11;
                else next_state = IDLE;
            DETECT_11:
                if (data) next_state = DETECT_110;
                else next_state = IDLE;
            DETECT_110:
                if (!data) next_state = SHIFT;
                else next_state = DETECT_11;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    parameter IDLE = 3'd0;
    parameter DETECT_1 = 3'd1;
    parameter DETECT_11 = 3'd2;
    parameter DETECT_110 = 3'd3;
    parameter SHIFT = 3'd4;
    parameter COUNT = 3'd5;
    parameter NOTIFY = 3'd6;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE:
                if (data) next_state = DETECT_1;
            DETECT_1:
                if (data) next_state = DETECT_11;
                else next_state = IDLE;
            DETECT_11:
                if (data) next_state = DETECT_11;
                else next_state = DETECT_110;
            DETECT_110:
                if (data) next_state = SHIFT;
                else next_state = IDLE;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = NOTIFY;
            end
            NOTIFY: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    reg [3:0] state;
    reg [3:0] pattern;
    reg [2:0] shift_count;

    parameter IDLE = 4'b0000;
    parameter DETECT = 4'b0001;
    parameter SHIFT = 4'b0010;
    parameter COUNT = 4'b0011;
    parameter FINISH = 4'b0100;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            pattern <= 4'b0000;
            shift_count <= 3'b000;
            shift_ena <= 1'b0;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    pattern <= {pattern[2:0], data};
                    if (pattern == 4'b1101) begin
                        state <= SHIFT;
                        shift_ena <= 1'b1;
                        shift_count <= 3'b000;
                    end
                end
                SHIFT: begin
                    shift_count <= shift_count + 1'b1;
                    if (shift_count == 3'b011) begin
                        state <= COUNT;
                        shift_ena <= 1'b0;
                        counting <= 1'b1;
                    end
                end
                COUNT: begin
                    if (done_counting) begin
                        state <= FINISH;
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end
                FINISH: begin
                    if (ack) begin
                        state <= IDLE;
                        done <= 1'b0;
                        pattern <= 4'b0000;
                    end
                end
                default: state <= IDLE;
            endcase
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, DETECT1 = 3'd1, DETECT11 = 3'd2, DETECT110 = 3'd3, SHIFT = 3'd4, COUNT = 3'd5, TIMEOUT = 3'd6;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: if (data) next_state = DETECT1;
            DETECT1: if (data) next_state = DETECT11; else next_state = IDLE;
            DETECT11: if (data) next_state = DETECT110; else next_state = DETECT1;
            DETECT110: begin
                if (!data) next_state = SHIFT;
                else next_state = DETECT11;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = TIMEOUT;
            end
            TIMEOUT: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, DETECT1 = 3'd1, DETECT11 = 3'd2, DETECT110 = 3'd3, SHIFT = 3'd4, COUNT = 3'd5, NOTIFY = 3'd6;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: if (data) next_state = DETECT1;
            DETECT1: if (data) next_state = DETECT11; else next_state = IDLE;
            DETECT11: if (data) next_state = DETECT110; else next_state = DETECT1;
            DETECT110: begin
                if (!data) next_state = SHIFT;
                else next_state = DETECT11;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = NOTIFY;
            end
            NOTIFY: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, DETECT_1 = 3'd1, DETECT_11 = 3'd2, DETECT_110 = 3'd3,
              SHIFT = 3'd4, COUNT = 3'd5, NOTIFY = 3'd6;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            shift_count <= 0;
        end else begin
            state <= next_state;
            if (state == SHIFT)
                shift_count <= shift_count + 1;
            else
                shift_count <= 0;
        end
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: if (data) next_state = DETECT_1;
            DETECT_1: if (data) next_state = DETECT_11; else next_state = IDLE;
            DETECT_11: if (data) next_state = DETECT_110; else next_state = DETECT_1;
            DETECT_110: begin
                if (!data) next_state = SHIFT;
                else next_state = DETECT_11;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = NOTIFY;
            end
            NOTIFY: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, S1 = 3'd1, S11 = 3'd2, S110 = 3'd3, S1101 = 3'd4,
              SHIFT = 3'd5, COUNT = 3'd6, DONE = 3'd7;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: next_state = data ? S1 : IDLE;
            S1: next_state = data ? S11 : IDLE;
            S11: next_state = data ? S11 : S110;
            S110: next_state = data ? S1101 : IDLE;
            S1101: begin
                next_state = SHIFT;
                shift_ena = 1;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk) begin
        if (reset || state != SHIFT)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, DETECT1 = 3'd1, DETECT11 = 3'd2, DETECT110 = 3'd3, SHIFT = 3'd4, COUNT = 3'd5, DONE = 3'd6;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE:
                if (data) next_state = DETECT1;
            DETECT1:
                if (data) next_state = DETECT11;
                else next_state = IDLE;
            DETECT11:
                if (data) next_state = DETECT11;
                else next_state = DETECT110;
            DETECT110:
                if (data) begin
                    next_state = SHIFT;
                    shift_ena = 1;
                end
                else next_state = IDLE;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, S1 = 3'd1, S11 = 3'd2, S110 = 3'd3, S1101 = 3'd4, SHIFT = 3'd5, COUNT = 3'd6, DONE = 3'd7;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE:  next_state = data ? S1 : IDLE;
            S1:    next_state = data ? S11 : IDLE;
            S11:   next_state = data ? S11 : S110;
            S110:  next_state = data ? S1101 : IDLE;
            S1101: next_state = SHIFT;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3)
                    next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk) begin
        if (reset || state != SHIFT)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, SEQ1 = 3'd1, SEQ2 = 3'd2, SEQ3 = 3'd3, SHIFT = 3'd4, COUNT = 3'd5, NOTIFY = 3'd6;
    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: if (data) next_state = SEQ1;
            SEQ1: next_state = data ? SEQ1 : SEQ2;
            SEQ2: next_state = data ? SEQ3 : IDLE;
            SEQ3: next_state = data ? SHIFT : IDLE;
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3) next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting) next_state = NOTIFY;
            end
            NOTIFY: begin
                done = 1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk) begin
        if (reset || state != SHIFT)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    parameter IDLE = 3'd0, S1 = 3'd1, S11 = 3'd2, S110 = 3'd3, S1101 = 3'd4,
              SHIFT = 3'd5, COUNT = 3'd6, NOTIFY = 3'd7;

    reg [2:0] state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: next_state = data ? S1 : IDLE;
            S1: next_state = data ? S11 : IDLE;
            S11: next_state = data ? S11 : S110;
            S110: next_state = data ? S1101 : IDLE;
            S1101: begin
                next_state = SHIFT;
                shift_ena = 1;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3)
                    next_state = COUNT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = NOTIFY;
            end
            NOTIFY: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule


module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, live_neighbors;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            live_neighbors = 0;

            for (j = -1; j <= 1; j = j + 1) begin
                live_neighbors = live_neighbors + q[((row + 16 + j) % 16) * 16 + ((col + 15) % 16)];
                live_neighbors = live_neighbors + q[((row + 16 + j) % 16) * 16 + ((col + 1) % 16)];
            end
            live_neighbors = live_neighbors + q[((row + 15) % 16) * 16 + col];
            live_neighbors = live_neighbors + q[((row + 1) % 16) * 16 + col];
            live_neighbors = live_neighbors - q[i];

            case (live_neighbors)
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, neighbors;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            neighbors = 0;

            for (j = 0; j < 8; j = j + 1) begin
                case (j)
                    0: neighbors = neighbors + q[((row - 1 + 16) % 16) * 16 + ((col - 1 + 16) % 16)];
                    1: neighbors = neighbors + q[((row - 1 + 16) % 16) * 16 + col];
                    2: neighbors = neighbors + q[((row - 1 + 16) % 16) * 16 + ((col + 1) % 16)];
                    3: neighbors = neighbors + q[row * 16 + ((col - 1 + 16) % 16)];
                    4: neighbors = neighbors + q[row * 16 + ((col + 1) % 16)];
                    5: neighbors = neighbors + q[((row + 1) % 16) * 16 + ((col - 1 + 16) % 16)];
                    6: neighbors = neighbors + q[((row + 1) % 16) * 16 + col];
                    7: neighbors = neighbors + q[((row + 1) % 16) * 16 + ((col + 1) % 16)];
                endcase
            end

            case (neighbors)
                0, 1: next_q[i] = 1'b0;
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer neighbors = 0;
                integer x, y;

                for (x = -1; x <= 1; x = x + 1) begin
                    for (y = -1; y <= 1; y = y + 1) begin
                        if (x != 0 || y != 0) begin
                            neighbors = neighbors + q[((i+x+16)%16)*16 + (j+y+16)%16];
                        end
                    end
                end

                case (neighbors)
                    0, 1: next_q[i*16+j] = 1'b0;
                    2: next_q[i*16+j] = q[i*16+j];
                    3: next_q[i*16+j] = 1'b1;
                    default: next_q[i*16+j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col;
    reg [3:0] neighbors;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            neighbors = 0;

            for (j = -1; j <= 1; j = j + 1) begin
                neighbors = neighbors + q[((row + 16 - 1) % 16) * 16 + ((col + 16 + j) % 16)];
                neighbors = neighbors + q[((row + 16 + 1) % 16) * 16 + ((col + 16 + j) % 16)];
            end
            neighbors = neighbors + q[row * 16 + ((col + 16 - 1) % 16)];
            neighbors = neighbors + q[row * 16 + ((col + 16 + 1) % 16)];

            case (neighbors)
                4'h2: next_q[i] = q[i];
                4'h3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, count;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            count = 0;

            for (j = -1; j <= 1; j = j + 1) begin
                count = count + q[((row + 16 + j) % 16) * 16 + ((col + 15) % 16)];
                count = count + q[((row + 16 + j) % 16) * 16 + col];
                count = count + q[((row + 16 + j) % 16) * 16 + ((col + 17) % 16)];
            end

            count = count - q[i];

            case (count)
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer count;
                integer row, col;
                count = 0;

                for (row = -1; row <= 1; row = row + 1) begin
                    for (col = -1; col <= 1; col = col + 1) begin
                        if (row != 0 || col != 0) begin
                            integer neighbor_row, neighbor_col;
                            neighbor_row = (i + row + 16) % 16;
                            neighbor_col = (j + col + 16) % 16;
                            count = count + q[neighbor_row * 16 + neighbor_col];
                        end
                    end
                end

                case (count)
                    2: next_q[i * 16 + j] = q[i * 16 + j];
                    3: next_q[i * 16 + j] = 1'b1;
                    default: next_q[i * 16 + j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, count;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            count = 0;

            for (j = 0; j < 8; j = j + 1) begin
                case (j)
                    0: count = count + q[((row-1+16)%16)*16 + ((col-1+16)%16)];
                    1: count = count + q[((row-1+16)%16)*16 + col];
                    2: count = count + q[((row-1+16)%16)*16 + ((col+1)%16)];
                    3: count = count + q[row*16 + ((col-1+16)%16)];
                    4: count = count + q[row*16 + ((col+1)%16)];
                    5: count = count + q[((row+1)%16)*16 + ((col-1+16)%16)];
                    6: count = count + q[((row+1)%16)*16 + col];
                    7: count = count + q[((row+1)%16)*16 + ((col+1)%16)];
                endcase
            end

            case (count)
                0, 1: next_q[i] = 1'b0;
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer count;
                integer row, col, index;
                count = 0;

                for (row = -1; row <= 1; row = row + 1) begin
                    for (col = -1; col <= 1; col = col + 1) begin
                        if (row != 0 || col != 0) begin
                            index = ((i + row + 16) % 16) * 16 + ((j + col + 16) % 16);
                            count = count + q[index];
                        end
                    end
                end

                case (count)
                    0, 1: next_q[i*16 + j] = 1'b0;
                    2: next_q[i*16 + j] = q[i*16 + j];
                    3: next_q[i*16 + j] = 1'b1;
                    default: next_q[i*16 + j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, count;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            count = 0;

            for (j = -1; j <= 1; j = j + 1) begin
                count = count + q[((row + 16 - 1) % 16) * 16 + ((col + 16 + j) % 16)];
                count = count + q[((row + 16 + 1) % 16) * 16 + ((col + 16 + j) % 16)];
            end
            count = count + q[row * 16 + ((col + 16 - 1) % 16)];
            count = count + q[row * 16 + ((col + 16 + 1) % 16)];

            case (count)
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer neighbors = 0;
                integer x, y;

                for (x = -1; x <= 1; x = x + 1) begin
                    for (y = -1; y <= 1; y = y + 1) begin
                        if (x != 0 || y != 0) begin
                            integer nx = (i + x + 16) % 16;
                            integer ny = (j + y + 16) % 16;
                            neighbors = neighbors + q[nx*16 + ny];
                        end
                    end
                end

                case (neighbors)
                    2: next_q[i*16 + j] = q[i*16 + j];
                    3: next_q[i*16 + j] = 1'b1;
                    default: next_q[i*16 + j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j, row, col, neighbors;

    always @(*) begin
        for (i = 0; i < 256; i = i + 1) begin
            row = i / 16;
            col = i % 16;
            neighbors = 0;

            for (j = 0; j < 8; j = j + 1) begin
                case (j)
                    0: neighbors = neighbors + q[((row-1+16)%16)*16 + ((col-1+16)%16)];
                    1: neighbors = neighbors + q[((row-1+16)%16)*16 + col];
                    2: neighbors = neighbors + q[((row-1+16)%16)*16 + ((col+1)%16)];
                    3: neighbors = neighbors + q[row*16 + ((col-1+16)%16)];
                    4: neighbors = neighbors + q[row*16 + ((col+1)%16)];
                    5: neighbors = neighbors + q[((row+1)%16)*16 + ((col-1+16)%16)];
                    6: neighbors = neighbors + q[((row+1)%16)*16 + col];
                    7: neighbors = neighbors + q[((row+1)%16)*16 + ((col+1)%16)];
                endcase
            end

            case (neighbors)
                2: next_q[i] = q[i];
                3: next_q[i] = 1'b1;
                default: next_q[i] = 1'b0;
            endcase
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer neighbors = 0;
                integer row, col;

                for (row = -1; row <= 1; row = row + 1) begin
                    for (col = -1; col <= 1; col = col + 1) begin
                        if (row != 0 || col != 0) begin
                            neighbors = neighbors + q[((i + row + 16) % 16) * 16 + ((j + col + 16) % 16)];
                        end
                    end
                end

                case (neighbors)
                    2: next_q[i*16 + j] = q[i*16 + j];
                    3: next_q[i*16 + j] = 1;
                    default: next_q[i*16 + j] = 0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer neighbors = 0;
                integer x, y;

                for (x = -1; x <= 1; x = x + 1) begin
                    for (y = -1; y <= 1; y = y + 1) begin
                        if (x != 0 || y != 0) begin
                            integer nx = (i + x + 16) % 16;
                            integer ny = (j + y + 16) % 16;
                            neighbors = neighbors + q[nx * 16 + ny];
                        end
                    end
                end

                case (neighbors)
                    0, 1: next_q[i * 16 + j] = 1'b0;
                    2: next_q[i * 16 + j] = q[i * 16 + j];
                    3: next_q[i * 16 + j] = 1'b1;
                    default: next_q[i * 16 + j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q
);

    reg [255:0] next_q;
    integer i, j;

    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                integer count;
                integer x, y;
                count = 0;

                for (x = -1; x <= 1; x = x + 1) begin
                    for (y = -1; y <= 1; y = y + 1) begin
                        if (x != 0 || y != 0) begin
                            integer nx, ny;
                            nx = (i + x + 16) % 16;
                            ny = (j + y + 16) % 16;
                            count = count + q[nx*16 + ny];
                        end
                    end
                end

                case (count)
                    2: next_q[i*16 + j] = q[i*16 + j];
                    3: next_q[i*16 + j] = 1'b1;
                    default: next_q[i*16 + j] = 1'b0;
                endcase
            end
        end
    end

    always @(posedge clk) begin
        if (load)
            q <= data;
        else
            q <= next_q;
    end

endmodule


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
                else
                    next_state = state;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
                else
                    next_state = FALL;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
                else
                    next_state = DIG;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg last_direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            last_direction <= 0;
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                last_direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT: begin
                if (!ground) next_state = FALL;
                else if (dig) next_state = DIG;
                else if (bump_left) next_state = RIGHT;
            end
            RIGHT: begin
                if (!ground) next_state = FALL;
                else if (dig) next_state = DIG;
                else if (bump_right) next_state = LEFT;
            end
            FALL: begin
                if (ground) next_state = last_direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground) next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            direction <= 0;
        end else if (state == LEFT || state == RIGHT) begin
            if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                direction <= ~direction;
        end
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;  // 0 for left, 1 for right

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if ((state == LEFT || state == RIGHT) && ground)
                direction <= (bump_left && !bump_right) ? 1 :
                             (bump_right && !bump_left) ? 0 : direction;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT:
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else
                    next_state = direction ? RIGHT : LEFT;
            FALL:
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            DIG:
                if (!ground)
                    next_state = FALL;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    localparam WALK_LEFT = 2'b00;
    localparam WALK_RIGHT = 2'b01;
    localparam FALL = 2'b10;
    localparam DIG = 2'b11;

    reg [1:0] state, next_state;
    reg last_direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
            last_direction <= 0;
        end else begin
            state <= next_state;
            if (state == WALK_LEFT || state == WALK_RIGHT)
                last_direction <= state[0];
        end
    end

    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
            FALL: begin
                if (ground)
                    next_state = last_direction ? WALK_RIGHT : WALK_LEFT;
                else
                    next_state = FALL;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
                else
                    next_state = DIG;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg last_direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            last_direction <= 1'b0; // 0 for left, 1 for right
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                last_direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = last_direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state != FALL && state != DIG)
                direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
                else
                    next_state = state;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
                else
                    next_state = FALL;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
                else
                    next_state = DIG;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL = 2'b10, DIG = 2'b11;
    reg [1:0] state, next_state;
    reg direction;  // 0 for left, 1 for right

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT;
            direction <= 0;
        end else begin
            state <= next_state;
            if (state == LEFT || state == RIGHT)
                direction <= (state == RIGHT);
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            LEFT, RIGHT: begin
                if (!ground)
                    next_state = FALL;
                else if (dig)
                    next_state = DIG;
                else if ((state == LEFT && bump_left) || (state == RIGHT && bump_right))
                    next_state = (state == LEFT) ? RIGHT : LEFT;
            end
            FALL: begin
                if (ground)
                    next_state = direction ? RIGHT : LEFT;
            end
            DIG: begin
                if (!ground)
                    next_state = FALL;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL);
        digging = (state == DIG);
    end

endmodule