module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh <= {4'h1, 4'h0};
                            end
                            else begin
                                hh <= hh + 8'h01;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 4'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 4'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 4'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 4'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
        end else if (ena) begin
            if (ss == 8'h59) begin
                ss <= 8'h00;
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm;
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;
                    end else begin
                        hh[3:0] <= hh[3:0] + 1'b1;
                        if (hh[3:0] == 4'h9) begin
                            hh[3:0] <= 4'h0;
                            hh[7:4] <= hh[7:4] + 1'b1;
                        end
                    end
                end else begin
                    mm[3:0] <= mm[3:0] + 1'b1;
                    if (mm[3:0] == 4'h9) begin
                        mm[3:0] <= 4'h0;
                        mm[7:4] <= mm[7:4] + 1'b1;
                    end
                end
            end else begin
                ss[3:0] <= ss[3:0] + 1'b1;
                if (ss[3:0] == 4'h9) begin
                    ss[3:0] <= 4'h0;
                    ss[7:4] <= ss[7:4] + 1'b1;
                end
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
        end else if (ena) begin
            if (ss == 8'h59) begin
                ss <= 8'h00;
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm;
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;
                    end else if (hh[3:0] == 4'h9) begin
                        hh <= {hh[7:4] + 1'b1, 4'h0};
                    end else begin
                        hh[3:0] <= hh[3:0] + 1'b1;
                    end
                end else if (mm[3:0] == 4'h9) begin
                    mm <= {mm[7:4] + 1'b1, 4'h0};
                end else begin
                    mm[3:0] <= mm[3:0] + 1'b1;
                end
            end else if (ss[3:0] == 4'h9) begin
                ss <= {ss[7:4] + 1'b1, 4'h0};
            end else begin
                ss[3:0] <= ss[3:0] + 1'b1;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] hh_ones, hh_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] ss_ones, ss_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
        end else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'd1;
                            end else begin
                                hh_ones <= hh_ones + 1'd1;
                            end
                        end else begin
                            mm_tens <= mm_tens + 1'd1;
                        end
                    end else begin
                        mm_ones <= mm_ones + 1'd1;
                    end
                end else begin
                    ss_tens <= ss_tens + 1'd1;
                end
            end else begin
                ss_ones <= ss_ones + 1'd1;
            end
        end
    end

    always @(*) begin
        hh = {hh_tens, hh_ones};
        mm = {mm_tens, mm_ones};
        ss = {ss_tens, ss_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh[7:4] <= hh[7:4] + 1'b1;
                                hh[3:0] <= 4'd0;
                            end
                            else begin
                                hh[3:0] <= hh[3:0] + 1'b1;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 1'b1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 1'b1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 1'b1;
                end
            end
            else begin
                ss_ones <= ss_ones + 1'b1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh <= {4'h1, 4'h0};
                            end
                            else begin
                                hh <= hh + 8'h01;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 4'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 4'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 4'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 4'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            pm <= 1'b0;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end
                            else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'b1;
                            end
                            else begin
                                hh_ones <= hh_ones + 1'b1;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 1'b1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 1'b1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 1'b1;
                end
            end
            else begin
                ss_ones <= ss_ones + 1'b1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh <= {4'h1, 4'h0};
                            end
                            else begin
                                hh[3:0] <= hh[3:0] + 1'd1;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 1'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 1'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 1'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 1'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh <= {4'h1, 4'h0};
                            end
                            else begin
                                hh[3:0] <= hh[3:0] + 1'd1;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 1'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 1'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 1'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 1'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            pm <= 1'b0;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end
                            else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'd1;
                            end
                            else begin
                                hh_ones <= hh_ones + 1'd1;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 1'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 1'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 1'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 1'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            pm <= 1'b0;
        end else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'b1;
                            end else begin
                                hh_ones <= hh_ones + 1'b1;
                            end
                        end else begin
                            mm_tens <= mm_tens + 1'b1;
                        end
                    end else begin
                        mm_ones <= mm_ones + 1'b1;
                    end
                end else begin
                    ss_tens <= ss_tens + 1'b1;
                end
            end else begin
                ss_ones <= ss_ones + 1'b1;
            end
        end
    end

    always @* begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
        end else if (ena) begin
            if (ss == 8'h59) begin
                ss <= 8'h00;
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    if (hh == 8'h11) begin
                        hh <= 8'h12;
                        pm <= ~pm;
                    end else if (hh == 8'h12) begin
                        hh <= 8'h01;
                    end else begin
                        hh <= hh + 8'h01;
                    end
                end else begin
                    mm <= (mm[3:0] == 4'h9) ? {mm[7:4] + 4'h1, 4'h0} : {mm[7:4], mm[3:0] + 4'h1};
                end
            end else begin
                ss <= (ss[3:0] == 4'h9) ? {ss[7:4] + 4'h1, 4'h0} : {ss[7:4], ss[3:0] + 4'h1};
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'h0;
            ss_tens <= 4'h0;
            mm_ones <= 4'h0;
            mm_tens <= 4'h0;
            hh_ones <= 4'h2;
            hh_tens <= 4'h1;
        end
        else if (ena) begin
            if (ss_ones == 4'h9) begin
                ss_ones <= 4'h0;
                if (ss_tens == 4'h5) begin
                    ss_tens <= 4'h0;
                    if (mm_ones == 4'h9) begin
                        mm_ones <= 4'h0;
                        if (mm_tens == 4'h5) begin
                            mm_tens <= 4'h0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'h9) begin
                                hh <= {4'h1, 4'h0};
                            end
                            else begin
                                hh <= hh + 8'h01;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 4'h1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 4'h1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 4'h1;
                end
            end
            else begin
                ss_ones <= ss_ones + 4'h1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

    reg [3:0] ss_ones, ss_tens;
    reg [3:0] mm_ones, mm_tens;
    reg [3:0] hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            pm <= 1'b0;
        end else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'b1;
                            end else begin
                                hh_ones <= hh_ones + 1'b1;
                            end
                        end else begin
                            mm_tens <= mm_tens + 1'b1;
                        end
                    end else begin
                        mm_ones <= mm_ones + 1'b1;
                    end
                end else begin
                    ss_tens <= ss_tens + 1'b1;
                end
            end else begin
                ss_ones <= ss_ones + 1'b1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    reg [3:0] hh_ones, hh_tens, mm_ones, mm_tens, ss_ones, ss_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
        end else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh_ones == 4'd2 && hh_tens == 4'd1) begin
                                hh_ones <= 4'd1;
                                hh_tens <= 4'd0;
                                pm <= ~pm;
                            end else if (hh_ones == 4'd9) begin
                                hh_ones <= 4'd0;
                                hh_tens <= hh_tens + 1'd1;
                            end else begin
                                hh_ones <= hh_ones + 1'd1;
                            end
                        end else begin
                            mm_tens <= mm_tens + 1'd1;
                        end
                    end else begin
                        mm_ones <= mm_ones + 1'd1;
                    end
                end else begin
                    ss_tens <= ss_tens + 1'd1;
                end
            end else begin
                ss_ones <= ss_ones + 1'd1;
            end
        end
    end

    always @(*) begin
        hh = {hh_tens, hh_ones};
        mm = {mm_tens, mm_ones};
        ss = {ss_tens, ss_ones};
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    reg [3:0] ss_ones, ss_tens, mm_ones, mm_tens, hh_ones, hh_tens;

    always @(posedge clk) begin
        if (reset) begin
            pm <= 0;
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            ss_ones <= 4'd0;
            ss_tens <= 4'd0;
            mm_ones <= 4'd0;
            mm_tens <= 4'd0;
            hh_ones <= 4'd2;
            hh_tens <= 4'd1;
        end
        else if (ena) begin
            if (ss_ones == 4'd9) begin
                ss_ones <= 4'd0;
                if (ss_tens == 4'd5) begin
                    ss_tens <= 4'd0;
                    if (mm_ones == 4'd9) begin
                        mm_ones <= 4'd0;
                        if (mm_tens == 4'd5) begin
                            mm_tens <= 4'd0;
                            if (hh == 8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end
                            else if (hh == 8'h12) begin
                                hh <= 8'h01;
                            end
                            else if (hh[3:0] == 4'd9) begin
                                hh <= {hh[7:4] + 4'd1, 4'd0};
                            end
                            else begin
                                hh <= hh + 8'h01;
                            end
                        end
                        else begin
                            mm_tens <= mm_tens + 4'd1;
                        end
                    end
                    else begin
                        mm_ones <= mm_ones + 4'd1;
                    end
                end
                else begin
                    ss_tens <= ss_tens + 4'd1;
                end
            end
            else begin
                ss_ones <= ss_ones + 4'd1;
            end
        end
    end

    always @(*) begin
        ss = {ss_tens, ss_ones};
        mm = {mm_tens, mm_ones};
        hh = {hh_tens, hh_ones};
    end

endmodule


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

	localparam LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
	reg [1:0] state, next_state;

	always @(posedge clk or posedge areset) begin
		if (areset)
			state <= LEFT;
		else
			state <= next_state;
	end

	always @(*) begin
		case (state)
			LEFT:
				if (!ground)
					next_state = FALL_LEFT;
				else if (bump_left)
					next_state = RIGHT;
				else
					next_state = LEFT;
			RIGHT:
				if (!ground)
					next_state = FALL_RIGHT;
				else if (bump_right)
					next_state = LEFT;
				else
					next_state = RIGHT;
			FALL_LEFT:
				if (ground)
					next_state = LEFT;
				else
					next_state = FALL_LEFT;
			FALL_RIGHT:
				if (ground)
					next_state = RIGHT;
				else
					next_state = FALL_RIGHT;
			default: next_state = LEFT;
		endcase
	end

	always @(*) begin
		walk_left = (state == LEFT);
		walk_right = (state == RIGHT);
		aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
	end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output walk_left,
	output walk_right,
	output aaah
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT:
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            RIGHT:
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            FALL_LEFT:
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            FALL_RIGHT:
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            default: next_state = LEFT;
        endcase
    end

    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT:
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            RIGHT:
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            FALL_LEFT:
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            FALL_RIGHT:
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output walk_left,
	output walk_right,
	output aaah
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end
            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            default: next_state = LEFT;
        endcase
    end

    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT:
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            RIGHT:
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            FALL_LEFT:
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            FALL_RIGHT:
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    localparam LEFT = 2'b00;
    localparam RIGHT = 2'b01;
    localparam FALL_LEFT = 2'b10;
    localparam FALL_RIGHT = 2'b11;

    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT:
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            RIGHT:
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            FALL_LEFT:
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            FALL_RIGHT:
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    localparam LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end
            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    parameter WALK_LEFT = 2'b00;
    parameter WALK_RIGHT = 2'b01;
    parameter FALL_LEFT = 2'b10;
    parameter FALL_RIGHT = 2'b11;

    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            default: next_state = WALK_LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end
            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

    parameter LEFT = 2'b00, RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end
            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            default: next_state = LEFT;
        endcase
    end

    always @(*) begin
        walk_left = (state == LEFT);
        walk_right = (state == RIGHT);
        aaah = (state == FALL_LEFT || state == FALL_RIGHT);
    end

endmodule


module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q
);

    reg [3:0] digit0, digit1, digit2, digit3;

    always @(posedge clk) begin
        if (reset) begin
            digit0 <= 4'd0;
            digit1 <= 4'd0;
            digit2 <= 4'd0;
            digit3 <= 4'd0;
        end else begin
            if (digit0 == 4'd9) begin
                digit0 <= 4'd0;
                if (digit1 == 4'd9) begin
                    digit1 <= 4'd0;
                    if (digit2 == 4'd9) begin
                        digit2 <= 4'd0;
                        if (digit3 == 4'd9) begin
                            digit3 <= 4'd0;
                        end else begin
                            digit3 <= digit3 + 1;
                        end
                    end else begin
                        digit2 <= digit2 + 1;
                    end
                end else begin
                    digit1 <= digit1 + 1;
                end
            end else begin
                digit0 <= digit0 + 1;
            end
        end
    end

    assign ena[1] = (digit0 == 4'd9);
    assign ena[2] = (digit0 == 4'd9) && (digit1 == 4'd9);
    assign ena[3] = (digit0 == 4'd9) && (digit1 == 4'd9) && (digit2 == 4'd9);

    always @(*) begin
        q = {digit3, digit2, digit1, digit0};
    end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] ena_internal;

    always @(posedge clk) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (ena_internal[0]) begin
                if (q[3:0] == 4'd9) q[3:0] <= 4'd0;
                else q[3:0] <= q[3:0] + 1'd1;
            end
            if (ena_internal[1]) begin
                if (q[7:4] == 4'd9) q[7:4] <= 4'd0;
                else q[7:4] <= q[7:4] + 1'd1;
            end
            if (ena_internal[2]) begin
                if (q[11:8] == 4'd9) q[11:8] <= 4'd0;
                else q[11:8] <= q[11:8] + 1'd1;
            end
            if (ena_internal[3]) begin
                if (q[15:12] == 4'd9) q[15:12] <= 4'd0;
                else q[15:12] <= q[15:12] + 1'd1;
            end
        end
    end

    assign ena_internal[0] = 1'b1;
    assign ena_internal[1] = (q[3:0] == 4'd9);
    assign ena_internal[2] = (q[7:4] == 4'd9) & ena_internal[1];
    assign ena_internal[3] = (q[11:8] == 4'd9) & ena_internal[2];

    assign ena = ena_internal[3:1];

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] digit_ena;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (digit_ena[0]) q[3:0] <= (q[3:0] == 4'd9) ? 4'd0 : q[3:0] + 1'd1;
            if (digit_ena[1]) q[7:4] <= (q[7:4] == 4'd9) ? 4'd0 : q[7:4] + 1'd1;
            if (digit_ena[2]) q[11:8] <= (q[11:8] == 4'd9) ? 4'd0 : q[11:8] + 1'd1;
            if (digit_ena[3]) q[15:12] <= (q[15:12] == 4'd9) ? 4'd0 : q[15:12] + 1'd1;
        end
    end

    assign digit_ena[0] = 1'b1;
    assign digit_ena[1] = (q[3:0] == 4'd9);
    assign digit_ena[2] = (q[7:4] == 4'd9) & digit_ena[1];
    assign digit_ena[3] = (q[11:8] == 4'd9) & digit_ena[2];

    assign ena = digit_ena[3:1];

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q
);

    wire [3:0] digit_ena;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (digit_ena[0]) q[3:0] <= (q[3:0] == 4'd9) ? 4'd0 : q[3:0] + 1'd1;
            if (digit_ena[1]) q[7:4] <= (q[7:4] == 4'd9) ? 4'd0 : q[7:4] + 1'd1;
            if (digit_ena[2]) q[11:8] <= (q[11:8] == 4'd9) ? 4'd0 : q[11:8] + 1'd1;
            if (digit_ena[3]) q[15:12] <= (q[15:12] == 4'd9) ? 4'd0 : q[15:12] + 1'd1;
        end
    end

    assign digit_ena[0] = 1'b1;
    assign digit_ena[1] = (q[3:0] == 4'd9);
    assign digit_ena[2] = (q[7:4] == 4'd9) & digit_ena[1];
    assign digit_ena[3] = (q[11:8] == 4'd9) & digit_ena[2];

    assign ena = digit_ena[3:1];

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] digit_ena;

    // Enable signals for each digit
    assign digit_ena[0] = 1'b1; // Ones digit always enabled
    assign digit_ena[1] = (q[3:0] == 4'd9);
    assign digit_ena[2] = (q[7:4] == 4'd9) & digit_ena[1];
    assign digit_ena[3] = (q[11:8] == 4'd9) & digit_ena[2];

    assign ena = digit_ena[3:1];

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            // Ones digit
            if (q[3:0] == 4'd9) begin
                q[3:0] <= 4'd0;
            end else begin
                q[3:0] <= q[3:0] + 1'b1;
            end

            // Tens digit
            if (digit_ena[1]) begin
                if (q[7:4] == 4'd9) begin
                    q[7:4] <= 4'd0;
                end else begin
                    q[7:4] <= q[7:4] + 1'b1;
                end
            end

            // Hundreds digit
            if (digit_ena[2]) begin
                if (q[11:8] == 4'd9) begin
                    q[11:8] <= 4'd0;
                end else begin
                    q[11:8] <= q[11:8] + 1'b1;
                end
            end

            // Thousands digit
            if (digit_ena[3]) begin
                if (q[15:12] == 4'd9) begin
                    q[15:12] <= 4'd0;
                end else begin
                    q[15:12] <= q[15:12] + 1'b1;
                end
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] digit_ena;

    // Enable signals for each digit
    assign digit_ena[0] = 1'b1;
    assign digit_ena[1] = (q[3:0] == 4'd9);
    assign digit_ena[2] = (q[7:4] == 4'd9) & digit_ena[1];
    assign digit_ena[3] = (q[11:8] == 4'd9) & digit_ena[2];

    assign ena = digit_ena[3:1];

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            // Ones digit
            if (digit_ena[0]) begin
                if (q[3:0] == 4'd9)
                    q[3:0] <= 4'd0;
                else
                    q[3:0] <= q[3:0] + 1'b1;
            end

            // Tens digit
            if (digit_ena[1]) begin
                if (q[7:4] == 4'd9)
                    q[7:4] <= 4'd0;
                else
                    q[7:4] <= q[7:4] + 1'b1;
            end

            // Hundreds digit
            if (digit_ena[2]) begin
                if (q[11:8] == 4'd9)
                    q[11:8] <= 4'd0;
                else
                    q[11:8] <= q[11:8] + 1'b1;
            end

            // Thousands digit
            if (digit_ena[3]) begin
                if (q[15:12] == 4'd9)
                    q[15:12] <= 4'd0;
                else
                    q[15:12] <= q[15:12] + 1'b1;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] ena_internal;

    always @(posedge clk) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (ena_internal[0]) q[3:0] <= (q[3:0] == 4'd9) ? 4'd0 : q[3:0] + 1'd1;
            if (ena_internal[1]) q[7:4] <= (q[7:4] == 4'd9) ? 4'd0 : q[7:4] + 1'd1;
            if (ena_internal[2]) q[11:8] <= (q[11:8] == 4'd9) ? 4'd0 : q[11:8] + 1'd1;
            if (ena_internal[3]) q[15:12] <= (q[15:12] == 4'd9) ? 4'd0 : q[15:12] + 1'd1;
        end
    end

    assign ena_internal[0] = 1'b1;
    assign ena_internal[1] = (q[3:0] == 4'd9);
    assign ena_internal[2] = (q[7:4] == 4'd9) & ena_internal[1];
    assign ena_internal[3] = (q[11:8] == 4'd9) & ena_internal[2];

    assign ena = ena_internal[3:1];

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

    wire [3:0] digit_ena;

    // Generate enable signals
    assign digit_ena[0] = 1'b1; // Ones digit always increments
    assign digit_ena[1] = (q[3:0] == 4'd9);
    assign digit_ena[2] = (q[7:4] == 4'd9) & digit_ena[1];
    assign digit_ena[3] = (q[11:8] == 4'd9) & digit_ena[2];

    assign ena = digit_ena[3:1];

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            // Ones digit
            if (digit_ena[0]) begin
                if (q[3:0] == 4'd9)
                    q[3:0] <= 4'd0;
                else
                    q[3:0] <= q[3:0] + 1'b1;
            end

            // Tens digit
            if (digit_ena[1]) begin
                if (q[7:4] == 4'd9)
                    q[7:4] <= 4'd0;
                else
                    q[7:4] <= q[7:4] + 1'b1;
            end

            // Hundreds digit
            if (digit_ena[2]) begin
                if (q[11:8] == 4'd9)
                    q[11:8] <= 4'd0;
                else
                    q[11:8] <= q[11:8] + 1'b1;
            end

            // Thousands digit
            if (digit_ena[3]) begin
                if (q[15:12] == 4'd9)
                    q[15:12] <= 4'd0;
                else
                    q[15:12] <= q[15:12] + 1'b1;
            end
        end
    end

endmodule