module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State definitions
    typedef enum reg [2:0] {
        IDLE = 3'd0,
        S1 = 3'd1,
        S11 = 3'd2,
        S110 = 3'd3,
        S1101 = 3'd4,
        SHIFTING = 3'd5,
        WAIT_COUNT = 3'd6,
        DONE = 3'd7
    } state_t;

    state_t current_state, next_state;
    reg [1:0] shift_count;

    // State transition logic (combinational)
    always @(*) begin
        next_state = current_state;
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (data == 1) next_state = S1;
            end
            S1: begin
                if (data == 1) next_state = S11;
                else next_state = IDLE;
            end
            S11: begin
                if (data == 0) next_state = S110;
                else if (data == 1) next_state = S1;
                else next_state = IDLE;
            end
            S110: begin
                if (data == 1) next_state = S1101;
                else if (data == 0) next_state = IDLE;
                else next_state = S11;
            end
            S1101: begin
                next_state = SHIFTING;
            end
            SHIFTING: begin
                shift_ena = 1'b1;
                if (shift_count == 2'd3) next_state = WAIT_COUNT;
            end
            WAIT_COUNT: begin
                counting = 1'b1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1'b1;
                if (ack) next_state = IDLE;
            end
            default: next_state = IDLE;
        endcase
    end

    // State register (sequential)
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            shift_count <= 2'd0;
        end
        else begin
            current_state <= next_state;
            if (current_state == SHIFTING)
                shift_count <= shift_count + 1;
            else
                shift_count <= 2'd0;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    typedef enum logic [2:0] {
        S_WAIT_PATTERN = 3'b000,
        S_SHIFT_4BITS  = 3'b001,
        S_WAIT_COUNT   = 3'b010,
        S_DONE         = 3'b011
    } state_t;

    state_t state, next_state;
    reg [3:0] pattern_shift_reg;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= S_WAIT_PATTERN;
            pattern_shift_reg <= 4'b0000;
        end else begin
            state <= next_state;

            if (state == S_WAIT_PATTERN)
                pattern_shift_reg <= {pattern_shift_reg[2:0], data};
        end
    end

    always_comb begin
        // Default signal values
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (state)
            S_WAIT_PATTERN: begin
                if (pattern_shift_reg == 4'b1101)
                    next_state = S_SHIFT_4BITS;
                else
                    next_state = S_WAIT_PATTERN;
            end

            S_SHIFT_4BITS: begin
                shift_ena = 1'b1;
                if (pattern_shift_reg == 4'b0000)  // All bits shifted after 4 cycles
                    next_state = S_WAIT_COUNT;
                else
                    next_state = S_SHIFT_4BITS;
            end

            S_WAIT_COUNT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = S_DONE;
                else
                    next_state = S_WAIT_COUNT;
            end

            S_DONE: begin
                done = 1'b1;
                if (ack)
                    next_state = S_WAIT_PATTERN;
                else
                    next_state = S_DONE;
            end

            default: next_state = S_WAIT_PATTERN;
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State encoding
    typedef enum reg [2:0] {
        STATE_IDLE,
        STATE_PATTERN_DETECT,
        STATE_SHIFT,
        STATE_COUNTING,
        STATE_DONE
    } state_t;

    state_t state, next_state;
    reg [3:0] pattern_register;

    // State transition logic
    always @(*) begin
        next_state = state; // Default: remain in the same state
        shift_ena = 0;
        counting = 0;
        done = 0;
        case (state)
            STATE_IDLE: begin
                if (pattern_register == 4'b1101) begin
                    next_state = STATE_SHIFT;
                end else begin
                    next_state = STATE_PATTERN_DETECT;
                end
            end

            STATE_PATTERN_DETECT: begin
                if (pattern_register == 4'b1101) begin
                    next_state = STATE_SHIFT;
                end
            end

            STATE_SHIFT: begin
                shift_ena = 1;
                if (pattern_register == 4'b0000) begin // Assuming 4 cycles are enough
                    next_state = STATE_COUNTING;
                end
            end

            STATE_COUNTING: begin
                counting = 1;
                if (done_counting) begin
                    next_state = STATE_DONE;
                end
            end

            STATE_DONE: begin
                done = 1;
                if (ack) begin
                    next_state = STATE_IDLE;
                end
            end

            default: begin
                next_state = STATE_IDLE;
            end
        endcase
    end

    // State flip-flops
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= STATE_IDLE;
            pattern_register <= 4'b0000;
        end else begin
            state <= next_state;
            if (state == STATE_IDLE || state == STATE_PATTERN_DETECT) begin
                pattern_register <= {pattern_register[2:0], data};
            end else if (state == STATE_SHIFT) begin
                pattern_register <= pattern_register - 1'b1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
    );

    typedef enum reg [2:0] {
        IDLE,
        PATTERN_DET_1,
        PATTERN_DET_11,
        PATTERN_DET_110,
        PATTERN_DET_1101,
        SHIFT,
        COUNT,
        DONE
    } state_t;

    state_t current_state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            shift_count <= 3'd0;
        end else begin
            current_state <= next_state;
            if (shift_ena)
                shift_count <= shift_count + 1;
            else
                shift_count <= 3'd0;
        end
    end

    always @(*) begin
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (current_state)
            IDLE: begin
                if (data)
                    next_state = PATTERN_DET_1;
                else
                    next_state = IDLE;
            end

            PATTERN_DET_1: begin
                if (data)
                    next_state = PATTERN_DET_11;
                else
                    next_state = IDLE;
            end

            PATTERN_DET_11: begin
                if (!data)
                    next_state = PATTERN_DET_110;
                else
                    next_state = IDLE;
            end

            PATTERN_DET_110: begin
                if (data)
                    next_state = PATTERN_DET_1101;
                else
                    next_state = IDLE;
            end

            PATTERN_DET_1101: begin
                shift_ena = 1;
                next_state = SHIFT;
            end

            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3'd3)
                    next_state = COUNT;
                else
                    next_state = SHIFT;
            end

            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
                else
                    next_state = COUNT;
            end

            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
                else
                    next_state = DONE;
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State encoding
    typedef enum reg [3:0] {
        IDLE = 4'b0000,
        DETECT1 = 4'b0001,
        DETECT11 = 4'b0010,
        DETECT110 = 4'b0011,
        DETECT1101 = 4'b0100,
        SHIFT = 4'b0101,
        COUNT = 4'b0110,
        DONE = 4'b0111
    } state_type;

    state_type state, next_state;

    // State transitions
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic and output logic
    always @(*) begin
        // Default values
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: begin
                if (data)
                    next_state = DETECT1;
                else
                    next_state = IDLE;
            end
            DETECT1: begin
                if (data)
                    next_state = DETECT11;
                else
                    next_state = IDLE;
            end
            DETECT11: begin
                if (~data)
                    next_state = DETECT110;
                else
                    next_state = DETECT1;
            end
            DETECT110: begin
                if (data)
                    next_state = DETECT1101;
                else
                    next_state = IDLE;
            end
            DETECT1101: begin
                shift_ena = 1;
                next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1;
                if (&{shift_ena, shift_ena, shift_ena, shift_ena}) // Assume counting happens after 4 cycles
                    next_state = COUNT;
                else
                    next_state = SHIFT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
                else
                    next_state = COUNT;
            end
            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
                else
                    next_state = DONE;
            end
            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    // State Definitions
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        PATTERN_DETECTED = 3'b001,
        SHIFT_ENABLE = 3'b010,
        COUNT_WAIT = 3'b011,
        DONE_WAIT = 3'b100
    } state_type;

    state_type current_state, next_state;
    reg [2:0] bit_counter;

    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    always @(*) begin
        // Default outputs
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;
        next_state = current_state;

        case (current_state)
            IDLE: begin
                if (data == 1)
                    next_state = PATTERN_DETECTED;
            end

            PATTERN_DETECTED: begin
                if (data == 1)
                    next_state = SHIFT_ENABLE;
                else
                    next_state = IDLE;
            end

            SHIFT_ENABLE: begin
                shift_ena = 1'b1;
                if (bit_counter == 3'b100)
                    next_state = COUNT_WAIT;
            end

            COUNT_WAIT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE_WAIT;
            end

            DONE_WAIT: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            bit_counter <= 3'b000;
        else if (current_state == SHIFT_ENABLE)
            bit_counter <= bit_counter + 1;
        else
            bit_counter <= 3'b000;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    // State Declaration
    typedef enum reg [2:0] {
        S_IDLE,        // Waiting for 1101
        S_DETECT_1,    // Detected '1'
        S_DETECT_11,   // Detected '11'
        S_DETECT_110,  // Detected '110'
        S_SHIFT,       // Shift in 4 bits for delay duration
        S_COUNT,       // Wait for counting to finish
        S_DONE         // Notify user timer has timed out
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= S_IDLE;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        // Default values
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            S_IDLE: begin
                if (data == 1'b1)
                    next_state = S_DETECT_1;
            end
            S_DETECT_1: begin
                if (data == 1'b1)
                    next_state = S_DETECT_11;
                else
                    next_state = S_IDLE;
            end
            S_DETECT_11: begin
                if (data == 1'b0)
                    next_state = S_DETECT_110;
                else
                    next_state = S_IDLE;
            end
            S_DETECT_110: begin
                if (data == 1'b1)
                    next_state = S_SHIFT;
                else
                    next_state = S_IDLE;
            end
            S_SHIFT: begin
                shift_ena = 1;
                if (shift_ena == 4)  // After 4 clock cycles
                    next_state = S_COUNT;
            end
            S_COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = S_DONE;
            end
            S_DONE: begin
                done = 1;
                if (ack)
                    next_state = S_IDLE;
            end
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State encoding
    typedef enum reg [2:0] {
        IDLE        = 3'b000,
        DETECT_1    = 3'b001,
        DETECT_11   = 3'b010,
        DETECT_110  = 3'b011,
        DETECT_1101 = 3'b100,
        SHIFT       = 3'b101,
        COUNT       = 3'b110,
        DONE        = 3'b111
    } state_t;

    state_t state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(posedge clk) begin
        if (reset)
            shift_count <= 3'd0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1'b1;
        else
            shift_count <= 3'd0;
    end

    always @(*) begin
        // Default outputs
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;
        next_state = state;

        case (state)
            IDLE: begin
                if (data)
                    next_state = DETECT_1;
            end
            DETECT_1: begin
                if (data)
                    next_state = DETECT_11;
                else
                    next_state = IDLE;
            end
            DETECT_11: begin
                if (~data)
                    next_state = DETECT_110;
                else
                    next_state = IDLE;
            end
            DETECT_110: begin
                if (data)
                    next_state = DETECT_1101;
                else
                    next_state = IDLE;
            end
            DETECT_1101: begin
                shift_ena = 1'b1;
                next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1'b1;
                if (shift_count == 3'd3)
                    next_state = COUNT;
            end
            COUNT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE;
            end
            DONE: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State declarations
    typedef enum reg [2:0] {
        IDLE,
        DETECT_1,
        DETECT_11,
        DETECT_110,
        DETECT_1101,
        SHIFT,
        COUNT,
        DONE
    } state_t;

    state_t state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    always @* begin
        // Default outputs
        shift_ena = 0;
        counting = 0;
        done = 0;
        next_state = state;

        case (state)
            IDLE: begin
                if (data == 1) next_state = DETECT_1;
            end

            DETECT_1: begin
                if (data == 1) next_state = DETECT_11;
                else next_state = IDLE;
            end

            DETECT_11: begin
                if (data == 0) next_state = DETECT_110;
                else next_state = IDLE;
            end

            DETECT_110: begin
                if (data == 1) next_state = DETECT_1101;
                else next_state = IDLE;
            end

            DETECT_1101: begin
                shift_ena = 1;
                next_state = SHIFT;
                shift_count = 4;
            end

            SHIFT: begin
                shift_ena = 1;
                if (shift_count > 0)
                    shift_count = shift_count - 1;
                else
                    next_state = COUNT;
            end

            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
            end

            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
            end

            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        SHIFT = 3'b001,
        COUNT_WAIT = 3'b010,
        DONE_NOTIFY = 3'b011
    } state_t;

    state_t state, next_state;
    reg [3:0] pattern_shift;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            pattern_shift <= 4'b0000;
        end else begin
            state <= next_state;
            if (shift_ena)
                pattern_shift <= {pattern_shift[2:0], data};
        end
    end

    always_comb begin
        // Default assignments
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;
        next_state = state;

        case (state)
            IDLE: begin
                if (pattern_shift == 4'b1101)
                    next_state = SHIFT;
                else
                    next_state = IDLE;
                shift_ena = 1'b1;
            end

            SHIFT: begin
                shift_ena = 1'b1;
                next_state = (pattern_shift == 4'b1111) ? COUNT_WAIT : SHIFT;
            end

            COUNT_WAIT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE_NOTIFY;
            end

            DONE_NOTIFY: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
            end

            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    typedef enum reg [2:0] {
        IDLE,
        CHECK_1,
        CHECK_11,
        CHECK_110,
        CHECK_1101,
        SHIFT,
        WAIT_COUNT,
        DONE,
        WAIT_ACK
    } state_t;

    state_t state, next_state;
    reg [1:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: begin
                if (data)
                    next_state = CHECK_1;
                else
                    next_state = IDLE;
            end
            CHECK_1: begin
                if (data)
                    next_state = CHECK_11;
                else
                    next_state = IDLE;
            end
            CHECK_11: begin
                if (~data)
                    next_state = CHECK_110;
                else
                    next_state = CHECK_1;
            end
            CHECK_110: begin
                if (data)
                    next_state = CHECK_1101;
                else
                    next_state = IDLE;
            end
            CHECK_1101: begin
                if (data)
                    next_state = CHECK_11;
                else begin
                    shift_ena = 1;
                    next_state = SHIFT;
                end
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 3)
                    next_state = WAIT_COUNT;
                else
                    next_state = SHIFT;
            end
            WAIT_COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
                else
                    next_state = WAIT_COUNT;
            end
            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
                else
                    next_state = DONE;
            end
            default: next_state = IDLE;
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    typedef enum reg [2:0] {
        IDLE,     // Waiting for the pattern 1101
        PAT_DET1, // Pattern detection state 1
        PAT_DET2, // Pattern detection state 2
        PAT_DET3, // Pattern detection state 3
        PAT_DET4, // Pattern detection state 4, i.e., pattern match complete
        SHIFT,    // Shift in the 4 bits to determine delay
        WAIT_CNT, // Wait for the counters to finish counting
        DONE      // Notify user that time has timed out
    } state_t;

    state_t current_state, next_state;
    reg [2:0] shift_count;

    // Sequential logic: State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            shift_count <= 3'd0;
        end else begin
            current_state <= next_state;
            if (current_state == SHIFT)
                shift_count <= shift_count + 1;
            else
                shift_count <= 3'd0;
        end
    end

    // Combinational logic: Next state logic and output logic
    always @(*) begin
        // Default outputs
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (data == 1'b1) next_state = PAT_DET1;
                else next_state = IDLE;
            end
            PAT_DET1: begin
                if (data == 1'b1) next_state = PAT_DET2;
                else next_state = IDLE;
            end
            PAT_DET2: begin
                if (data == 1'b0) next_state = PAT_DET3;
                else next_state = PAT_DET1;
            end
            PAT_DET3: begin
                if (data == 1'b1) next_state = PAT_DET4;
                else next_state = IDLE;
            end
            PAT_DET4: begin
                next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1'b1;
                if (shift_count == 3'd3)
                    next_state = WAIT_CNT;
                else
                    next_state = SHIFT;
            end
            WAIT_CNT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE;
                else
                    next_state = WAIT_CNT;
            end
            DONE: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
                else
                    next_state = DONE;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State encoding
    typedef enum reg [2:0] {
        IDLE          = 3'b000,
        PATTERN_MATCH = 3'b001,
        SHIFT_ENA     = 3'b010,
        COUNT         = 3'b011,
        DONE          = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [3:0] pattern_shift;

    // State register
    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        // Default assignments
        next_state = current_state;
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (pattern_shift == 4'b1101)
                    next_state = PATTERN_MATCH;
            end
            PATTERN_MATCH: begin
                next_state = SHIFT_ENA;
            end
            SHIFT_ENA: begin
                shift_ena = 1'b1;
                if (pattern_shift[3:0] == 4'b0000) // After 4 shifts
                    next_state = COUNT;
            end
            COUNT: begin
                counting = 1'b1;
                if (done_counting)
                    next_state = DONE;
            end
            DONE: begin
                done = 1'b1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    // Shift register for pattern matching and shift count
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            pattern_shift <= 4'b0000;
        end else begin
            if (current_state == IDLE || current_state == SHIFT_ENA)
                pattern_shift <= {pattern_shift[2:0], data};
            else
                pattern_shift <= 4'b0000;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    // Define states
    typedef enum reg [2:0] {
        IDLE      = 3'b000,
        PATTERN_1 = 3'b001,
        PATTERN_2 = 3'b010,
        PATTERN_3 = 3'b011,
        PATTERN_4 = 3'b100,
        SHIFT     = 3'b101,
        COUNT     = 3'b110,
        DONE      = 3'b111
    } state_t;

    state_t current_state, next_state;
    reg [2:0] shift_count;

    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    always @(*) begin
        // Default outputs
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (data == 1'b1) next_state = PATTERN_1;
                else next_state = IDLE;
            end
            PATTERN_1: begin
                if (data == 1'b1) next_state = PATTERN_2;
                else next_state = IDLE;
            end
            PATTERN_2: begin
                if (data == 1'b0) next_state = PATTERN_3;
                else next_state = IDLE;
            end
            PATTERN_3: begin
                if (data == 1'b1) next_state = PATTERN_4;
                else next_state = IDLE;
            end
            PATTERN_4: begin
                next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1'b1;
                if (shift_count == 3'h3) next_state = COUNT; // After 4 cycles (0 to 3)
                else next_state = SHIFT;
            end
            COUNT: begin
                counting = 1'b1;
                if (done_counting) next_state = DONE;
                else next_state = COUNT;
            end
            DONE: begin
                done = 1'b1;
                if (ack) next_state = IDLE;
                else next_state = DONE;
            end
            default: begin
                next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 3'h0;
        else if (current_state == SHIFT)
            shift_count <= shift_count + 1'b1;
        else
            shift_count <= 3'h0;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // Define states
    typedef enum reg [2:0] {
        IDLE,
        PATTERN_DETECT,
        SHIFT,
        WAIT_COUNTER,
        DONE_STATE
    } state_type;

    state_type state, next_state;
    reg [3:0] pattern_shift_reg;
    reg [1:0] shift_counter;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            pattern_shift_reg <= 4'b0000;
            shift_counter <= 2'b00;
            shift_ena <= 0;
            counting <= 0;
            done <= 0;
        end else begin
            state <= next_state;
            if (state == SHIFT) begin
                shift_counter <= shift_counter + 1;
            end
            if (state == PATTERN_DETECT) begin
                pattern_shift_reg <= {pattern_shift_reg[2:0], data};
            end
        end
    end

    always @(*) begin
        // Default values
        next_state = state;
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: begin
                if ({pattern_shift_reg[2:0], data} == 4'b1101)
                    next_state = PATTERN_DETECT;
            end
            PATTERN_DETECT: begin
                if ({pattern_shift_reg[2:0], data} == 4'b1101) begin
                    next_state = SHIFT;
                end else begin
                    next_state = IDLE;
                end
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_counter == 2'b11) begin
                    next_state = WAIT_COUNTER;
                end
            end
            WAIT_COUNTER: begin
                counting = 1;
                if (done_counting) begin
                    next_state = DONE_STATE;
                end
            end
            DONE_STATE: begin
                done = 1;
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        DETECT_1 = 3'b001,
        DETECT_11 = 3'b010,
        DETECT_110 = 3'b011,
        DETECT_1101 = 3'b100,
        SHIFT = 3'b101,
        COUNT = 3'b110,
        NOTIFY = 3'b111
    } state_t;

    state_t state, next_state;
    reg [1:0] shift_counter;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            shift_ena <= 0;
            counting <= 0;
            done <= 0;
            shift_counter <= 0;
        end else begin
            state <= next_state;

            case (state)
                IDLE: begin
                    shift_ena <= 0;
                    counting <= 0;
                    done <= 0;
                end
                DETECT_1101: begin
                    shift_ena <= 1;
                    shift_counter <= 2'b00;
                end
                SHIFT: begin
                    shift_ena <= 1;
                    shift_counter <= shift_counter + 1;
                    if (shift_counter == 2'b11) begin
                        shift_ena <= 0;
                    end
                end
                COUNT: begin
                    shift_ena <= 0;
                    counting <= 1;
                end
                NOTIFY: begin
                    counting <= 0;
                    done <= 1;
                end
                default: begin
                    shift_ena <= 0;
                    counting <= 0;
                    done <= 0;
                end
            endcase
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: begin
                if (data)
                    next_state = DETECT_1;
            end
            DETECT_1: begin
                if (data)
                    next_state = DETECT_11;
                else
                    next_state = IDLE;
            end
            DETECT_11: begin
                if (!data)
                    next_state = DETECT_110;
                else
                    next_state = DETECT_1;
            end
            DETECT_110: begin
                if (data)
                    next_state = DETECT_1101;
                else
                    next_state = IDLE;
            end
            DETECT_1101: begin
                next_state = SHIFT;
            end
            SHIFT: begin
                if (shift_counter == 2'b11)
                    next_state = COUNT;
            end
            COUNT: begin
                if (done_counting)
                    next_state = NOTIFY;
            end
            NOTIFY: begin
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
    );

    reg [2:0] state, next_state;
    reg [3:0] pattern_shifter;
    reg [1:0] bit_counter;

    localparam IDLE = 3'b000,
               PATTERN_DETECT = 3'b001,
               SHIFT_IN = 3'b010,
               COUNT_WAIT = 3'b011,
               DONE = 3'b100;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            pattern_shifter <= 4'b0000;
            bit_counter <= 2'b00;
        end else begin
            state <= next_state;
            if (state == PATTERN_DETECT) begin
                pattern_shifter <= {pattern_shifter[2:0], data};
            end
            if (state == SHIFT_IN) begin
                bit_counter <= bit_counter + 1;
            end else begin
                bit_counter <= 2'b00;
            end
        end
    end

    // Next state logic
    always @(*) begin
        shift_ena = 0;
        counting = 0;
        done = 0;
        next_state = state;

        case (state)
            IDLE: begin
                if (data == 1) begin
                    next_state = PATTERN_DETECT;
                    pattern_shifter = {pattern_shifter[2:0], data};
                end
            end
            PATTERN_DETECT: begin
                if (pattern_shifter == 4'b1101) begin
                    next_state = SHIFT_IN;
                end else begin
                    pattern_shifter = {pattern_shifter[2:0], data};
                end
            end
            SHIFT_IN: begin
                shift_ena = 1;
                if (bit_counter == 2'b11) begin // 4 bits shifted in
                    next_state = COUNT_WAIT;
                end
            end
            COUNT_WAIT: begin
                counting = 1;
                if (done_counting) begin
                    next_state = DONE;
                end
            end
            DONE: begin
                done = 1;
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State encoding
    typedef enum logic [2:0] {
        IDLE       = 3'b000,
        DETECT_1   = 3'b001,
        DETECT_11  = 3'b010,
        DETECT_110 = 3'b011,
        DETECT_1101 = 3'b100,
        SHIFT      = 3'b101,
        COUNT      = 3'b110,
        DONE       = 3'b111
    } state_t;

    state_t state, next_state;
    reg [1:0] shift_count;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next state and output logic
    always_comb begin
        // Default outputs
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: begin
                if (data)
                    next_state = DETECT_1;
                else
                    next_state = IDLE;
            end
            DETECT_1: begin
                if (data)
                    next_state = DETECT_11;
                else
                    next_state = IDLE;
            end
            DETECT_11: begin
                if (data)
                    next_state = DETECT_110;
                else
                    next_state = IDLE;
            end
            DETECT_110: begin
                if (data)
                    next_state = DETECT_1101;
                else
                    next_state = IDLE;
            end
            DETECT_1101: begin
                shift_ena = 1;
                next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_count == 2'd3)
                    next_state = COUNT;
                else
                    next_state = SHIFT;
            end
            COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
                else
                    next_state = COUNT;
            end
            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
                else
                    next_state = DONE;
            end
            default: next_state = IDLE;
        endcase
    end

    // Shift counter logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            shift_count <= 0;
        else if (state == SHIFT)
            shift_count <= shift_count + 1;
        else
            shift_count <= 0;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack
    );

    // State encoding
    parameter IDLE = 3'b000,
              DETECT1 = 3'b001,
              DETECT2 = 3'b010,
              DETECT3 = 3'b011,
              DETECT4 = 3'b100,
              SHIFT = 3'b101,
              WAIT_COUNT = 3'b110,
              DONE = 3'b111;

    reg [2:0] state, next_state;
    reg [1:0] shift_counter;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        next_state = state;  // Default state transition
        shift_ena = 0;
        counting = 0;
        done = 0;

        case (state)
            IDLE: begin
                if (data == 1'b1)
                    next_state = DETECT1;
            end
            DETECT1: begin
                if (data == 1'b1)
                    next_state = DETECT2;
                else
                    next_state = IDLE;
            end
            DETECT2: begin
                if (data == 1'b0)
                    next_state = DETECT3;
                else
                    next_state = IDLE;
            end
            DETECT3: begin
                if (data == 1'b1)
                    next_state = DETECT4;
                else
                    next_state = IDLE;
            end
            DETECT4: begin
                if (data == 1'b1)
                    next_state = DETECT1;
                else
                    next_state = SHIFT;
            end
            SHIFT: begin
                shift_ena = 1;
                if (shift_counter == 2'b11)
                    next_state = WAIT_COUNT;
            end
            WAIT_COUNT: begin
                counting = 1;
                if (done_counting)
                    next_state = DONE;
            end
            DONE: begin
                done = 1;
                if (ack)
                    next_state = IDLE;
            end
        endcase
    end

    // Shift counter logic during SHIFT state
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            shift_counter <= 2'b00;
        end else if (shift_ena) begin
            shift_counter <= shift_counter + 1;
        end else begin
            shift_counter <= 2'b00;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

    // State definitions
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        PATTERN_1 = 3'b001,
        PATTERN_2 = 3'b010,
        PATTERN_3 = 3'b011,
        PATTERN_4 = 3'b100,
        SHIFT = 3'b101,
        COUNT = 3'b110,
        DONE = 3'b111
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_counter;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        // Default values
        shift_ena = 1'b0;
        counting = 1'b0;
        done = 1'b0;
        next_state = state;

        case (state)
            IDLE: begin
                if (data) next_state = PATTERN_1;
            end
            PATTERN_1: begin
                if (~data) next_state = PATTERN_2;
                else next_state = PATTERN_1;
            end
            PATTERN_2: begin
                if (data) next_state = PATTERN_3;
                else next_state = IDLE;
            end
            PATTERN_3: begin
                if (data) next_state = PATTERN_4;
                else next_state = IDLE;
            end
            PATTERN_4: begin
                if (~data) next_state = SHIFT;
                else next_state = IDLE;
            end
            SHIFT: begin
                shift_ena = 1'b1;
                if (bit_counter == 3'b011) next_state = COUNT;
            end
            COUNT: begin
                counting = 1'b1;
                if (done_counting) next_state = DONE;
            end
            DONE: begin
                done = 1'b1;
                if (ack) next_state = IDLE;
            end
        endcase
    end

    // Bit counter logic
    always @(posedge clk or posedge reset) begin
        if (reset)
            bit_counter <= 3'b000;
        else if (state == SHIFT)
            bit_counter <= bit_counter + 1;
        else
            bit_counter <= 3'b000;
    end

endmodule