module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging
);

    // Define states
    typedef enum logic [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL_LEFT,
        STATE_FALL_RIGHT,
        STATE_DIG_LEFT,
        STATE_DIG_RIGHT
    } state_t;

    // State registers
    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                if (!ground)
                    next_state = STATE_FALL_LEFT;
                else if (dig)
                    next_state = STATE_DIG_LEFT;
                else if (bump_left || (bump_left && bump_right))
                    next_state = STATE_WALK_RIGHT;
                else
                    next_state = STATE_WALK_LEFT;
            end
            STATE_WALK_RIGHT: begin
                if (!ground)
                    next_state = STATE_FALL_RIGHT;
                else if (dig)
                    next_state = STATE_DIG_RIGHT;
                else if (bump_right || (bump_left && bump_right))
                    next_state = STATE_WALK_LEFT;
                else
                    next_state = STATE_WALK_RIGHT;
            end
            STATE_FALL_LEFT: begin
                if (ground)
                    next_state = STATE_WALK_LEFT;
                else
                    next_state = STATE_FALL_LEFT;
            end
            STATE_FALL_RIGHT: begin
                if (ground)
                    next_state = STATE_WALK_RIGHT;
                else
                    next_state = STATE_FALL_RIGHT;
            end
            STATE_DIG_LEFT: begin
                if (!ground)
                    next_state = STATE_FALL_LEFT;
                else
                    next_state = STATE_DIG_LEFT;
            end
            STATE_DIG_RIGHT: begin
                if (!ground)
                    next_state = STATE_FALL_RIGHT;
                else
                    next_state = STATE_DIG_RIGHT;
            end
            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

    // State update
    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= STATE_WALK_LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left = (state == STATE_WALK_LEFT);
    assign walk_right = (state == STATE_WALK_RIGHT);
    assign aaah = (state == STATE_FALL_LEFT) || (state == STATE_FALL_RIGHT);
    assign digging = (state == STATE_DIG_LEFT) || (state == STATE_DIG_RIGHT);

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALLING_LEFT,
        STATE_FALLING_RIGHT,
        STATE_DIGGING_LEFT,
        STATE_DIGGING_RIGHT
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALLING_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIGGING_LEFT;
                end else if (bump_left) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end
            STATE_WALK_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALLING_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIGGING_RIGHT;
                end else if (bump_right) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end
            STATE_FALLING_LEFT: begin
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_FALLING_LEFT;
                end
            end
            STATE_FALLING_RIGHT: begin
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_FALLING_RIGHT;
                end
            end
            STATE_DIGGING_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALLING_LEFT;
                end else begin
                    next_state = STATE_DIGGING_LEFT;
                end
            end
            STATE_DIGGING_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALLING_RIGHT;
                end else begin
                    next_state = STATE_DIGGING_RIGHT;
                end
            end
            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == STATE_WALK_LEFT);
        walk_right = (state == STATE_WALK_RIGHT);
        aaah = (state == STATE_FALLING_LEFT) || (state == STATE_FALLING_RIGHT);
        digging = (state == STATE_DIGGING_LEFT) || (state == STATE_DIGGING_RIGHT);
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging
);

    // State encoding
    typedef enum logic [2:0] {
        WALK_LEFT   = 3'b000,
        WALK_RIGHT  = 3'b001,
        FALL_LEFT   = 3'b010,
        FALL_RIGHT  = 3'b011,
        DIG_LEFT    = 3'b100,
        DIG_RIGHT   = 3'b101
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;  // Reset state
        else
            state <= next_state;
    end

    always_comb begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left || (bump_left && bump_right))
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end

            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right || (bump_left && bump_right))
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end

            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end

            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end

            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end

            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end

            default: next_state = WALK_LEFT;
        endcase
    end

    // Output logic: based on state
    assign walk_left = (state == WALK_LEFT);
    assign walk_right = (state == WALK_RIGHT);
    assign aaah = (state == FALL_LEFT || state == FALL_RIGHT);
    assign digging = (state == DIG_LEFT || state == DIG_RIGHT);

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // State encoding
    typedef enum reg [2:0] {
        WALK_LEFT    = 3'b000,
        WALK_RIGHT   = 3'b001,
        FALL_LEFT    = 3'b010,
        FALL_RIGHT   = 3'b011,
        DIG_LEFT     = 3'b100,
        DIG_RIGHT    = 3'b101
    } state_t;
    state_t state, next_state;

    always @(*) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else if (dig) begin
                    next_state = DIG_LEFT;
                end else if (bump_left || (bump_left && bump_right)) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else if (dig) begin
                    next_state = DIG_RIGHT;
                end else if (bump_right || (bump_left && bump_right)) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                end
            end

            FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = FALL_LEFT;
                end
            end

            FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = FALL_RIGHT;
                end
            end

            DIG_LEFT: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else begin
                    next_state = DIG_LEFT;
                end
            end

            DIG_RIGHT: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else begin
                    next_state = DIG_RIGHT;
                end
            end

            default: begin
                next_state = WALK_LEFT;
            end
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALL_LEFT,
        FALL_RIGHT,
        DIG_LEFT,
        DIG_RIGHT
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    always_comb begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left || bump_right)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end

            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_left || bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end

            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end

            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end

            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end

            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end

            default: next_state = WALK_LEFT;
        endcase
    end

    always_comb begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
        digging = (state == DIG_LEFT) || (state == DIG_RIGHT);
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // Define states
    typedef enum reg [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (ground == 0)
                    next_state = FALL_LEFT;
                else if (dig == 1)
                    next_state = DIG_LEFT;
                else if (bump_left || bump_right)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (ground == 0)
                    next_state = FALL_RIGHT;
                else if (dig == 1)
                    next_state = DIG_RIGHT;
                else if (bump_left || bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
            FALL_LEFT: begin
                if (ground == 1)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground == 1)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            DIG_LEFT: begin
                if (ground == 0)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end
            DIG_RIGHT: begin
                if (ground == 0)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end
            default:
                next_state = WALK_LEFT;
        endcase
    end

    // State flip-flops
    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            WALK_LEFT: walk_left = 1;
            WALK_RIGHT: walk_right = 1;
            FALL_LEFT: aaah = 1;
            FALL_RIGHT: aaah = 1;
            DIG_LEFT: digging = 1;
            DIG_RIGHT: digging = 1;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL_LEFT,
        STATE_FALL_RIGHT,
        STATE_DIG_LEFT,
        STATE_DIG_RIGHT
    } state_t;

    state_t state, next_state;

    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                if (!ground)
                    next_state = STATE_FALL_LEFT;
                else if (dig)
                    next_state = STATE_DIG_LEFT;
                else if (bump_left || (bump_left && bump_right))
                    next_state = STATE_WALK_RIGHT;
                else
                    next_state = STATE_WALK_LEFT;
            end

            STATE_WALK_RIGHT: begin
                if (!ground)
                    next_state = STATE_FALL_RIGHT;
                else if (dig)
                    next_state = STATE_DIG_RIGHT;
                else if (bump_right || (bump_left && bump_right))
                    next_state = STATE_WALK_LEFT;
                else
                    next_state = STATE_WALK_RIGHT;
            end

            STATE_FALL_LEFT: begin
                if (ground)
                    next_state = STATE_WALK_LEFT;
                else
                    next_state = STATE_FALL_LEFT;
            end

            STATE_FALL_RIGHT: begin
                if (ground)
                    next_state = STATE_WALK_RIGHT;
                else
                    next_state = STATE_FALL_RIGHT;
            end

            STATE_DIG_LEFT: begin
                if (!ground)
                    next_state = STATE_FALL_LEFT;
                else
                    next_state = STATE_DIG_LEFT;
            end

            STATE_DIG_RIGHT: begin
                if (!ground)
                    next_state = STATE_FALL_RIGHT;
                else
                    next_state = STATE_DIG_RIGHT;
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= STATE_WALK_LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            STATE_WALK_LEFT: walk_left = 1;
            STATE_WALK_RIGHT: walk_right = 1;
            STATE_FALL_LEFT,
            STATE_FALL_RIGHT: aaah = 1;
            STATE_DIG_LEFT: begin
                walk_left = 1;
                digging = 1;
            end
            STATE_DIG_RIGHT: begin
                walk_right = 1;
                digging = 1;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    typedef enum reg [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    always @(*) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;

                walk_left = 1;
            end
            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;

                walk_right = 1;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;

                aaah = 1;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;

                aaah = 1;
            end
            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;

                digging = 1;
            end
            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;

                digging = 1;
            end
            default: begin
                next_state = WALK_LEFT;
            end
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL_LEFT,
        STATE_FALL_RIGHT,
        STATE_DIG_LEFT,
        STATE_DIG_RIGHT,
        STATE_FALL_DIG_LEFT,
        STATE_FALL_DIG_RIGHT
    } state_t;

    state_t state, next_state;

    always @ (posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        dig = 1'b0;
        aaah = 1'b0;
        walking_left = 1'b0;
        walking_right = 1'b0;

        case (state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIG_LEFT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end
            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIG_RIGHT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end
            STATE_FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_FALL_LEFT;
                end
            end
            STATE_FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_FALL_RIGHT;
                end
            end
            STATE_DIG_LEFT: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL_DIG_LEFT;
                end else begin
                    next_state = STATE_DIG_LEFT;
                end
            end
            STATE_DIG_RIGHT: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL_DIG_RIGHT;
                end else begin
                    next_state = STATE_DIG_RIGHT;
                end
            end
            STATE_FALL_DIG_LEFT: begin
                aaah = 1;
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_FALL_DIG_LEFT;
                end
            end
            STATE_FALL_DIG_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_FALL_DIG_RIGHT;
                end
            end
            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // Define state encoding
    typedef enum logic [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    // State transition
    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end

            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end

            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end

            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end

            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end

            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end

            default: next_state = WALK_LEFT;
        endcase
    end

    // State register
    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
        digging = (state == DIG_LEFT) || (state == DIG_RIGHT);
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        case (state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else if (dig) begin
                    next_state = DIG_LEFT;
                end else if (bump_left) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                end
                walk_left = 1;
            end
            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else if (dig) begin
                    next_state = DIG_RIGHT;
                end else if (bump_right) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                end
                walk_right = 1;
            end
            FALL_LEFT: begin
                aaah = 1;
                if (ground) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = FALL_LEFT;
                end
            end
            FALL_RIGHT: begin
                aaah = 1;
                if (ground) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = FALL_RIGHT;
                end
            end
            DIG_LEFT: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else begin
                    next_state = DIG_LEFT;
                end
            end
            DIG_RIGHT: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else begin
                    next_state = DIG_RIGHT;
                end
            end
            default: next_state = WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // State encoding
    typedef enum logic [2:0] {
        WALK_LEFT  = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT  = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT   = 3'b100,
        DIG_RIGHT  = 3'b101
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else if (dig) begin
                    next_state = DIG_LEFT;
                end else if (bump_left || bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                end
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else if (dig) begin
                    next_state = DIG_RIGHT;
                end else if (bump_left || bump_right) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                end
            end

            FALL_LEFT: begin
                if (ground) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = FALL_LEFT;
                end
            end

            FALL_RIGHT: begin
                if (ground) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = FALL_RIGHT;
                end
            end

            DIG_LEFT: begin
                if (!ground) begin
                    next_state = FALL_LEFT;
                end else begin
                    next_state = DIG_LEFT;
                end
            end

            DIG_RIGHT: begin
                if (!ground) begin
                    next_state = FALL_RIGHT;
                end else begin
                    next_state = DIG_RIGHT;
                end
            end

            default: next_state = WALK_LEFT;
        endcase
    end

    // State flip-flops
    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    // Output logic
    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        case (state)
            WALK_LEFT: walk_left = 1;
            WALK_RIGHT: walk_right = 1;
            FALL_LEFT, FALL_RIGHT: aaah = 1;
            DIG_LEFT: digging = 1;
            DIG_RIGHT: digging = 1;
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

    // State encoding
    typedef enum logic [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    // State transition
    always_comb begin
        case (state)
            WALK_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else if (dig) next_state = DIG_LEFT;
                else if (bump_left || bump_right) next_state = WALK_RIGHT;
                else next_state = WALK_LEFT;
            end

            WALK_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else if (dig) next_state = DIG_RIGHT;
                else if (bump_right || bump_left) next_state = WALK_LEFT;
                else next_state = WALK_RIGHT;
            end

            FALL_LEFT: begin
                if (ground) next_state = WALK_LEFT;
                else next_state = FALL_LEFT;
            end

            FALL_RIGHT: begin
                if (ground) next_state = WALK_RIGHT;
                else next_state = FALL_RIGHT;
            end

            DIG_LEFT: begin
                if (!ground) next_state = FALL_LEFT;
                else next_state = DIG_LEFT;
            end

            DIG_RIGHT: begin
                if (!ground) next_state = FALL_RIGHT;
                else next_state = DIG_RIGHT;
            end

            default: begin
                next_state = WALK_LEFT; // Default to walk left on undefined state
            end
        endcase
    end

    // State flip-flops with asynchronous reset
    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    // Output logic
    always_comb begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
        aaah = (state == FALL_LEFT) || (state == FALL_RIGHT);
        digging = (state == DIG_LEFT) || (state == DIG_RIGHT);
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // Define states
    typedef enum reg [2:0] {
        LEFT = 3'b000,       // Walking left
        RIGHT = 3'b001,      // Walking right
        FALL_LEFT = 3'b010,  // Falling from left
        FALL_RIGHT = 3'b011, // Falling from right
        DIG_LEFT = 3'b100,   // Digging to left
        DIG_RIGHT = 3'b101   // Digging to right
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = RIGHT;
                else
                    next_state = LEFT;
            end

            RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = LEFT;
                else
                    next_state = RIGHT;
            end

            FALL_LEFT: begin
                if (ground)
                    next_state = LEFT;
                else
                    next_state = FALL_LEFT;
            end

            FALL_RIGHT: begin
                if (ground)
                    next_state = RIGHT;
                else
                    next_state = FALL_RIGHT;
            end

            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end

            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end

            default: next_state = LEFT;
        endcase
    end

    // Sequential logic for state register
    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        // Default assignments
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            LEFT: walk_left = 1;
            RIGHT: walk_right = 1;
            FALL_LEFT,
            FALL_RIGHT: aaah = 1;
            DIG_LEFT: begin
                walk_left = 1;
                digging = 1;
            end
            DIG_RIGHT: begin
                walk_right = 1;
                digging = 1;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        WALK_LEFT  = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT  = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT   = 3'b100,
        DIG_RIGHT  = 3'b101
    } state_t;

    state_t state, next_state;

    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end
            default: next_state = WALK_LEFT;
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        case (state)
            WALK_LEFT: walk_left = 1;
            WALK_RIGHT: walk_right = 1;
            FALL_LEFT, FALL_RIGHT: aaah = 1;
            DIG_LEFT: begin
                walk_left = 1;
                digging = 1;
            end
            DIG_RIGHT: begin
                walk_right = 1;
                digging = 1;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL_LEFT,
        STATE_FALL_RIGHT,
        STATE_DIG_LEFT,
        STATE_DIG_RIGHT
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALL_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIG_LEFT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_WALK_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALL_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIG_RIGHT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_FALL_LEFT: begin
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_FALL_LEFT;
                end
            end

            STATE_FALL_RIGHT: begin
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_FALL_RIGHT;
                end
            end

            STATE_DIG_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALL_LEFT;
                end else begin
                    next_state = STATE_DIG_LEFT;
                end
            end

            STATE_DIG_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALL_RIGHT;
                end else begin
                    next_state = STATE_DIG_RIGHT;
                end
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

    // State flip-flops with asynchronous reset
    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    // Output logic
    always @(*) begin
        walk_left = (state == STATE_WALK_LEFT);
        walk_right = (state == STATE_WALK_RIGHT);
        aaah = (state == STATE_FALL_LEFT) || (state == STATE_FALL_RIGHT);
        digging = (state == STATE_DIG_LEFT) || (state == STATE_DIG_RIGHT);
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT = 3'b000,
        STATE_WALK_RIGHT = 3'b001,
        STATE_FALL_LEFT = 3'b010,
        STATE_FALL_RIGHT = 3'b011,
        STATE_DIGGING_LEFT = 3'b100,
        STATE_DIGGING_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALL_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIGGING_LEFT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end
            STATE_WALK_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALL_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIGGING_RIGHT;
                end else if (bump_left || bump_right) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end
            STATE_FALL_LEFT: begin
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_FALL_LEFT;
                end
            end
            STATE_FALL_RIGHT: begin
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_FALL_RIGHT;
                end
            end
            STATE_DIGGING_LEFT: begin
                if (!ground) begin
                    next_state = STATE_FALL_LEFT;
                end else begin
                    next_state = STATE_DIGGING_LEFT;
                end
            end
            STATE_DIGGING_RIGHT: begin
                if (!ground) begin
                    next_state = STATE_FALL_RIGHT;
                end else begin
                    next_state = STATE_DIGGING_RIGHT;
                end
            end
            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

    always @(*) begin
        case (state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;
                digging = 0;
            end
            STATE_WALK_RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                aaah = 0;
                digging = 0;
            end
            STATE_FALL_LEFT, STATE_FALL_RIGHT: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1;
                digging = 0;
            end
            STATE_DIGGING_LEFT: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 0;
                digging = 1;
            end
            STATE_DIGGING_RIGHT: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 0;
                digging = 1;
            end
            default: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 0;
                digging = 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // Define the states
    typedef enum reg [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end
            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;
            end
            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;
            end
            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;
            end
            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;
            end
            default: next_state = WALK_LEFT;
        endcase
    end

    // State flip-flops with asynchronous reset
    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= WALK_LEFT;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            WALK_LEFT: walk_left = 1;
            WALK_RIGHT: walk_right = 1;
            FALL_LEFT, FALL_RIGHT: aaah = 1;
            DIG_LEFT: digging = 1;
            DIG_RIGHT: digging = 1;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging
);

    typedef enum logic [2:0] {
        LEFT_WALK = 3'b000,
        RIGHT_WALK = 3'b001,
        LEFT_FALL = 3'b010,
        RIGHT_FALL = 3'b011,
        LEFT_DIG = 3'b100,
        RIGHT_DIG = 3'b101
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= LEFT_WALK;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        case (state)
            LEFT_WALK: begin
                if (!ground) begin
                    next_state = LEFT_FALL;
                end else if (dig) begin
                    next_state = LEFT_DIG;
                end else if (bump_left) begin
                    next_state = RIGHT_WALK;
                end else begin
                    next_state = LEFT_WALK;
                end
            end
            RIGHT_WALK: begin
                if (!ground) begin
                    next_state = RIGHT_FALL;
                end else if (dig) begin
                    next_state = RIGHT_DIG;
                end else if (bump_right) begin
                    next_state = LEFT_WALK;
                end else begin
                    next_state = RIGHT_WALK;
                end
            end
            LEFT_FALL: begin
                if (ground) begin
                    next_state = LEFT_WALK;
                end else begin
                    next_state = LEFT_FALL;
                end
            end
            RIGHT_FALL: begin
                if (ground) begin
                    next_state = RIGHT_WALK;
                end else begin
                    next_state = RIGHT_FALL;
                end
            end
            LEFT_DIG: begin
                if (!ground) begin
                    next_state = LEFT_FALL;
                end else begin
                    next_state = LEFT_DIG;
                end
            end
            RIGHT_DIG: begin
                if (!ground) begin
                    next_state = RIGHT_FALL;
                end else begin
                    next_state = RIGHT_DIG;
                end
            end
            default: begin
                next_state = LEFT_WALK;
            end
        endcase
    end

    assign walk_left = (state == LEFT_WALK);
    assign walk_right = (state == RIGHT_WALK);
    assign aaah = (state == LEFT_FALL || state == RIGHT_FALL);
    assign digging = (state == LEFT_DIG || state == RIGHT_DIG);

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    // Define state encoding
    typedef enum logic [2:0] {
        WALK_LEFT = 3'b000,
        WALK_RIGHT = 3'b001,
        FALL_LEFT = 3'b010,
        FALL_RIGHT = 3'b011,
        DIG_LEFT = 3'b100,
        DIG_RIGHT = 3'b101
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_comb begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (current_state)
            WALK_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else if (dig && ground)
                    next_state = DIG_LEFT;
                else if (bump_left)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;

                walk_left = 1;
            end

            WALK_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else if (dig && ground)
                    next_state = DIG_RIGHT;
                else if (bump_right)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;

                walk_right = 1;
            end

            FALL_LEFT: begin
                if (ground)
                    next_state = WALK_LEFT;
                else
                    next_state = FALL_LEFT;

                aaah = 1;
            end

            FALL_RIGHT: begin
                if (ground)
                    next_state = WALK_RIGHT;
                else
                    next_state = FALL_RIGHT;

                aaah = 1;
            end

            DIG_LEFT: begin
                if (!ground)
                    next_state = FALL_LEFT;
                else
                    next_state = DIG_LEFT;

                digging = 1;
            end

            DIG_RIGHT: begin
                if (!ground)
                    next_state = FALL_RIGHT;
                else
                    next_state = DIG_RIGHT;

                digging = 1;
            end

            default: begin
                next_state = WALK_LEFT;
            end
        endcase
    end

endmodule


module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    // Initialize hh, mm, ss, and pm
    initial begin
        hh = 8'b00010010;  // "12"
        mm = 8'b00000000;  // "00"
        ss = 8'b00000000;  // "00"
        pm = 1'b0;         // "AM"
    end

    always @(posedge clk) begin
        if (reset) begin
            // Reset clock to 12:00 AM
            hh <= 8'b00010010;
            mm <= 8'b00000000;
            ss <= 8'b00000000;
            pm <= 1'b0;
        end else if (ena) begin
            // Increment seconds
            if (ss[3:0] == 4'd9) begin
                if (ss[7:4] == 4'd5) begin
                    ss <= 8'b00000000;  // Roll over to "00"

                    // Increment minutes
                    if (mm[3:0] == 4'd9) begin
                        if (mm[7:4] == 4'd5) begin
                            mm <= 8'b00000000;  // Roll over to "00"

                            // Increment hours
                            if (hh == 8'b00010010) begin
                                hh <= 8'b00000001;  // Roll over to "01"
                                pm <= ~pm;          // Toggle AM/PM
                            end else if (hh[3:0] == 4'd9) begin
                                hh[3:0] <= 4'd0;
                                hh[7:4] <= hh[7:4] + 1;
                            end else begin
                                hh <= hh + 1;
                            end
                        end else begin
                            mm[7:4] <= mm[7:4] + 1;
                            mm[3:0] <= 4'd0;
                        end
                    end else begin
                        mm[3:0] <= mm[3:0] + 1;
                    end
                end else begin
                    ss[7:4] <= ss[7:4] + 1;
                    ss[3:0] <= 4'd0;
                end
            end else begin
                ss[3:0] <= ss[3:0] + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010010; // 12 in BCD
            mm <= 8'b00000000; // 00 in BCD
            ss <= 8'b00000000; // 00 in BCD
            pm <= 1'b0; // AM
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'b01011001) begin // 59 in BCD
                ss <= 8'b00000000; // Reset seconds to 00
                // Increment minutes
                if (mm == 8'b01011001) begin // 59 in BCD
                    mm <= 8'b00000000; // Reset minutes to 00
                    // Increment hours
                    if (hh == 8'b00010010) begin // 12 in BCD
                        hh <= 8'b00000001; // Reset hours to 01
                        pm <= ~pm; // Toggle AM/PM
                    end else if (hh == 8'b00001001) begin // 9 in BCD
                        hh <= hh + 8'b00000110; // Adjust to 10
                    end else begin
                        hh <= hh + 8'b00000001; // Simple increment
                    end
                end else if (mm[3:0] == 4'b1001) begin // Last digit is 9
                    mm <= mm + 8'b00000110; // Adjust the tens digit
                end else begin
                    mm <= mm + 8'b00000001; // Simple increment
                end
            end else if (ss[3:0] == 4'b1001) begin // Last digit is 9
                ss <= ss + 8'b00000110; // Adjust the tens digit
            end else begin
                ss <= ss + 8'b00000001; // Simple increment
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    // Binary Coded Decimal counter utility
    function [7:0] bcd_increment;
        input [7:0] value;
        input [3:0] max_value;
        begin
            if (value[3:0] == 4'd9) begin
                if (value[7:4] == max_value) begin
                    bcd_increment = 8'd0;
                end else begin
                    bcd_increment = {value[7:4] + 4'd1, 4'd0};
                end
            end else begin
                bcd_increment = value + 1;
            end
        end
    endfunction

    // Initialization
    initial begin
        hh = 8'd12;
        mm = 8'd0;
        ss = 8'd0;
        pm = 0;
    end

    // Clock
    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd12;
            mm <= 8'd0;
            ss <= 8'd0;
            pm <= 0;
        end else if (ena) begin
            ss <= bcd_increment(ss, 4'd5);

            if (ss == 8'd59) begin
                ss <= 8'd0;
                mm <= bcd_increment(mm, 4'd5);

                if (mm == 8'd59) begin
                    mm <= 8'd0;
                    if (hh == 8'd12) begin
                        hh <= 8'd1;
                        pm <= ~pm;
                    end else begin
                        hh <= bcd_increment(hh, 4'd1);
                        if (hh == 8'd11 && !pm) begin
                            pm <= 1;
                        end else if (hh == 8'd11 && pm) begin
                            pm <= 0;
                        end
                    end
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to 12:00 AM
            hh <= 8'b0001_0010; // 12 in BCD
            mm <= 8'b0000_0000; // 00 in BCD
            ss <= 8'b0000_0000; // 00 in BCD
            pm <= 1'b0; // AM
        end else if (ena) begin
            // Seconds counter
            if (ss == 8'b0101_1001) begin // 59 in BCD
                ss <= 8'b0000_0000; // Reset seconds to 00
                // Minutes counter
                if (mm == 8'b0101_1001) begin // 59 in BCD
                    mm <= 8'b0000_0000; // Reset minutes to 00
                    // Hours counter
                    if (hh == 8'b0001_0010) begin // 12 in BCD
                        hh <= 8'b0000_0001; // Set hours to 01
                        pm <= ~pm; // Toggle PM/AM
                    end else if (hh == 8'b0000_1001) begin // 09 in BCD
                        hh <= 8'b0001_0000; // Set hours to 10
                    end else if (hh == 8'b0001_0000) begin // 10 in BCD
                        hh <= 8'b0001_0001; // Set hours to 11
                    end else if (hh == 8'b0001_0001) begin // 11 in BCD
                        hh <= 8'b0001_0010; // Set hours to 12
                    end else begin
                        hh[3:0] <= hh[3:0] + 1'b1; // Increment hours (for 01 to 08)
                    end
                end else if (mm[3:0] == 4'b1001) begin // If minutes LSB is 9
                    mm <= {mm[7:4] + 1'b1, 4'b0000}; // Increment tens place
                end else begin
                    mm <= {mm[7:4], mm[3:0] + 1'b1}; // Increment minutes
                end
            end else if (ss[3:0] == 4'b1001) begin // If seconds LSB is 9
                ss <= {ss[7:4] + 1'b1, 4'b0000}; // Increment tens place
            end else begin
                ss <= {ss[7:4], ss[3:0] + 1'b1}; // Increment seconds
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to "12:00 AM"
            hh <= 8'h12; // 12 in BCD
            mm <= 8'h00; // 00 in BCD
            ss <= 8'h00; // 00 in BCD
            pm <= 1'b0; // AM
        end
        else if (ena) begin
            // Increment the seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment the minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment the hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm; // Toggle AM/PM
                    end
                    else if (hh == 8'h11) begin
                        hh <= 8'h12; // Transition from 11 to 12
                    end
                    else begin
                        hh <= hh + 1;
                    end
                end
                else begin
                    mm <= mm + 1;
                end
            end
            else begin
                ss <= ss + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to 12:00:00 AM
            hh <= 8'b0001_0010; // 12 in BCD
            mm <= 8'b0000_0000; // 00 in BCD
            ss <= 8'b0000_0000; // 00 in BCD
            pm <= 1'b0;        // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'b0101_1001) begin
                ss <= 8'b0000_0000; // Roll over to 00
                // Increment minutes
                if (mm == 8'b0101_1001) begin
                    mm <= 8'b0000_0000; // Roll over to 00
                    // Increment hours
                    if (hh == 8'b0001_0010) begin
                        hh <= 8'b0000_0001; // Roll over to 01
                        pm <= ~pm; // Toggle AM/PM
                    end
                    else if (hh == 8'b0000_1001) begin
                        hh <= 8'b0001_0000; // 09 to 10
                    end
                    else if (hh == 8'b0001_0000) begin
                        hh <= 8'b0001_0001; // 10 to 11
                    end
                    else if (hh == 8'b0001_0001) begin
                        hh <= 8'b0001_0010; // 11 to 12
                    end
                    else begin
                        hh <= hh + 8'b0000_0001; // Increment hours
                    end
                end
                else if (mm[3:0] == 4'b1001) begin
                    mm <= {mm[7:4] + 4'b0001, 4'b0000}; // Handle minute rollover
                end
                else begin
                    mm <= mm + 8'b0000_0001; // Increment minutes
                end
            end
            else if (ss[3:0] == 4'b1001) begin
                ss <= {ss[7:4] + 4'b0001, 4'b0000}; // Handle second rollover
            end
            else begin
                ss <= ss + 8'b0000_0001; // Increment seconds
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the time to 12:00 AM
            hh <= 8'd12;
            mm <= 8'd0;
            ss <= 8'd0;
            pm <= 1'b0;
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'd59) begin
                ss <= 8'd0;
                // Increment minutes
                if (mm == 8'd59) begin
                    mm <= 8'd0;
                    // Increment hours
                    if (hh == 8'd12) begin
                        hh <= 8'd1;
                        pm <= ~pm; // Toggle AM/PM
                    end else if (hh == 8'd11) begin
                        hh <= 8'd12;
                    end else begin
                        hh <= hh + 8'd1;
                    end
                end else begin
                    mm <= mm + 8'd1;
                end
            end else begin
                ss <= ss + 8'd1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to 12:00 AM
            hh <= 8'h12; // 12 in BCD
            mm <= 8'h00; // 00 in BCD
            ss <= 8'h00; // 00 in BCD
            pm <= 1'b0;  // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;

                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;

                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm;  // Toggle AM/PM
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;  // Wrap 11 to 12
                    end else begin
                        if (hh[3:0] == 4'd9) begin
                            hh <= {hh[7:4] + 1'b1, 4'h0};  // Handle BCD increment
                        end else begin
                            hh <= hh + 1'b1;
                        end
                    end
                end else begin
                    if (mm[3:0] == 4'd9) begin
                        mm <= {mm[7:4] + 1'b1, 4'h0};  // Handle BCD increment
                    end else begin
                        mm <= mm + 1'b1;
                    end
                end
            end else begin
                if (ss[3:0] == 4'd9) begin
                    ss <= {ss[7:4] + 1'b1, 4'h0};  // Handle BCD increment
                end else begin
                    ss <= ss + 1'b1;
                end
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset to "12:00 AM"
            hh <= 8'b0001_0010; // BCD for 12
            mm <= 8'b0000_0000; // BCD for 00
            ss <= 8'b0000_0000; // BCD for 00
            pm <= 0; // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'b0101_1001) begin // 59
                ss <= 8'b0000_0000;

                // Increment minutes
                if (mm == 8'b0101_1001) begin // 59
                    mm <= 8'b0000_0000;

                    // Increment hours
                    if (hh == 8'b0001_0010) begin // 12
                        hh <= 8'b0000_0001; // 1
                        pm <= ~pm; // Toggle AM/PM
                    end
                    else if (hh == 8'b0001_0001) begin // 11
                        hh <= 8'b0001_0010; // 12
                    end
                    else if (hh[3:0] == 4'b1001) begin // x9
                        hh[3:0] <= 4'b0000;
                        hh[7:4] <= hh[7:4] + 1;
                    end
                    else begin
                        hh <= hh + 1;
                    end
                end
                else if (mm[3:0] == 4'b1001) begin // x9
                    mm[3:0] <= 4'b0000;
                    mm[7:4] <= mm[7:4] + 1;
                end
                else begin
                    mm <= mm + 1;
                end
            end
            else if (ss[3:0] == 4'b1001) begin // x9
                ss[3:0] <= 4'b0000;
                ss[7:4] <= ss[7:4] + 1;
            end
            else begin
                ss <= ss + 1;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'b00010010; // 12 in BCD
			mm <= 8'b00000000; // 00 in BCD
			ss <= 8'b00000000; // 00 in BCD
			pm <= 0; // AM
		end
		else if (ena) begin
			if (ss == 8'b01011001) begin // 59 in BCD
				ss <= 8'b00000000;
				if (mm == 8'b01011001) begin // 59 in BCD
					mm <= 8'b00000000;
					if (hh == 8'b00010010) begin // 12 in BCD
						hh <= 8'b00000001; // 01 in BCD
						pm <= ~pm; // toggle am/pm
					end
					else if (hh == 8'b00010001) begin // 11 in BCD
						hh <= 8'b00010010; // 12 in BCD
					end
					else begin
						if (hh[3:0] == 4'b1001) begin // 9 in BCD
							hh[3:0] <= 4'b0000;
							hh[7:4] <= hh[7:4] + 1;
						end
						else begin
							hh[3:0] <= hh[3:0] + 1;
						end
					end
				end
				else begin
					if (mm[3:0] == 4'b1001) begin // 9 in BCD
						mm[3:0] <= 4'b0000;
						mm[7:4] <= mm[7:4] + 1;
					end
					else begin
						mm[3:0] <= mm[3:0] + 1;
					end
				end
			end
			else begin
				if (ss[3:0] == 4'b1001) begin // 9 in BCD
					ss[3:0] <= 4'b0000;
					ss[7:4] <= ss[7:4] + 1;
				end
				else begin
					ss[3:0] <= ss[3:0] + 1;
				end
			end
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    // Helper function to increment BCD digits
    function [7:0] increment_bcd;
        input [7:0] bcd;
        if (bcd[3:0] == 4'd9) begin
            if (bcd[7:4] == 4'd5) begin
                increment_bcd = 8'd0;
            end
            else begin
                increment_bcd = {bcd[7:4] + 4'd1, 4'd0};
            end
        end
        else begin
            increment_bcd = bcd + 1;
        end
    endfunction

    // Main sequential logic
    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'h12; // hours set to 12
            mm <= 8'h00; // minutes set to 00
            ss <= 8'h00; // seconds set to 00
            pm <= 1'b0;  // indicator set to AM
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm; // Toggle PM indicator
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;
                    end else begin
                        hh <= increment_bcd(hh);
                    end
                end else begin
                    mm <= increment_bcd(mm);
                end
            end else begin
                ss <= increment_bcd(ss);
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset time to 12:00:00 AM
            ss <= 8'b00000000;
            mm <= 8'b00000000;
            hh <= 8'b00010010;  // 12 in BCD
            pm <= 0;
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'b01011001) begin
                ss <= 8'b00000000;
                // Increment minutes
                if (mm == 8'b01011001) begin
                    mm <= 8'b00000000;
                    // Increment hours
                    if (hh == 8'b00010010) begin
                        hh <= 8'b00000001;  // Turn to 1
                    end else if (hh == 8'b00001001) begin
                        hh <= 8'b00010000;  // Turn to 10
                    end else if (hh == 8'b00010010) begin
                        hh <= 8'b00000001;  // Turn to 1
                        pm <= ~pm;          // Toggle AM/PM
                    end else begin
                        hh <= hh + 1;
                    end
                end else begin
                    mm <= mm + 1;
                end
            end else begin
                ss <= ss + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    // BCD counter helper function
    function [7:0] bcd_inc;
        input [7:0] bcd;
        if (bcd[3:0] == 4'd9) begin
            bcd_inc[3:0] = 4'd0;
            if (bcd[7:4] == 4'd9)
                bcd_inc[7:4] = 4'd0;
            else
                bcd_inc[7:4] = bcd[7:4] + 4'd1;
        end
        else begin
            bcd_inc[3:0] = bcd[3:0] + 4'd1;
            bcd_inc[7:4] = bcd[7:4];
        end
    endfunction

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'h12;    // Set hours to "12"
            mm <= 8'h00;    // Set minutes to "00"
            ss <= 8'h00;    // Set seconds to "00"
            pm <= 1'b0;     // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm;  // Toggle AM/PM
                    end
                    else if (hh == 8'h11) begin
                        hh <= 8'h12; // Move to next hour, "12"
                    end
                    else begin
                        hh <= bcd_inc(hh);
                    end
                end
                else begin
                    mm <= bcd_inc(mm);
                end
            end
            else begin
                ss <= bcd_inc(ss);
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset to 12:00:00 AM
            hh <= 8'b0001_0010; // 12 in BCD
            mm <= 8'b0000_0000; // 00 in BCD
            ss <= 8'b0000_0000; // 00 in BCD
            pm <= 0; // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'b0101_1001) begin // 59 in BCD
                ss <= 8'b0000_0000; // Reset seconds to 00
                // Increment minutes
                if (mm == 8'b0101_1001) begin // 59 in BCD
                    mm <= 8'b0000_0000; // Reset minutes to 00
                    // Increment hours
                    if (hh == 8'b0001_0010) begin // 12 in BCD
                        hh <= 8'b0000_0001; // Reset hours to 01
                        pm <= ~pm; // Toggle AM/PM
                    end
                    else if (hh == 8'b0000_1001) begin // 09 in BCD
                        hh <= 8'b0001_0000; // Increment to 10
                    end
                    else if (hh == 8'b0001_0000) begin // 10 in BCD
                        hh <= 8'b0001_0001; // Increment to 11
                    end
                    else if (hh == 8'b0001_0001) begin // 11 in BCD
                        hh <= 8'b0001_0010; // Increment to 12
                    end
                    else begin
                        hh[3:0] <= hh[3:0] + 1; // Increment ones place
                    end
                end
                else begin
                    if (mm[3:0] == 4'b1001) begin // Ones place is at 9
                        mm[3:0] <= 4'b0000; // Reset ones place to 0
                        mm[7:4] <= mm[7:4] + 1; // Increment tens place
                    end
                    else begin
                        mm[3:0] <= mm[3:0] + 1; // Increment ones place
                    end
                end
            end
            else begin
                if (ss[3:0] == 4'b1001) begin // Ones place is at 9
                    ss[3:0] <= 4'b0000; // Reset ones place to 0
                    ss[7:4] <= ss[7:4] + 1; // Increment tens place
                end
                else begin
                    ss[3:0] <= ss[3:0] + 1; // Increment ones place
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset to 12:00:00 AM
            hh <= 8'b00010010; // 12 in BCD
            mm <= 8'b00000000; // 00 in BCD
            ss <= 8'b00000000; // 00 in BCD
            pm <= 1'b0;        // AM
        end
        else if (ena) begin
            // Increment seconds
            if (ss == 8'b01011001) begin  // 59 in BCD
                ss <= 8'b00000000;        // Reset seconds to 00
                // Increment minutes
                if (mm == 8'b01011001) begin // 59 in BCD
                    mm <= 8'b00000000;      // Reset minutes to 00
                    // Increment hours
                    if (hh == 8'b00010010) begin // 12 in BCD
                        hh <= 8'b00000001;      // Reset hours to 01
                        pm <= ~pm;             // Toggle AM/PM
                    end
                    else if (hh == 8'b00010001) begin // 11 in BCD
                        hh <= 8'b00010010;          // Set hours to 12
                    end
                    else begin
                        if ((hh[3:0] == 4'b1001)) begin
                            hh <= {hh[7:4] + 1'b1, 4'b0000}; // Increment tens place
                        end
                        else begin
                            hh <= hh + 1'b1; // Increment units place
                        end
                    end
                end
                else begin
                    if ((mm[3:0] == 4'b1001)) begin
                        mm <= {mm[7:4] + 1'b1, 4'b0000}; // Increment tens place if units is 9
                    end
                    else begin
                        mm <= mm + 1'b1; // Increment units place
                    end
                end
            end
            else begin
                if ((ss[3:0] == 4'b1001)) begin
                    ss <= {ss[7:4] + 1'b1, 4'b0000}; // Increment tens place if units is 9
                end
                else begin
                    ss <= ss + 1'b1; // Increment units place
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset to "12:00:00 AM"
            hh <= 8'h12;  // 12 in BCD
            mm <= 8'h00;
            ss <= 8'h00;
            pm <= 0;
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm;  // Toggle AM/PM
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;
                    end else begin
                        hh <= hh + 8'h01;
                    end
                end else begin
                    mm <= mm + 8'h01;
                end
            end else begin
                ss <= ss + 8'h01;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    // Define initial values
    initial begin
        hh = 8'h12; // 12 in BCD
        mm = 8'h00; // 00 in BCD
        ss = 8'h00; // 00 in BCD
        pm = 0;     // AM
    end

    // Sequential logic for the clock, with synchronous reset
    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to 12:00:00 AM
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            pm <= 0;
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        pm <= ~pm; // Toggle AM/PM
                    end else if (hh == 8'h11) begin
                        hh <= 8'h12;
                    end else begin
                        hh[3:0] <= hh[3:0] + 4'b0001;
                    end
                end else if (mm[3:0] == 4'h9) begin
                    mm <= {mm[7:4] + 4'b0001, 4'h0};
                end else begin
                    mm[3:0] <= mm[3:0] + 4'b0001;
                end
            end else if (ss[3:0] == 4'h9) begin
                ss <= {ss[7:4] + 4'b0001, 4'h0};
            end else begin
                ss[3:0] <= ss[3:0] + 4'b0001;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

always @(posedge clk) begin
    if (reset) begin
        // Reset the time to "12:00 AM"
        ss <= 8'b00000000; // 00
        mm <= 8'b00000000; // 00
        hh <= 8'b00010010; // 12
        pm <= 1'b0;        // AM
    end else if (ena) begin
        // Increment seconds
        if (ss == 8'b01011001) begin // 59
            ss <= 8'b00000000; // Reset seconds to 00
            // Increment minutes
            if (mm == 8'b01011001) begin // 59
                mm <= 8'b00000000; // Reset minutes to 00
                // Increment hours
                if (hh == 8'b00010010) begin // 12
                    hh <= 8'b00000001; // Wrap to 01
                    pm <= ~pm; // Toggle AM/PM
                end else if (hh == 8'b00001001) begin // 09
                    hh <= 8'b00010010; // Next is 10
                end else begin
                    hh[3:0] <= hh[3:0] + 4'b0001;
                    // Handle BCD carry for hh[7:4] when hours are 10, 11
                    if (hh[3:0] == 4'b1001) begin
                        hh[7:4] <= hh[7:4] + 4'b0001;
                        hh[3:0] <= 4'b0000;
                    end
                end
            end else begin
                mm[3:0] <= mm[3:0] + 4'b0001;
                // Handle BCD carry for mm[7:4]
                if (mm[3:0] == 4'b1001) begin
                    mm[7:4] <= mm[7:4] + 4'b0001;
                    mm[3:0] <= 4'b0000;
                end
            end
        end else begin
            ss[3:0] <= ss[3:0] + 4'b0001;
            // Handle BCD carry for ss[7:4]
            if (ss[3:0] == 4'b1001) begin
                ss[7:4] <= ss[7:4] + 4'b0001;
                ss[3:0] <= 4'b0000;
            end
        end
    end
end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    // Initialize registers
    initial begin
        hh = 8'b00010010; // 12 in BCD
        mm = 8'b00000000; // 00 in BCD
        ss = 8'b00000000; // 00 in BCD
        pm = 0; // AM
    end

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010010; // Reset to 12
            mm <= 8'b00000000; // Reset to 00
            ss <= 8'b00000000; // Reset to 00
            pm <= 0; // Reset to AM
        end else if (ena) begin
            // Increment the second counter
            if (ss == 8'b01011001) begin // 59 in BCD
                ss <= 8'b00000000; // Reset seconds to 00
                // Increment the minute counter
                if (mm == 8'b01011001) begin // 59 in BCD
                    mm <= 8'b00000000; // Reset minutes to 00
                    // Increment the hour counter
                    if (hh == 8'b00010010) begin // 12 in BCD
                        hh <= 8'b00000001; // Reset hours to 01
                        pm <= ~pm; // Toggle AM/PM
                    end else if (hh == 8'b00001001) begin // 09 in BCD
                        hh <= 8'b00010000; // Go to 10 in BCD
                    end else if (hh == 8'b00001000) begin // 08 in BCD
                        hh <= 8'b00001001; // Go to 09 in BCD
                    end else begin
                        hh <= hh + 1; // Simply increment the hour
                    end
                end else if (mm[3:0] == 4'b1001) begin // X9 in BCD
                    mm <= {mm[7:4] + 1, 4'b0000}; // Increment tens of minutes
                end else begin
                    mm <= mm + 1; // Increment unit of minutes
                end
            end else if (ss[3:0] == 4'b1001) begin // X9 in BCD
                ss <= {ss[7:4] + 1, 4'b0000}; // Increment tens of seconds
            end else begin
                ss <= ss + 1; // Increment unit of seconds
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            // Reset the clock to "12:00 AM"
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            pm <= 1'b0;
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'h59) begin
                ss <= 8'h00;
                // Increment minutes
                if (mm == 8'h59) begin
                    mm <= 8'h00;
                    // Increment hours
                    if (hh == 8'h12) begin
                        hh <= 8'h01;
                        // Toggle AM/PM
                        pm <= ~pm;
                    end else if (hh == 8'h11) begin
                        hh <= hh + 1;
                        // Toggle AM/PM on transition from 11 to 12
                        pm <= ~pm;
                    end else begin
                        hh <= hh + 1;
                    end
                end else begin
                    mm <= mm + 1;
                end
            end else begin
                ss <= ss + 1;
            end
        end
    end
endmodule