module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check scancode and set appropriate output
        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                // If none of the specified scancodes match, all outputs remain 0
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default output values
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check the scancodes
        case (scancode)
            16'he06b: left = 1;      // Left arrow
            16'he072: down = 1;      // Down arrow
            16'he074: right = 1;     // Right arrow
            16'he075: up = 1;        // Up arrow
            // Anything else results in all outputs remaining 0
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default values for outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;  // Left arrow key
            16'he072: down = 1;  // Down arrow key
            16'he074: right = 1; // Right arrow key
            16'he075: up = 1;    // Up arrow key
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check scancode and set respective output
        case (scancode)
            16'he06b: left  = 1;
            16'he072: down  = 1;
            16'he074: right = 1;
            16'he075: up    = 1;
            default: ; // No arrow key pressed
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default to all outputs being 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Decode the scancode
        case (scancode)
            16'he06b: left = 1;   // left arrow
            16'he072: down = 1;   // down arrow
            16'he074: right = 1;  // right arrow
            16'he075: up = 1;     // up arrow
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);
    always @(*) begin
        // Default all outputs to zero
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check scancode and set the appropriate output
        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: ;
        endcase
    end
endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    // Always block to evaluate scancode and set the appropriate outputs
    always @(*) begin
        // Default all outputs to zero
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Case statement to map scancode to arrow key
        case (scancode)
            16'he06b: left = 1;  // Left arrow
            16'he072: down = 1;  // Down arrow
            16'he074: right = 1; // Right arrow
            16'he075: up = 1;    // Up arrow
            // Default case is already handled by initializing to 0
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default values for all outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Determine which key is pressed based on scancode
        case (scancode)
            16'he06b: left = 1;  // left arrow
            16'he072: down = 1;  // down arrow
            16'he074: right = 1; // right arrow
            16'he075: up = 1;    // up arrow
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;    // left arrow
            16'he072: down = 1;    // down arrow
            16'he074: right = 1;   // right arrow
            16'he075: up = 1;      // up arrow
            default: ;             // none (all outputs remain 0)
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default values
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                // No arrow key is pressed
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default values
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check the scancode and assert the appropriate key
        case (scancode)
            16'he06b: left = 1;  // Left arrow key
            16'he072: down = 1;  // Down arrow key
            16'he074: right = 1; // Right arrow key
            16'he075: up = 1;    // Up arrow key
            default: ;  // No arrow key
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check scancode and set the appropriate output
        case (scancode)
            16'he06b: left = 1;  // left arrow
            16'he072: down = 1;  // down arrow
            16'he074: right = 1; // right arrow
            16'he075: up = 1;    // up arrow
            default: ;  // none
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;  // left arrow
            16'he072: down = 1;  // down arrow
            16'he074: right = 1; // right arrow
            16'he075: up = 1;    // up arrow
            default: ;           // none
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Initialize all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Determine which arrow key is pressed based on the scancode
        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                // No arrow key pressed, all outputs remain 0
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

    always @(*) begin
        // default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // check scancode and set the appropriate output
        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            default: begin
                left = 0;
                down = 0;
                right = 0;
                up = 0;
            end
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default all outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
            // No need for a default, as outputs are already set to 0
        endcase
    end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default values for outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Scancode processing
        case (scancode)
            16'he06b: left = 1;  // left arrow
            16'he072: down = 1;  // down arrow
            16'he074: right = 1; // right arrow
            16'he075: up = 1;    // up arrow
            default: ;           // none
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

	always @(*) begin
		// Default all outputs to 0
		left = 0;
		down = 0;
		right = 0;
		up = 0;

		// Check scancode and set the appropriate output
		case (scancode)
			16'he06b: left = 1;
			16'he072: down = 1;
			16'he074: right = 1;
			16'he075: up = 1;
			default: ; // Do nothing for other scancodes
		endcase
	end

endmodule


module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c0, c1, c2, c3;

    // Full adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign c0 = x[0] & y[0];

    // Full adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ c0;
    assign c1 = (x[1] & y[1]) | (c0 & (x[1] ^ y[1]));

    // Full adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ c1;
    assign c2 = (x[2] & y[2]) | (c1 & (x[2] ^ y[2]));

    // Full adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ c2;
    assign c3 = (x[3] & y[3]) | (c2 & (x[3] ^ y[3]));

    // Overflow bit
    assign sum[4] = c3;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // Full Adder for bit 0
    assign {c1, sum[0]} = x[0] + y[0];

    // Full Adder for bit 1
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Full Adder for bit 2
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Full Adder for bit 3
    assign {c4, sum[3]} = x[3] + y[3] + c3;

    // Overflow bit
    assign sum[4] = c4;
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3;

    // First full adder for LSB
    assign {c1, sum[0]} = x[0] + y[0];

    // Second full adder
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Third full adder
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Fourth full adder
    assign {sum[4], sum[3]} = x[3] + y[3] + c3;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // Full adder for the least significant bit
    assign {c1, sum[0]} = x[0] + y[0];

    // Full adder for the second bit
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Full adder for the third bit
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Full adder for the most significant bit
    assign {c4, sum[3]} = x[3] + y[3] + c3;

    // Assign the carry out as the overflow bit
    assign sum[4] = c4;
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

  wire c1, c2, c3;

  // Instantiate full adders
  full_adder fa0 (x[0], y[0], 1'b0, sum[0], c1);       // First full adder with initial carry-in as 0
  full_adder fa1 (x[1], y[1], c1, sum[1], c2);        // Second full adder
  full_adder fa2 (x[2], y[2], c2, sum[2], c3);        // Third full adder
  full_adder fa3 (x[3], y[3], c3, sum[3], sum[4]);    // Fourth full adder, sum[4] is the overflow

endmodule

module full_adder (
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
  assign {cout, sum} = a + b + cin;
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // Full adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign c1 = x[0] & y[0];

    // Full adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ c1;
    assign c2 = (x[1] & y[1]) | (c1 & (x[1] ^ y[1]));

    // Full adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ c2;
    assign c3 = (x[2] & y[2]) | (c2 & (x[2] ^ y[2]));

    // Full adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign c4 = (x[3] & y[3]) | (c3 & (x[3] ^ y[3]));

    // The overflow bit
    assign sum[4] = c4;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c1, c2, c3, c4;

    // Define the full adder for each bit position
    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(c1)
    );

    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(c1),
        .sum(sum[1]),
        .cout(c2)
    );

    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(c2),
        .sum(sum[2]),
        .cout(c3)
    );

    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(c3),
        .sum(sum[3]),
        .cout(c4)
    );

    // Overflow bit
    assign sum[4] = c4;

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (cin & a);

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // First Full Adder
    assign {c1, sum[0]} = x[0] + y[0];

    // Second Full Adder
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Third Full Adder
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Fourth Full Adder
    assign {c4, sum[3]} = x[3] + y[3] + c3;

    // Overflow bit
    assign sum[4] = c4;
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c1, c2, c3; // Internal carry wires

    // 1st full adder
    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(c1)
    );

    // 2nd full adder
    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(c1),
        .sum(sum[1]),
        .cout(c2)
    );

    // 3rd full adder
    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(c2),
        .sum(sum[2]),
        .cout(c3)
    );

    // 4th full adder
    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(c3),
        .sum(sum[3]),
        .cout(sum[4]) // The carry-out from the last adder is the overflow bit
    );

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

    assign sum = a ^ b ^ cin; // Sum bit calculation
    assign cout = (a & b) | (b & cin) | (cin & a); // Carry-out calculation

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3; // Internal wires to connect carry outputs

    // Instantiate 4 full adders
    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(c1)
    );

    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(c1),
        .sum(sum[1]),
        .cout(c2)
    );

    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(c2),
        .sum(sum[2]),
        .cout(c3)
    );

    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(c3),
        .sum(sum[3]),
        .cout(sum[4])
    );

endmodule

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // First full adder for least significant bit
    assign {c1, sum[0]} = x[0] + y[0];

    // Second full adder
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Third full adder
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Fourth full adder
    assign {c4, sum[3]} = x[3] + y[3] + c3;

    // Assign overflow bit
    assign sum[4] = c4;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c1, c2, c3;

    // Instantiate full adders for each bit
    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(0),
        .sum(sum[0]),
        .cout(c1)
    );

    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(c1),
        .sum(sum[1]),
        .cout(c2)
    );

    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(c2),
        .sum(sum[2]),
        .cout(c3)
    );

    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(c3),
        .sum(sum[3]),
        .cout(sum[4])
    );

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3;

    // Full Adder for bit[0]
    assign sum[0] = x[0] ^ y[0];
    assign c1 = x[0] & y[0];

    // Full Adder for bit[1]
    assign sum[1] = x[1] ^ y[1] ^ c1;
    assign c2 = (x[1] & y[1]) | (x[1] & c1) | (y[1] & c1);

    // Full Adder for bit[2]
    assign sum[2] = x[2] ^ y[2] ^ c2;
    assign c3 = (x[2] & y[2]) | (x[2] & c2) | (y[2] & c2);

    // Full Adder for bit[3]
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign sum[4] = (x[3] & y[3]) | (x[3] & c3) | (y[3] & c3);

endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	wire c1, c2, c3, c4;

	// First full adder
	assign sum[0] = x[0] ^ y[0];
	assign c1 = x[0] & y[0];

	// Second full adder
	assign sum[1] = x[1] ^ y[1] ^ c1;
	assign c2 = (x[1] & y[1]) | (x[1] & c1) | (y[1] & c1);

	// Third full adder
	assign sum[2] = x[2] ^ y[2] ^ c2;
	assign c3 = (x[2] & y[2]) | (x[2] & c2) | (y[2] & c2);

	// Fourth full adder
	assign sum[3] = x[3] ^ y[3] ^ c3;
	assign c4 = (x[3] & y[3]) | (x[3] & c3) | (y[3] & c3);

	// Overflow bit
	assign sum[4] = c4;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c1, c2, c3; // Intermediate carry wires

    // Full adder for bit 0
    assign {c1, sum[0]} = x[0] + y[0];

    // Full adder for bit 1
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Full adder for bit 2
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Full adder for bit 3
    assign {sum[4], sum[3]} = x[3] + y[3] + c3;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3;

    // Full adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign c1 = x[0] & y[0];

    // Full adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ c1;
    assign c2 = (x[1] & y[1]) | (x[1] & c1) | (y[1] & c1);

    // Full adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ c2;
    assign c3 = (x[2] & y[2]) | (x[2] & c2) | (y[2] & c2);

    // Full adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign sum[4] = (x[3] & y[3]) | (x[3] & c3) | (y[3] & c3);

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire c1, c2, c3, c4;

    // Full Adder for the least significant bit
    assign sum[0] = x[0] ^ y[0];
    assign c1 = x[0] & y[0];

    // Full Adder for the second bit
    assign sum[1] = x[1] ^ y[1] ^ c1;
    assign c2 = (x[1] & y[1]) | (x[1] & c1) | (y[1] & c1);

    // Full Adder for the third bit
    assign sum[2] = x[2] ^ y[2] ^ c2;
    assign c3 = (x[2] & y[2]) | (x[2] & c2) | (y[2] & c2);

    // Full Adder for the most significant bit
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign c4 = (x[3] & y[3]) | (x[3] & c3) | (y[3] & c3);

    // Overflow bit
    assign sum[4] = c4;

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3, c4;

    // Full adder for each bit, including carry-in and carry-out
    assign {c1, sum[0]} = x[0] + y[0];
    assign {c2, sum[1]} = x[1] + y[1] + c1;
    assign {c3, sum[2]} = x[2] + y[2] + c2;
    assign {c4, sum[3]} = x[3] + y[3] + c3;
    assign sum[4] = c4; // Overflow bit

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3;

    // First full adder: add x[0], y[0] and carry-in 0
    assign {c1, sum[0]} = x[0] + y[0];

    // Second full adder: add x[1], y[1] and carry-in c1
    assign {c2, sum[1]} = x[1] + y[1] + c1;

    // Third full adder: add x[2], y[2] and carry-in c2
    assign {c3, sum[2]} = x[2] + y[2] + c2;

    // Fourth full adder: add x[3], y[3] and carry-in c3
    assign {sum[4], sum[3]} = x[3] + y[3] + c3;

endmodule


module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);

	reg [7:0] Q;
	wire [2:0] selector;
	assign selector = {A, B, C};

	always @(posedge clk) begin
		if (enable) begin
			Q <= {Q[6:0], S}; // Shift right and insert S into Q[0]
		end
	end

	always @(*) begin
		case (selector)
			3'b000: Z = Q[0];
			3'b001: Z = Q[1];
			3'b010: Z = Q[2];
			3'b011: Z = Q[3];
			3'b100: Z = Q[4];
			3'b101: Z = Q[5];
			3'b110: Z = Q[6];
			3'b111: Z = Q[7];
			default: Z = 1'b0; // Default case (shouldn't happen)
		endcase
	end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);
    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift left and input new bit S
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // This case is technically redundant
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);
    reg [7:0] Q; // 8-bit shift register

    // Shift register logic
    always @(posedge clk) begin
        if (enable) begin
            Q[7:1] <= Q[6:0];
            Q[0] <= S;
        end
    end

    // 3:8 Decoder or Multiplexer logic for Z
    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // default case, though not necessary
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift in new bit S
        end
    end

    always @* begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case if needed
        endcase
    end

endmodule

module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift operation
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case to handle unknown states
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift operation
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0;
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift the register and input S into Q[0]
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 0; // Default case to avoid latches
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] shift_reg; // 8-bit shift register
    wire [2:0] select;
    assign select = {A, B, C}; // 3-bit select signal

    always @(posedge clk) begin
        if (enable) begin
            // Shift operation
            shift_reg <= {shift_reg[6:0], S};
        end
    end

    always @(*) begin
        // Multiplexing to select the appropriate Q[i] based on ABC
        case (select)
            3'b000: Z = shift_reg[0];
            3'b001: Z = shift_reg[1];
            3'b010: Z = shift_reg[2];
            3'b011: Z = shift_reg[3];
            3'b100: Z = shift_reg[4];
            3'b101: Z = shift_reg[5];
            3'b110: Z = shift_reg[6];
            3'b111: Z = shift_reg[7];
            default: Z = 0; // Default case
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    // Shift register logic
    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift-in operation
        end
    end

    // Multiplexer logic based on inputs A, B, C
    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case (typically unreachable)
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    // Shift register logic
    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift in the new bit S to Q[0], MSB shifted first
        end
    end

    // Multiplexer logic
    always @* begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case, though not necessary
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);
    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift right and input S
        end
    end

    always @* begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0;
        endcase
    end
endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S};
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case, should not happen
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // shift-in operation
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // just in case, though this should not occur
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift in the new bit S
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case, though unnecessary for 3-bit logic
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q;

    // 8-bit Shift Register
    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S};
        end
    end

    // Multiplexer for selecting output Z based on inputs A, B, C
    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 0;
        endcase
    end

endmodule

module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);
    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift to the right and insert new bit S
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case, though shouldn't occur
        endcase
    end
endmodule

module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift operation
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0;
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift and input new bit S
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0; // Default case
        endcase
    end

endmodule

module top_module (
    input clk,
    input enable,
    input S,
    input A,
    input B,
    input C,
    output reg Z
);

    reg [7:0] Q; // 8-bit shift register

    // Shift register logic
    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift in the bit S
        end
    end

    // Multiplexer to choose the output based on ABC
    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0;
        endcase
    end

endmodule

module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);

    reg [7:0] Q;

    always @(posedge clk) begin
        if (enable) begin
            Q <= {Q[6:0], S}; // Shift left, MSB (Q[0]) shifts in first
        end
    end

    always @(*) begin
        case ({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
            default: Z = 1'b0;
        endcase
    end

endmodule


module top_module(
    input clk,
    input reset,
    output reg [31:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 32'h1;
        end else begin
            q <= {q[30:0], q[31] ^ q[21] ^ q[1] ^ q[0]};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [31:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 32'h1;
        end else begin
            q <= {q[30:0], q[31] ^ q[21] ^ q[1] ^ q[0]};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [31:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 32'h1;
        end else begin
            q <= {q[30:0], (q[31] ^ q[21] ^ q[1] ^ q[0])};
        end
    end

endmodule


module top_module(
	input in,
	output out);

	assign out = in;

endmodule

module top_module(
    input in,
    output out
);

    assign out = in;

endmodule


module top_module(
    input in,
    output out
);

    assign out = ~in;

endmodule


module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    // Intermediate wires for the outputs of the AND gates
    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // 2-input AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // 2-input OR gates to generate final outputs
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for the outputs of the 3-input AND gates
    assign p1y = and1_out | and2_out;

    // 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for the outputs of the 2-input AND gates
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for first output (p1y)
    assign p1y = and1_out | and2_out;

    // 2-input AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for second output (p2y)
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // First two 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for p1y output
    assign p1y = and1_out | and2_out;

    // 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for p2y output
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;
    assign p1y = and1_out | and2_out;

    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // First AND gate for p1y
    assign and1_out = p1a & p1b & p1c;

    // Second AND gate for p1y
    assign and2_out = p1d & p1e & p1f;

    // OR the outputs of the first two AND gates to produce p1y
    assign p1y = and1_out | and2_out;

    // First AND gate for p2y
    assign and3_out = p2a & p2b;

    // Second AND gate for p2y
    assign and4_out = p2c & p2d;

    // OR the outputs of the last two AND gates to produce p2y
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);
    wire and1_out, and2_out, and3_out, and4_out;

    // AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for p1y
    assign p1y = and1_out | and2_out;

    // AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for p2y
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // First two 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for the first set of AND outputs
    assign p1y = and1_out | and2_out;

    // Two 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for the second set of AND outputs
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1, and2, and3, and4;

    // Three-input AND gates
    assign and1 = p1a & p1b & p1c;
    assign and2 = p1d & p1e & p1f;

    // Two-input AND gates
    assign and3 = p2a & p2b;
    assign and4 = p2c & p2d;

    // OR gates combining the outputs of the AND gates
    assign p1y = and1 | and2;
    assign p2y = and3 | and4;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    // Intermediate wires for AND gate outputs
    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // 2-input AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gates combining the AND gate results
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gates
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out;
    wire and2_out;
    wire and3_out;
    wire and4_out;

    // 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gates
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR of the outputs of the two 3-input AND gates
    assign p1y = and1_out | and2_out;

    // 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR of the outputs of the two 2-input AND gates
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
	input p1a,
	input p1b,
	input p1c,
	input p1d,
	input p1e,
	input p1f,
	output p1y,
	input p2a,
	input p2b,
	input p2c,
	input p2d,
	output p2y
);
    // Intermediate wires for the outputs of the AND gates
    wire and1_out, and2_out, and3_out, and4_out;

    // AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gates
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;
endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;
    assign p1y = and1_out | and2_out;

    // 2-input AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out;
    wire and2_out;
    wire and3_out;
    wire and4_out;

    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;
    assign p1y = and1_out | and2_out;

    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    // Intermediate wires for AND gate outputs
    wire and1_out, and2_out, and3_out, and4_out;

    // 3-input AND gates for p1y
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // 2-input AND gates for p2y
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR outputs of the AND gate results
    assign p1y = and1_out | and2_out;
    assign p2y = and3_out | and4_out;

endmodule

module top_module(
    input p1a,
    input p1b,
    input p1c,
    input p1d,
    input p1e,
    input p1f,
    output p1y,
    input p2a,
    input p2b,
    input p2c,
    input p2d,
    output p2y
);

    wire and1_out, and2_out, and3_out, and4_out;

    // First pair of 3-input AND gates
    assign and1_out = p1a & p1b & p1c;
    assign and2_out = p1d & p1e & p1f;

    // OR gate for p1y
    assign p1y = and1_out | and2_out;

    // First pair of 2-input AND gates
    assign and3_out = p2a & p2b;
    assign and4_out = p2c & p2d;

    // OR gate for p2y
    assign p2y = and3_out | and4_out;

endmodule


module top_module (
    input in1,
    input in2,
    output logic out
);
    assign out = ~(in1 | in2);
endmodule


module top_module (
	input clk,
	input d,
	input ar,
	output logic q
);

	always_ff @(posedge clk or posedge ar) begin
		if (ar)
			q <= 0;
		else
			q <= d;
	end

endmodule

module top_module (
    input clk,
    input d,
    input ar,
    output logic q
);

    always @(posedge clk or posedge ar) begin
        if (ar)
            q <= 1'b0;
        else
            q <= d;
    end

endmodule

module top_module (
    input clk,
    input d,
    input ar,
    output logic q
);
    always_ff @(posedge clk or posedge ar) begin
        if (ar)
            q <= 1'b0;
        else
            q <= d;
    end
endmodule

module top_module (
    input clk,
    input d,
    input ar,
    output logic q
);
    always @(posedge clk or posedge ar) begin
        if (ar)
            q <= 0;
        else
            q <= d;
    end
endmodule

module top_module (
	input clk,
	input d,
	input ar,
	output logic q
);

	always_ff @(posedge clk or posedge ar) begin
		if (ar) begin
			q <= 0;
		end else begin
			q <= d;
		end
	end

endmodule


module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        STATE_IDLE = 3'b000,
        STATE_1    = 3'b001,
        STATE_11   = 3'b010,
        STATE_110  = 3'b011,
        STATE_1101 = 3'b100
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk) begin
        if (reset) begin
            current_state <= STATE_IDLE;
            start_shifting <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == STATE_1101) begin
                start_shifting <= 1;
            end
        end
    end

    always @(*) begin
        case (current_state)
            STATE_IDLE: next_state = (data == 1'b1) ? STATE_1 : STATE_IDLE;
            STATE_1:    next_state = (data == 1'b1) ? STATE_11 : STATE_IDLE;
            STATE_11:   next_state = (data == 1'b0) ? STATE_110 : STATE_1;
            STATE_110:  next_state = (data == 1'b1) ? STATE_1101 : STATE_IDLE;
            STATE_1101: next_state = STATE_1101;
            default:    next_state = STATE_IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting);

    // State encoding
    typedef enum logic [2:0] {
        S0 = 3'b000, // Initial state
        S1 = 3'b001, // Detected 1
        S2 = 3'b010, // Detected 11
        S3 = 3'b011, // Detected 110
        S4 = 3'b100  // Detected 1101, set start_shifting
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            current_state <= S0;
            start_shifting <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state and output logic
    always @(*) begin
        next_state = current_state; // Default state is current state
        case (current_state)
            S0: begin
                if (data) next_state = S1;
            end
            S1: begin
                if (data) next_state = S2;
                else next_state = S0;
            end
            S2: begin
                if (data) next_state = S2;
                else next_state = S3;
            end
            S3: begin
                if (data) next_state = S4;
                else next_state = S0;
            end
            S4: begin
                // Remain in state S4 once reached
            end
            default: next_state = S0;
        endcase
    end

    // Output logic for start_shifting
    always @(posedge clk) begin
        if (reset) begin
            start_shifting <= 0;
        end else if (next_state == S4) begin
            start_shifting <= 1;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting );

    // State encoding
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        S1101 = 3'b100
    } state_t;

    state_t state, next_state;

    // State transition
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        next_state = state; // Default to stay in the same state
        case (state)
            IDLE:
                if (data) next_state = S1;
            S1:
                if (data) next_state = S11;
                else next_state = IDLE;
            S11:
                if (!data) next_state = S110;
            S110:
                if (data) next_state = S1101;
                else next_state = IDLE;
            S1101:
                next_state = S1101; // Stay in the same state
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset)
            start_shifting <= 0;
        else if (state == S1101)
            start_shifting <= 1;
    end
endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting);

    typedef enum reg [2:0] {
        S0 = 3'b000,
        S1 = 3'b001,
        S2 = 3'b010,
        S3 = 3'b011,
        S4 = 3'b100
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset) begin
            state <= S0;
            start_shifting <= 0;
        end else begin
            state <= next_state;
            if (state == S4)
                start_shifting <= 1;
        end
    end

    always @(*) begin
        case (state)
            S0: next_state = data ? S1 : S0;
            S1: next_state = data ? S2 : S0;
            S2: next_state = data ? S2 : S3;
            S3: next_state = data ? S4 : S0;
            S4: next_state = S4;
            default: next_state = S0;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // State encoding
    typedef enum reg [2:0] {
        S0,  // Initial state
        S1,  // Detected '1'
        S2,  // Detected '11'
        S3,  // Detected '110'
        S4   // Detected '1101'
    } state_t;

    state_t current_state, next_state;

    // Sequential logic: State transitions
    always @(posedge clk) begin
        if (reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    // Combinational logic: Next state logic
    always @(*) begin
        case (current_state)
            S0: next_state = (data) ? S1 : S0;
            S1: next_state = (data) ? S2 : S0;
            S2: next_state = (data) ? S2 : S3;
            S3: next_state = (data) ? S4 : S0;
            S4: next_state = S4;
            default: next_state = S0;
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset)
            start_shifting <= 1'b0;
        else if (current_state == S4)
            start_shifting <= 1'b1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        S1101 = 3'b100
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    always_comb begin
        next_state = current_state;
        case (current_state)
            IDLE:   next_state = (data ? S1 : IDLE);
            S1:     next_state = (data ? S11 : IDLE);
            S11:    next_state = (data ? S11 : S110);
            S110:   next_state = (data ? S1101 : IDLE);
            S1101:  next_state = S1101;
        endcase
    end

    always_ff @(posedge clk) begin
        if (reset)
            start_shifting <= 0;
        else if (current_state == S1101)
            start_shifting <= 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1 = 3'b001,      // Detected '1'
        S11 = 3'b010,     // Detected '11'
        S110 = 3'b011,    // Detected '110'
        S1101 = 3'b100   // Detected '1101'
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            start_shifting <= 0;
        end else begin
            state <= next_state;
            if (state == S1101)
                start_shifting <= 1;
        end
    end

    always @(*) begin
        case (state)
            IDLE: next_state = (data) ? S1 : IDLE;
            S1: next_state = (data) ? S11 : IDLE;
            S11: next_state = (data) ? S11 : S110;
            S110: next_state = (data) ? S1101 : IDLE;
            S1101: next_state = S1101; // Remain in this state
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        IDLE      = 3'b000,
        S1        = 3'b001,
        S11       = 3'b010,
        S110      = 3'b011,
        FOUND     = 3'b100
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            IDLE: begin
                if (data)
                    next_state = S1;
                else
                    next_state = IDLE;
            end
            S1: begin
                if (data)
                    next_state = S11;
                else
                    next_state = IDLE;
            end
            S11: begin
                if (!data)
                    next_state = S110;
                else
                    next_state = S11;
            end
            S110: begin
                if (data)
                    next_state = FOUND;
                else
                    next_state = IDLE;
            end
            FOUND: begin
                next_state = FOUND; // Remain in FOUND state
            end
            default: next_state = IDLE;
        endcase
    end

    always @(posedge clk) begin
        if (reset)
            start_shifting <= 0;
        else if (state == FOUND)
            start_shifting <= 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        IDLE    = 3'b000,
        S1      = 3'b001,
        S11     = 3'b010,
        S110    = 3'b011,
        FOUND   = 3'b100
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (state)
            IDLE:   next_state = data ? S1   : IDLE;
            S1:     next_state = data ? S11  : IDLE;
            S11:    next_state = data ? S11  : S110;
            S110:   next_state = data ? FOUND: IDLE;
            FOUND:  next_state = FOUND;
            default: next_state = IDLE;
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset)
            start_shifting <= 1'b0;
        else if (state == FOUND)
            start_shifting <= 1'b1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // Define state encoding
    typedef enum reg [2:0] {
        IDLE        = 3'b000,
        FIRST_ONE   = 3'b001,
        SECOND_ONE  = 3'b010,
        ZERO_AFTER_TWO_ONES = 3'b011,
        THIRD_ONE   = 3'b100
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
            start_shifting <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == THIRD_ONE && data == 1)
                start_shifting <= 1;
        end
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: begin
                if (data == 1)
                    next_state = FIRST_ONE;
                else
                    next_state = IDLE;
            end

            FIRST_ONE: begin
                if (data == 1)
                    next_state = SECOND_ONE;
                else
                    next_state = IDLE;
            end

            SECOND_ONE: begin
                if (data == 0)
                    next_state = ZERO_AFTER_TWO_ONES;
                else
                    next_state = SECOND_ONE;
            end

            ZERO_AFTER_TWO_ONES: begin
                if (data == 1)
                    next_state = THIRD_ONE;
                else
                    next_state = IDLE;
            end

            THIRD_ONE: begin
                if (data == 1)
                    next_state = FIRST_ONE;
                else
                    next_state = IDLE;
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        S0, // 0
        S1, // 1
        S2, // 11
        S3, // 110
        S4  // 1101 (sequence found)
    } state_t;

    state_t state, next_state;

    // State transition
    always @(posedge clk) begin
        if (reset) begin
            state <= S0;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case(state)
            S0: next_state = data ? S1 : S0;
            S1: next_state = data ? S2 : S0;
            S2: next_state = data ? S2 : S3;
            S3: next_state = data ? S4 : S0;
            S4: next_state = S4;
            default: next_state = S0;
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset) begin
            start_shifting <= 1'b0;
        end else if (state == S4) begin
            start_shifting <= 1'b1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        FOUND = 3'b100
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            IDLE:   next_state = data ? S1 : IDLE;
            S1:     next_state = data ? S11 : IDLE;
            S11:    next_state = data ? S11 : S110;
            S110:   next_state = data ? FOUND : IDLE;
            FOUND:  next_state = FOUND;
            default:next_state = IDLE;
        endcase
    end

    always @(posedge clk) begin
        if (reset)
            start_shifting <= 1'b0;
        else if (state == FOUND)
            start_shifting <= 1'b1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        S0 = 3'b000,
        S1 = 3'b001,
        S2 = 3'b010,
        S3 = 3'b011,
        S4 = 3'b100
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            state <= S0;
            start_shifting <= 0;
        end else begin
            state <= next_state;
            if (state == S4) begin
                start_shifting <= 1;
            end
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            S0: next_state = (data == 1) ? S1 : S0;
            S1: next_state = (data == 1) ? S2 : S0;
            S2: next_state = (data == 0) ? S3 : S2;
            S3: next_state = (data == 1) ? S4 : S0;
            S4: next_state = S4;
            default: next_state = S0;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // Define states
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        S1101= 3'b100
    } state_t;

    state_t current_state, next_state;

    // State Transition
    always @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    // Next State Logic
    always @(*) begin
        case (current_state)
            IDLE: next_state = (data) ? S1 : IDLE;
            S1: next_state = (data) ? S11 : IDLE;
            S11: next_state = (data) ? S11 : S110;
            S110: next_state = (data) ? S1101 : IDLE;
            S1101: next_state = S1101;
            default: next_state = IDLE;
        endcase
    end

    // Output Logic
    always @(posedge clk) begin
        if (reset) begin
            start_shifting <= 1'b0;
        end else begin
            if (current_state == S1101) begin
                start_shifting <= 1'b1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // State encoding
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001, // Seen first 1
        S11  = 3'b010, // Seen 11
        S110 = 3'b011, // Seen 110
        S1101 = 3'b100 // Seen 1101
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always @(*) begin
        case (current_state)
            IDLE: next_state = data ? S1 : IDLE;
            S1: next_state = data ? S11 : IDLE;
            S11: next_state = data ? S11 : S110;
            S110: next_state = data ? S1101 : IDLE;
            S1101: next_state = S1101;
            default: next_state = IDLE;
        endcase
    end

    // State memory
    always @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
            start_shifting <= 0;
        end
        else begin
            current_state <= next_state;
            if (current_state == S1101) begin
                start_shifting <= 1;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input data,
	output reg start_shifting);

	// State encoding
	typedef enum reg [2:0] {
		IDLE = 3'b000,
		S1   = 3'b001,
		S11  = 3'b010,
		S110 = 3'b011,
		S1101 = 3'b100,
		FOUND = 3'b101
	} state_type;

	state_type state, next_state;

	// State transition logic
	always @(posedge clk) begin
		if (reset) begin
			state <= IDLE;
			start_shifting <= 0;
		end else begin
			state <= next_state;
			if (state == FOUND)
				start_shifting <= 1;
		end
	end

	// Next state logic
	always @* begin
		next_state = state;
		case (state)
			IDLE:  next_state = data ? S1 : IDLE;
			S1:    next_state = data ? S11 : IDLE;
			S11:   next_state = data ? S11 : S110;
			S110:  next_state = data ? S1101 : IDLE;
			S1101: next_state = FOUND;
			FOUND: next_state = FOUND;
			default: next_state = IDLE;
		endcase
	end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting);

    // State encoding
    typedef enum reg [2:0] {
        S0, // Initial state, looking for first '1'
        S1, // Found '1', looking for second '1'
        S2, // Found '11', looking for '0'
        S3, // Found '110', looking for '1'
        S4  // Found '1101', activate start_shifting
    } state_t;

    state_t current_state, next_state;

    // Sequential logic for state transitions
    always @(posedge clk) begin
        if (reset) begin
            current_state <= S0;
            start_shifting <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == S4)
                start_shifting <= 1;
        end
    end

    // Combinational logic to determine next state
    always @(*) begin
        case (current_state)
            S0: next_state = data ? S1 : S0;
            S1: next_state = data ? S2 : S0;
            S2: next_state = data ? S2 : S3;
            S3: next_state = data ? S4 : S0;
            S4: next_state = S4; // stay in S4 once sequence is detected
            default: next_state = S0;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        S1101= 3'b100
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            start_shifting <= 0;
        end else begin
            state <= next_state;
            if (state == S1101)
                start_shifting <= 1;
        end
    end

    always @(*) begin
        case (state)
            IDLE: next_state = (data) ? S1 : IDLE;
            S1:   next_state = (data) ? S11 : IDLE;
            S11:  next_state = (data) ? S11 : S110;
            S110: next_state = (data) ? S1101 : IDLE;
            S1101: next_state = S1101;
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // Define state encoding
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        S1   = 3'b001,
        S11  = 3'b010,
        S110 = 3'b011,
        S1101 = 3'b100
    } state_t;

    state_t current_state, next_state;

    // Sequential logic for state transition
    always @(posedge clk) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    // Combinational logic for next state logic and output logic
    always_comb begin
        next_state = current_state; // Default state transition
        case (current_state)
            IDLE: begin
                if (data)
                    next_state = S1;
            end
            S1: begin
                if (data)
                    next_state = S11;
                else
                    next_state = IDLE;
            end
            S11: begin
                if (data)
                    next_state = S11;
                else
                    next_state = S110;
            end
            S110: begin
                if (data)
                    next_state = S1101;
                else
                    next_state = IDLE;
            end
            S1101: begin
                // Stay in this state indefinitely once reached
                next_state = S1101;
            end
            default: next_state = IDLE;
        endcase
    end

    // Output logic
    always_comb begin
        start_shifting = (current_state == S1101);
    end

endmodule

module top_module(
    input clk,
    input reset,
    input data,
    output reg start_shifting
);

    // State encoding
    typedef enum reg [1:0] {S0, S1, S2, S3, FOUND} state_t;
    state_t current_state, next_state;

    // State transition
    always @(posedge clk) begin
        if (reset) begin
            current_state <= S0;
            start_shifting <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == FOUND)
                start_shifting <= 1;
        end
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            S0: next_state = (data) ? S1 : S0;
            S1: next_state = (data) ? S1 : S2;
            S2: next_state = (data) ? S3 : S0;
            S3: next_state = (data) ? FOUND : S2;
            FOUND: next_state = FOUND;
            default: next_state = S0;
        endcase
    end

endmodule


module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (reset)
            q <= 4'd1;
        else if (q == 4'd10)
            q <= 4'd1;
        else
            q <= q + 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset counter to 1
        end else if (q == 4'b1010) begin
            q <= 4'b0001; // Reset to 1 after reaching 10
        end else begin
            q <= q + 1; // Increment counter
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else begin
            if (q == 4'd10) begin
                q <= 4'd1;
            end else begin
                q <= q + 4'd1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset the counter to 1
        end else if (q == 4'b1010) begin
            q <= 4'b0001; // Wrap around to 1 after reaching 10
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else if (q == 4'd10) begin
            q <= 4'd1;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1; // Reset the counter to 1
        end
        else if (q == 4'd10) begin
            q <= 4'd1; // Wrap around to 1 when reaching 10
        end
        else begin
            q <= q + 1; // Increment the counter
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset the counter to 1
        end else if (q == 4'b1010) begin
            q <= 4'b0001; // Reset to 1 after reaching 10
        end else begin
            q <= q + 1; // Increment the counter
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset the counter to 1
        end
        else if (q == 4'b1010) begin
            q <= 4'b0001; // Wrap around to 1 when reaching 10
        end
        else begin
            q <= q + 1; // Increment the counter
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset the counter to 1
        end else begin
            if (q == 4'b1010) begin // If the counter reaches 10
                q <= 4'b0001; // Reset the counter to 1
            end else begin
                q <= q + 1; // Increment the counter
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'b0001;
        else if (q == 4'b1010)
            q <= 4'b0001;
        else
            q <= q + 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else if (q == 4'd10) begin
            q <= 4'd1;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else if (q == 4'd10) begin
            q <= 4'd1;
        end else begin
            q <= q + 1'b1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset to 1
        end else begin
            if (q == 4'b1010) begin
                q <= 4'b0001; // Wrap around to 1 after counting to 10
            end else begin
                q <= q + 1; // Increment counter
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'b0001; // Reset counter to 1
        else if (q == 4'b1010)
            q <= 4'b0001; // Reset counter to 1 after reaching 10
        else
            q <= q + 1;   // Increment counter
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'd1;
        else if (q == 4'd10)
            q <= 4'd1;
        else
            q <= q + 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else if (q == 4'd10) begin
            q <= 4'd1;
        end else begin
            q <= q + 4'd1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

always @(posedge clk) begin
    if (reset) begin
        q <= 4'd1;
    end else begin
        if (q == 4'd10) begin
            q <= 4'd1;
        end else begin
            q <= q + 1;
        end
    end
end

endmodule


module top_module (
	input [4:1] x,
	output logic f
);
    always_comb begin
        case (x)
            4'b0000: f = 1'b0; // d (choosing 0 for don't-care)
            4'b0001: f = 1'b0;
            4'b0011: f = 1'b0; // d (choosing 0 for don't-care)
            4'b0010: f = 1'b0; // d (choosing 0 for don't-care)
            4'b0100: f = 1'b0;
            4'b0101: f = 1'b0; // d (choosing 0 for don't-care)
            4'b0111: f = 1'b1;
            4'b0110: f = 1'b0;
            4'b1100: f = 1'b1;
            4'b1101: f = 1'b1;
            4'b1111: f = 1'b1; // d (choosing 1 for don't-care)
            4'b1110: f = 1'b1; // d (choosing 1 for don't-care)
            4'b1000: f = 1'b1;
            4'b1001: f = 1'b1;
            4'b1011: f = 1'b0;
            4'b1010: f = 1'b1; // d (choosing 1 for don't-care)
            default: f = 1'b0;
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001, 4'b0110, 4'b1000, 4'b1001, 4'b1100, 4'b1101: f = 1;
            default: f = 0;
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001: f = 0;
            4'b0100: f = 0;
            4'b0110: f = 1;
            4'b0111: f = 0;
            4'b1011: f = 1;
            4'b1100: f = 1;
            4'b1101: f = 1;
            4'b1110: f = 0;
            4'b1111: f = 1;
            4'b1000: f = 1;
            default: f = 1'bx; // Handle don't-cares as undefined
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);

    always_comb begin
        casez (x)
            4'b00?0: f = 0;
            4'b01?1: f = 1;
            4'b1100: f = 1;
            4'b1101: f = 1;
            4'b1110: f = 1;
            4'b1000: f = 1;
            4'b1001: f = 1;
            4'b1010: f = 0;
            default: f = 0;
        endcase
    end

endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001, 4'b0100, 4'b0111: f = 0;
            4'b0101, 4'b0110, 4'b1011, 4'b1000, 4'b1001, 4'b1100, 4'b1101: f = 1;
            default: f = 0; // for don't-care conditions
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001, 4'b0111, 4'b1011, 4'b1000, 4'b1001, 4'b1100, 4'b1101: f = 1;
            4'b0100, 4'b0110, 4'b1010, 4'b1111: f = 0;
            default: f = 0; // Don't-care conditions default to 0 or could be left unspecified
        endcase
    end
endmodule

module top_module (
	input [4:1] x,
	output logic f
);
    always_comb begin
        case (x)
            4'b0100: f = 1'b0;
            4'b0110: f = 1'b0;
            4'b0111: f = 1'b1;
            4'b1000: f = 1'b1;
            4'b1001: f = 1'b1;
            4'b1100: f = 1'b1;
            4'b1101: f = 1'b1;
            4'b1110: f = 1'b0;
            default: f = 1'b0; // Default can be don't-care but choosing '0' for simplicity
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001: f = 0;
            4'b0100: f = 0;
            4'b0111: f = 1;
            4'b0110: f = 0;
            4'b1100: f = 1;
            4'b1101: f = 1;
            4'b1000: f = 1;
            4'b1001: f = 1;
            4'b1010: f = 0;
            default: f = 0; // Assign for don't-cares conveniently
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001, 4'b0111, 4'b1011, 4'b1000, 4'b1100: f = 1;
            4'b0100, 4'b0110, 4'b1010: f = 0;
            default: f = 1'bx; // Consider don't-cares as undefined
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0000: f = 0; // don't care, choose 0
            4'b0001: f = 0;
            4'b0011: f = 0; // don't care, choose 0
            4'b0010: f = 0; // don't care, choose 0
            4'b0100: f = 0;
            4'b0101: f = 0; // don't care, choose 0
            4'b0110: f = 1;
            4'b0111: f = 0;
            4'b1100: f = 1;
            4'b1101: f = 1;
            4'b1111: f = 1; // don't care, choose 1
            4'b1110: f = 1; // don't care, choose 1
            4'b1000: f = 1;
            4'b1001: f = 1;
            4'b1011: f = 0;
            4'b1010: f = 1; // don't care, choose 1
            default: f = 0; // Covers unexpected inputs, choose 0
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001: f = 0;
            4'b0110: f = 1;
            4'b0100: f = 0;
            4'b1000,
            4'b1001: f = 1;
            4'b1100,
            4'b1101: f = 1;
            4'b1011: f = 0;
            default: f = 0; // handle don't-cares and unspecified states
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0001: f = 0;
            4'b0100: f = 0;
            4'b0111: f = 1;
            4'b1011: f = 0;
            4'b1100: f = 1;
            4'b1101: f = 1;
            4'b1000: f = 1;
            4'b1001: f = 1;
            default: f = 0; // Assign a value to don't-cares, 0 is chosen here for default.
        endcase
    end
endmodule

module top_module (
    input [4:1] x,
    output logic f
);

    always_comb begin
        case (x)
            4'b0010, 4'b1011, 4'b1100, 4'b1101, 4'b1110: f = 1;
            4'b0100, 4'b1001, 4'b1010, 4'b1111: f = 0;
            default: f = 0;
        endcase
    end

endmodule

module top_module (
    input [4:1] x,
    output logic f
);
    always_comb begin
        case (x)
            4'b0100, 4'b1011, 4'b1110: f = 0;
            4'b0110, 4'b0111, 4'b1100, 4'b1101, 4'b1000, 4'b1001: f = 1;
            default: f = 0; // Assigning convenient value for don't-care conditions
        endcase
    end
endmodule


module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};
        end else if (count_ena) begin
            q <= q - 1;
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};  // Shift left and insert data into LSB
        end else if (count_ena) begin
            q <= q - 1;  // Decrement counter
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};  // Shift in MSB first
        end
        else if (count_ena) begin
            q <= q - 1;  // Decrement the counter
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};  // Shift in data from MSB first
        end
        else if (count_ena) begin
            q <= q - 1;  // Decrement by one
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data}; // Shift in data as MSB
        end
        else if (count_ena) begin
            q <= q - 1; // Decrement the value
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};
        end
        else if (count_ena) begin
            q <= q - 1;
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data}; // Shift left and insert new data bit
        end
        else if (count_ena) begin
            q <= q - 1; // Decrement the shift register value
        end
    end
endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (shift_ena) begin
			q <= {q[2:0], data}; // Shift in MSB first
		end
		else if (count_ena) begin
			q <= q - 1; // Decrement the value
		end
	end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};
        end
        else if (count_ena) begin
            q <= q - 1'b1;
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data};  // Shift left and bring in new data
        end else if (count_ena) begin
            q <= q - 1;  // Decrement the value in q
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            // Shift in data MSB first
            q <= {q[2:0], data};
        end else if (count_ena) begin
            // Decrement the counter
            q <= q - 1;
        end
    end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {q[2:0], data}; // Shift in data MSB first
        end
        else if (count_ena) begin
            q <= q - 1; // Decrement the number in the register
        end
    end

endmodule


module top_module(
    input in,
    output out);

    assign out = in;

endmodule

module top_module(
    input in,
    output out
);
    assign out = in;
endmodule