module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    typedef enum logic [2:0] {
        IDLE,
        DETECT_PATTERN,
        LOAD_DELAY,
        COUNTING,
        WAIT_ACK
    } state_t;

    state_t state, next_state;
    reg [3:0] shift_reg;
    reg [3:0] delay;
    reg [11:0] counter;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            shift_reg <= 4'b0;
            delay <= 4'b0;
            counter <= 12'b0;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            state <= next_state;
            shift_reg <= {shift_reg[2:0], data};
            if (state == LOAD_DELAY) begin
                delay <= {delay[2:0], data};
            end
            if (state == COUNTING && counting) begin
                if (counter != 12'd0) begin
                    counter <= counter - 12'd1;
                end
            end
        end
    end

    always @(*) begin
        next_state = state;
        counting = 1'b0;
        done = 1'b0;

        case (state)
            IDLE: begin
                if (shift_reg == 4'b1101) begin
                    next_state = LOAD_DELAY;
                end
            end

            LOAD_DELAY: begin
                if (delay[3:0] == 4'b1111) begin
                    next_state = COUNTING;
                    counting = 1'b1;
                    counter = (delay + 4'b0001) * 12'd1000;
                end
            end

            COUNTING: begin
                if (counter == 12'd0) begin
                    next_state = WAIT_ACK;
                    done = 1'b1;
                end else begin
                    counting = 1'b1;
                end
            end

            WAIT_ACK: begin
                if (ack) begin
                    next_state = DETECT_PATTERN;
                end
            end
        endcase
    end

    assign count = (state == COUNTING) ? (counter / 12'd1000) : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State encoding
    typedef enum reg [2:0] {
        WAIT_PATTERN = 3'd0,
        LOAD_DELAY   = 3'd1,
        COUNTING     = 3'd2,
        DONE         = 3'd3
    } state_t;

    state_t state, next_state;
    reg [3:0] delay;
    reg [3:0] current_count;
    reg [13:0] cycle_count;

    // Initialize state and outputs
    initial begin
        state = WAIT_PATTERN;
        done = 0;
        counting = 0;
    end

    // State register
    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT_PATTERN;
            done <= 0;
            counting <= 0;
            cycle_count <= 14'd0;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic and output control
    always @(*) begin
        next_state = state;
        case (state)
            WAIT_PATTERN: begin
                done = 0;
                counting = 0;
                cycle_count = 14'd0;
                current_count = 4'd0;

                // Shift in bits and detect pattern 1101
                if (data) begin
                    if (({data, cycle_count[3:1]} == 4'b1101)) begin
                        next_state = LOAD_DELAY;
                    end else begin
                        cycle_count = {data, cycle_count[3:0]};
                    end
                end
            end

            LOAD_DELAY: begin
                if (cycle_count[3:0] != 4'b1111) begin
                    cycle_count = {data, cycle_count[3:0]};
                end else begin
                    delay = cycle_count[3:0];
                    next_state = COUNTING;
                end
            end

            COUNTING: begin
                counting = 1;

                cycle_count = cycle_count + 1;

                if (cycle_count == 14'd999) begin
                    cycle_count = 14'd0;
                    if (current_count > 0) begin
                        current_count = current_count - 1;
                    end else begin
                        next_state = DONE;
                    end
                end
            end

            DONE: begin
                counting = 0;
                done = 1;

                if (ack) begin
                    next_state = WAIT_PATTERN;
                end
            end

            default: begin
                next_state = WAIT_PATTERN;
            end
        endcase
    end

    // Output logic for the count output
    assign count = (state == COUNTING) ? current_count : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        PATTERN_DETECT = 3'b001,
        LOAD_DELAY = 3'b010,
        COUNT = 3'b011,
        WAIT_ACK = 3'b100
    } state_t;

    state_t state, next_state;
    logic [3:0] delay;
    logic [12:0] count_cycle; // to count up to 8000

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            count <= 4'b0;
            counting <= 1'b0;
            done <= 1'b0;
            delay <= 4'b0;
            count_cycle <= 13'b0;
        end else begin
            state <= next_state;
            if (state == LOAD_DELAY && next_state == COUNT) begin
                count <= delay;
                count_cycle <= (delay + 1) * 1000;
                counting <= 1'b1;
            end else if (next_state == COUNT) begin
                if (count_cycle == 0) begin
                    counting <= 1'b0;
                    done <= 1'b1;
                end else if (count_cycle % 1000 == 0) begin
                    count <= count - 1;
                end
                count_cycle <= count_cycle - 1;
            end else if (next_state == WAIT_ACK) begin
                done <= 1'b1;
            end else if (next_state == IDLE) begin
                done <= 1'b0;
            end
        end
    end

    always_comb begin
        next_state = state;
        case (state)
            IDLE: begin
                if (data == 1'b1) begin // Start of 1101 pattern
                    next_state = PATTERN_DETECT;
                end
            end
            PATTERN_DETECT: begin
                if (data == 1'b1) begin // 2nd bit of pattern is 1
                    next_state = LOAD_DELAY;
                end else begin
                    next_state = IDLE; // Reset state if pattern fails
                end
            end
            LOAD_DELAY: begin
                if (count_cycle[12:9] == 4'b1101) begin
                    delay = count_cycle[8:5]; // Delay comes from next 4 bits
                    next_state = COUNT;
                end else begin
                    count_cycle = {count_cycle[11:0], data}; // Shift in next data bit
                end
            end
            COUNT: begin
                if (count_cycle == 13'b0) begin
                    next_state = WAIT_ACK;
                end
            end
            WAIT_ACK: begin
                if (ack == 1'b1) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state, next_state;
    reg [5:0] bit_counter; // To count delay and sequence bits
    reg [3:0] delay, current_count;
    reg [9:0] cycle_counter; // For 1000 cycle count

    localparam IDLE = 4'd0,
               DETECT_1 = 4'd1,
               DETECT_11 = 4'd2,
               DETECT_110 = 4'd3,
               DETECT_1101 = 4'd4,
               LOAD_DELAY = 4'd5,
               COUNTDOWN = 4'd6,
               DONE = 4'd7;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            bit_counter <= 0;
            current_count <= 0;
            cycle_counter <= 0;
            delay <= 0;
            done <= 0;
            counting <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(posedge clk) begin
        case (state)
            IDLE: begin
                counting <= 0;
                done <= 0;
                bit_counter <= 0;
                if (data)
                    next_state <= DETECT_1;
                else
                    next_state <= IDLE;
            end

            DETECT_1: next_state <= (data) ? DETECT_11 : IDLE;

            DETECT_11: next_state <= (!data) ? DETECT_110 : IDLE;

            DETECT_110: next_state <= (data) ? DETECT_1101 : IDLE;

            DETECT_1101: begin
                if (data) begin
                    bit_counter <= 0;
                    next_state <= LOAD_DELAY;
                end else begin
                    next_state <= IDLE;
                end
            end

            LOAD_DELAY: begin
                bit_counter <= bit_counter + 1;
                delay <= {delay[2:0], data};
                if (bit_counter == 3) begin // Once 4 bits are loaded
                    current_count <= delay;
                    counting <= 1;
                    cycle_counter <= 0;
                    next_state <= COUNTDOWN;
                end else begin
                    next_state <= LOAD_DELAY;
                end
            end

            COUNTDOWN: begin
                if (cycle_counter == 999) begin
                    cycle_counter <= 0;
                    if (current_count == 0) begin
                        counting <= 0;
                        done <= 1;
                        next_state <= DONE;
                    end else begin
                        current_count <= current_count - 1;
                        next_state <= COUNTDOWN;
                    end
                end else begin
                    cycle_counter <= cycle_counter + 1;
                    next_state <= COUNTDOWN;
                end
            end

            DONE: begin
                if (ack) begin
                    done <= 0;
                    next_state <= IDLE;
                end else begin
                    next_state <= DONE;
                end
            end

            default: next_state <= IDLE;
        endcase
    end

    always @* begin
        if (state == COUNTDOWN)
            count = current_count;
        else
            count = 4'bxxxx; // Don't care state
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State encoding
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        READ_DELAY = 3'b001,
        COUNT = 3'b010,
        DONE = 3'b011,
        WAIT_ACK = 3'b100
    } state_t;

    state_t current_state, next_state;

    reg [3:0] delay;
    reg [3:0] delay_counter;
    reg [9:0] cycle_counter;

    // State transition
    always_ff @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic and output logic
    always_comb begin
        next_state = current_state;
        counting = 1'b0;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                count = 4'd0;
                if (data == 1'b1 && $past(data, 1) == 1'b0 &&
                    $past(data, 2) == 1'b1 && $past(data, 3) == 1'b1) begin
                    next_state = READ_DELAY;
                end
            end

            READ_DELAY: begin
                if (cycle_counter < 4) begin
                    delay[3] = delay[2];
                    delay[2] = delay[1];
                    delay[1] = delay[0];
                    delay[0] = data;
                    cycle_counter = cycle_counter + 1;
                end else begin
                    delay_counter = delay;
                    cycle_counter = 10'd1000;
                    next_state = COUNT;
                end
            end

            COUNT: begin
                counting = 1'b1;
                count = delay_counter;
                if (cycle_counter == 10'd0) begin
                    if (delay_counter == 4'd0) begin
                        next_state = DONE;
                    end else begin
                        delay_counter = delay_counter - 1;
                        cycle_counter = 10'd999;
                    end
                end else begin
                    cycle_counter = cycle_counter - 1;
                end
            end

            DONE: begin
                done = 1'b1;
                if (ack) begin
                    next_state = WAIT_ACK;
                end
            end

            WAIT_ACK: begin
                if (!ack) begin
                    next_state = IDLE;
                end
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State definitions
    typedef enum reg [2:0] {
        S_IDLE = 3'b000,
        S_DETECT = 3'b001,
        S_LOAD_DELAY = 3'b010,
        S_COUNTDOWN = 3'b011,
        S_DONE = 3'b100
    } state_t;

    reg [2:0] state, next_state;
    reg [3:0] delay;
    reg [3:0] received_bits;
    reg [12:0] cycle_count; // 13 bits to count up to 8000

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S_IDLE;
        else
            state <= next_state;
    end

    // Next state logic and outputs
    always @(*) begin
        // Defaults
        next_state = state;
        counting = 0;
        done = 0;
        case (state)
            S_IDLE: begin
                if (reset)
                    next_state = S_IDLE;
                else
                    next_state = S_DETECT;
            end
            S_DETECT: begin
                if (reset)
                    next_state = S_IDLE;
                else if (received_bits == 4'b1101)
                    next_state = S_LOAD_DELAY;
            end
            S_LOAD_DELAY: begin
                if (reset)
                    next_state = S_IDLE;
                else if (received_bits[3:0] == 4'hF)
                    next_state = S_COUNTDOWN;
            end
            S_COUNTDOWN: begin
                counting = 1;
                if (cycle_count == 13'd0)
                    next_state = S_DONE;
            end
            S_DONE: begin
                done = 1;
                if (ack)
                    next_state = S_IDLE;
            end
        endcase
    end

    // Register control
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            received_bits <= 4'b0;
            delay <= 4'b0;
            cycle_count <= 13'b0;
            count <= 4'b0;
        end else begin
            case (state)
                S_DETECT: begin
                    received_bits <= {received_bits[2:0], data};
                end
                S_LOAD_DELAY: begin
                    delay <= {delay[2:0], data};
                end
                S_COUNTDOWN: begin
                    if (cycle_count == 13'd0) begin
                        if (count > 0)
                            count <= count - 1;
                        cycle_count <= 13'd999;
                    end else begin
                        cycle_count <= cycle_count - 1;
                    end
                end
                S_DONE: begin
                    if (ack) begin
                        received_bits <= 4'b0;
                        delay <= 4'b0;
                        cycle_count <= 13'b0;
                        count <= 4'b0;
                    end
                end
            endcase
        end
    end

    // Countdown logic
    always @(state or count) begin
        case (state)
            S_COUNTDOWN: begin
                if (cycle_count == 13'd999)
                    count <= delay;
            end
        endcase
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State definitions
    typedef enum reg [2:0] {
        IDLE,
        PATTERN_DETECTION,
        LOAD_DELAY,
        COUNTING,
        WAIT_ACK
    } state_t;

    state_t state, next_state;
    reg [3:0] shift_reg;
    reg [3:0] delay;
    reg [9:0] cycle_counter;
    reg [11:0] total_cycles; // Stores (delay + 1) * 1000
    reg [3:0] remaining_time;

    // Shift register logic for pattern detection and delay loading
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else if (state == PATTERN_DETECTION) begin
            shift_reg <= {shift_reg[2:0], data};
        end else if (state == LOAD_DELAY) begin
            shift_reg <= {shift_reg[2:0], data};
        end
    end

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // State machine
    always @(*) begin
        next_state = state;
        counting = 1'b0;
        done = 1'b0;

        case (state)
            IDLE: begin
                if (shift_reg == 4'b1101) begin
                    next_state = LOAD_DELAY;
                end
            end
            LOAD_DELAY: begin
                if (&shift_reg) begin // Delay pattern loaded (after keeping clk cycles)
                    delay = shift_reg;
                    total_cycles = (delay + 1) * 1000;
                    cycle_counter = 0;
                    remaining_time = delay;
                    next_state = COUNTING;
                end
            end
            COUNTING: begin
                counting = 1'b1;
                if (cycle_counter < total_cycles) begin
                    cycle_counter = cycle_counter + 1;
                end else begin
                    next_state = WAIT_ACK;
                end
                if (cycle_counter % 1000 == 0 && cycle_counter != 0) begin
                    remaining_time = remaining_time - 1;
                end
            end
            WAIT_ACK: begin
                done = 1'b1;
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

    // Remaining time and count logic
    assign count = (counting) ? remaining_time : 4'bx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state, next_state;
    reg [3:0] shift_reg, delay;
    reg [13:0] cycle_counter;
    reg [1:0] bit_count;
    wire pattern_detected;

    // State encoding
    localparam IDLE        = 4'd0,
               READ_DELAY  = 4'd1,
               COUNTING    = 4'd2,
               DONE        = 4'd3;

    // Pattern detection: 1101
    assign pattern_detected = (shift_reg == 4'b1101);

    // Output count as the remaining time in 1000 cycle units
    assign count = (state == COUNTING) ? (cycle_counter[13:10]) : 4'bxxxx;

    // State machine logic
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            shift_reg <= 4'b0;
            delay <= 4'b0;
            cycle_counter <= 14'b0;
            counting <= 1'b0;
            done <= 1'b0;
            bit_count <= 2'b0;
        end
        else begin
            state <= next_state;
            case(state)
                IDLE: begin
                    shift_reg <= {shift_reg[2:0], data}; // Shift in new data bit
                    if (pattern_detected) begin
                        counting <= 1'b1;
                        bit_count <= 2'b0;
                    end
                end

                READ_DELAY: begin
                    if (bit_count < 2'b11) begin
                        shift_reg <= {shift_reg[2:0], data}; // Shift in next 4 bits (MSB first)
                        bit_count <= bit_count + 1;
                    end
                    else begin
                        delay <= {shift_reg[2:0], data};
                        cycle_counter <= ({shift_reg[2:0], data} + 1) * 1000;
                        bit_count <= 2'b0;
                    end
                end

                COUNTING: begin
                    if (cycle_counter > 0) begin
                        cycle_counter <= cycle_counter - 1;
                    end
                    else begin
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end

                DONE: begin
                    if (ack) begin
                        done <= 1'b0;
                    end
                end
            endcase
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: begin
                if (pattern_detected) begin
                    next_state = READ_DELAY;
                end
            end
            READ_DELAY: begin
                if (bit_count == 2'b11) begin
                    next_state = COUNTING;
                end
            end
            COUNTING: begin
                if (cycle_counter == 0) begin
                    next_state = DONE;
                end
            end
            DONE: begin
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

    reg [3:0] state;
    reg [2:0] bit_counter;
    reg [3:0] delay;
    reg [13:0] cycle_counter;

    localparam STATE_IDLE = 4'd0;
    localparam STATE_DETECT_1101 = 4'd1;
    localparam STATE_SHIFT = 4'd2;
    localparam STATE_COUNT = 4'd3;
    localparam STATE_DONE = 4'd4;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= STATE_IDLE;
            bit_counter <= 3'd0;
            delay <= 4'd0;
            cycle_counter <= 14'd0;
            counting <= 1'b0;
            done <= 1'b0;
            count <= 4'd0;
        end else begin
            case (state)
                STATE_IDLE: begin
                    done <= 1'b0;
                    counting <= 1'b0;
                    if (data) begin
                        bit_counter <= 3'd1;
                        state <= STATE_DETECT_1101;
                    end
                end

                STATE_DETECT_1101: begin
                    if (data == 1'b1 && bit_counter == 3'd3) begin
                        state <= STATE_SHIFT;
                        delay <= 4'd0;
                        bit_counter <= 3'd0;
                    end else if (data == 1'b1 && bit_counter < 3'd3) begin
                        bit_counter <= bit_counter + 3'd1;
                    end else begin
                        state <= STATE_IDLE;
                    end
                end

                STATE_SHIFT: begin
                    if (bit_counter < 3'd4) begin
                        delay <= {delay[2:0], data};
                        bit_counter <= bit_counter + 3'd1;
                    end else begin
                        cycle_counter <= (delay + 14'd1) * 14'd1000;
                        state <= STATE_COUNT;
                        counting <= 1'b1;
                        bit_counter <= 3'd0;
                    end
                end

                STATE_COUNT: begin
                    if (cycle_counter > 0) begin
                        cycle_counter <= cycle_counter - 1;
                        if (cycle_counter[9:0] == 10'd0)
                            count <= cycle_counter[13:10];
                    end else begin
                        state <= STATE_DONE;
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end

                STATE_DONE: begin
                    if (ack) begin
                        state <= STATE_IDLE;
                    end
                end

                default: begin
                    state <= STATE_IDLE;
                end
            endcase
        end
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state;
    reg [3:0] delay;
    reg [9:0] counter;
    reg [3:0] shift_register;
    reg [3:0] remaining_count;

    localparam IDLE = 4'd0;
    localparam PATTERN_DETECTED = 4'd1;
    localparam DELAY_RECEIVING = 4'd2;
    localparam COUNTING = 4'd3;
    localparam DONE = 4'd4;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            delay <= 4'd0;
            shift_register <= 4'd0;
            counter <= 10'd0;
            remaining_count <= 4'd0;
            counting <= 0;
            done <= 0;
        end else begin
            case (state)
                IDLE: begin
                    done <= 0;
                    if (shift_register == 4'b1101) begin
                        state <= PATTERN_DETECTED;
                        shift_register <= 4'd0;
                    end else begin
                        shift_register <= {shift_register[2:0], data};
                    end
                end
                PATTERN_DETECTED: begin
                    shift_register <= {shift_register[2:0], data};
                    if (shift_register == 4'b1100) begin  // After reaching 4 bits
                        delay <= {shift_register[2:0], data};
                        state <= DELAY_RECEIVING;
                        remaining_count <= {shift_register[2:0], data};
                    end
                end
                DELAY_RECEIVING: begin
                    counter <= 10'd999;
                    state <= COUNTING;
                    counting <= 1;
                end
                COUNTING: begin
                    if (counter == 0) begin
                        if (remaining_count == 0) begin
                            state <= DONE;
                            counting <= 0;
                            done <= 1;
                        end else begin
                            remaining_count <= remaining_count - 1;
                            counter <= 10'd999;
                        end
                    end else begin
                        counter <= counter - 1;
                    end
                end
                DONE: begin
                    if (ack) begin
                        state <= IDLE;
                    end
                end
            endcase
        end
    end

    assign count = (counting) ? remaining_count : 4'd0;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    // State encoding
    typedef enum reg [2:0] {
        IDLE       = 3'b000,
        DETECT_1   = 3'b001,
        DETECT_11  = 3'b010,
        DETECT_110 = 3'b011,
        DETECT_1101= 3'b100,
        LOAD_DELAY = 3'b101,
        COUNTING   = 3'b110,
        WAIT_ACK   = 3'b111
    } state_t;

    state_t state, next_state; // current and next state

    reg [3:0] delay, remaining_time;
    reg [12:0] cycle_count; // 13 bits to count up to 8191 cycles (max delay+1)*1000

    // State transition
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic and outputs
    always @(*) begin
        // Default signals
        done = 0;
        counting = 0;
        next_state = state;

        case (state)
            IDLE: begin
                if (data) next_state = DETECT_1;
            end

            DETECT_1: begin
                if (!data) next_state = IDLE;
                else next_state = DETECT_11;
            end

            DETECT_11: begin
                if (!data) next_state = IDLE;
                else next_state = DETECT_110;
            end

            DETECT_110: begin
                if (data) next_state = DETECT_1101;
                else next_state = IDLE;
            end

            DETECT_1101: begin
                if (!data) next_state = LOAD_DELAY;
                else next_state = IDLE;
            end

            LOAD_DELAY: begin
                next_state = COUNTING;
            end

            COUNTING: begin
                counting = 1;
                if (cycle_count == 13'd0) begin
                    done = 1;
                    next_state = WAIT_ACK;
                end
            end

            WAIT_ACK: begin
                done = 1;
                if (ack) next_state = IDLE;
            end

            default: begin
                next_state = IDLE;
            end
        endcase
    end

    // Timer count and shift logic
    always @(posedge clk) begin
        if (reset) begin
            delay <= 4'b0;
            remaining_time <= 4'b0;
            cycle_count <= 13'd0;
        end else begin
            case (state)
                DETECT_1101: begin
                    delay <= {delay[2:0], data}; // Shift in the next 4 bits as delay
                    remaining_time <= delay;
                end

                LOAD_DELAY: begin
                    cycle_count <= (delay + 4'b1) * 13'd1000;
                    remaining_time <= delay;
                end

                COUNTING: begin
                    if (cycle_count != 13'd0) begin
                        cycle_count <= cycle_count - 1;
                        if (cycle_count[9:0] == 10'd0) begin
                            if (remaining_time != 4'b0) begin
                                remaining_time <= remaining_time - 1;
                            end
                        end
                    end
                end
            endcase
        end
    end

    // Assign count output
    assign count = (counting) ? remaining_time : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State encoding
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        PATTERN_DETECTED = 3'b001,
        LOAD_DELAY = 3'b010,
        COUNTING = 3'b011,
        WAIT_FOR_ACK = 3'b100
    } state_t;

    reg [2:0] current_state, next_state;
    reg [3:0] delay;
    reg [3:0] delay_counter;
    reg [9:0] cycle_counter;
    reg [2:0] pattern_count;

    // State machine
    always @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: begin
                if (pattern_count == 3'b110 && data) begin
                    next_state = PATTERN_DETECTED;
                end else begin
                    next_state = IDLE;
                end
            end
            PATTERN_DETECTED: begin
                next_state = LOAD_DELAY;
            end
            LOAD_DELAY: begin
                if (delay_counter == 4'b1000) begin
                    next_state = COUNTING;
                end else begin
                    next_state = LOAD_DELAY;
                end
            end
            COUNTING: begin
                if (cycle_counter == 10'b0) begin
                    next_state = WAIT_FOR_ACK;
                end else begin
                    next_state = COUNTING;
                end
            end
            WAIT_FOR_ACK: begin
                if (ack) begin
                    next_state = IDLE;
                end else begin
                    next_state = WAIT_FOR_ACK;
                end
            end
            default: next_state = IDLE;
        endcase
    end

    // Output logic and counter updates
    always @(posedge clk) begin
        if (reset) begin
            pattern_count <= 3'b0;
            delay <= 4'b0;
            delay_counter <= 4'b0;
            cycle_counter <= 10'b0;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            case (current_state)
                IDLE: begin
                    done <= 1'b0;
                    counting <= 1'b0;
                    if (data) begin
                        pattern_count <= {pattern_count[1:0], 1'b1};
                    end else begin
                        pattern_count <= {pattern_count[1:0], 1'b0};
                    end
                end
                PATTERN_DETECTED: begin
                    delay_counter <= 4'b0;
                    pattern_count <= 3'b0;
                end
                LOAD_DELAY: begin
                    delay <= {delay[2:0], data};
                    delay_counter <= delay_counter + 1;
                end
                COUNTING: begin
                    counting <= 1'b1;
                    if (cycle_counter == 10'd0) begin
                        delay <= delay - 1;
                        cycle_counter <= 10'd999;
                    end else begin
                        cycle_counter <= cycle_counter - 1;
                    end
                    if (delay == 4'b0 && cycle_counter == 10'd0) begin
                        counting <= 1'b0;
                        done <= 1'b1;
                    end
                end
                WAIT_FOR_ACK: begin
                    if (ack) begin
                        done <= 1'b0;
                    end
                end
            endcase
        end
    end

    assign count = counting ? delay : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        DETECT_PATTERN = 3'b001,
        LOAD_DELAY = 3'b010,
        COUNT_DELAY = 3'b011,
        WAIT_ACK = 3'b100
    } state_t;

    reg [2:0] state, next_state;
    reg [3:0] shift_reg;
    reg [9:0] count_reg;
    reg [3:0] delay_reg, delay_counter;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            shift_reg <= 4'b0000;
            count_reg <= 10'b0000000000;
            delay_reg <= 4'b0000;
            counting <= 1'b0;
            done <= 1'b0;
        end else begin
            state <= next_state;

            // State Actions
            case (state)
                IDLE: begin
                    // Reset values
                    counting <= 1'b0;
                    done <= 1'b0;
                end

                DETECT_PATTERN: begin
                    // Shift in data
                    shift_reg <= {shift_reg[2:0], data};
                end

                LOAD_DELAY: begin
                    // Shift in delay duration
                    shift_reg <= {shift_reg[2:0], data};
                end

                COUNT_DELAY: begin
                    // Count down delay counter and 1000 clock cycles
                    if (count_reg == 10'd0) begin
                        if (delay_counter == 4'b0000) begin
                            // Timer is done
                            done <= 1'b1;
                            counting <= 1'b0;
                        end else begin
                            // Decrement delay counter
                            delay_counter <= delay_counter - 4'b0001;
                            count_reg <= 10'd999; // 1000 cycles per delay step
                        end
                    end else begin
                        count_reg <= count_reg - 10'b0000000001;
                    end
                end

                WAIT_ACK: begin
                    if (ack) begin
                        done <= 1'b0;
                    end
                end
            endcase
        end
    end

    always @(*) begin
        next_state = state; // Default to stay in current state

        case (state)
            IDLE: begin
                if (reset == 1'b0) begin
                    next_state = DETECT_PATTERN;
                end
            end

            DETECT_PATTERN: begin
                if (shift_reg == 4'b1101) begin
                    next_state = LOAD_DELAY;
                    shift_reg = 4'b0000; // Clear the shift register for loading delay
                end
            end

            LOAD_DELAY: begin
                if (&shift_reg) begin // If 4 bits have been shifted in
                    delay_reg = shift_reg; // Store the delay
                    delay_counter = shift_reg; // Initialize delay counter
                    count_reg = 10'd999; // Start 1000-cycle countdown
                    next_state = COUNT_DELAY;
                    counting = 1'b1;
                end
            end

            COUNT_DELAY: begin
                if (done) begin
                    next_state = WAIT_ACK;
                end
            end

            WAIT_ACK: begin
                if (ack) begin
                    next_state = IDLE; // After acknowledgment, go back to IDLE
                end
            end
        endcase
    end

    // Assign current remaining time as count output
    assign count = (counting) ? delay_counter : 4'bx;

endmodule

module top_module(
	input wire clk,
	input wire reset,
	input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State Encoding
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        CHECK_PATTERN = 3'b001,
        LOAD_DELAY = 3'b010,
        COUNT = 3'b011,
        DONE = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [3:0] delay;
    reg [9:0] cycle_count;
    reg [3:0] bit_count;
    reg [3:0] temp_count;

    // Sequential Logic for State Transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    // Combinational Logic for Next State and Outputs
    always @(*) begin
        // Default values
        next_state = current_state;
        done = 1'b0;
        counting = 1'b0;

        case (current_state)
            IDLE: begin
                // Start pattern detection
                if (data == 1) begin
                    bit_count <= 0;
                    temp_count <= 4'b1101;
                    next_state = CHECK_PATTERN;
                end
            end
            CHECK_PATTERN: begin
                if (data == temp_count[bit_count]) begin
                    bit_count = bit_count + 1;
                    if (bit_count == 3) next_state = LOAD_DELAY;
                end else begin
                    next_state = IDLE;
                end
            end
            LOAD_DELAY: begin
                delay[3 - bit_count] = data;
                bit_count = bit_count + 1;
                if (bit_count == 4) begin
                    cycle_count = 10'd0;
                    next_state = COUNT;
                end
            end
            COUNT: begin
                counting = 1'b1;
                if (cycle_count < (delay + 1) * 1000) begin
                    cycle_count = cycle_count + 1;
                end else begin
                    next_state = DONE;
                end
            end
            DONE: begin
                done = 1'b1;
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

    // Output logic for count
    assign count = counting ? delay - (cycle_count / 1000) : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state, next_state;
    reg [3:0] delay, delay_reg;
    reg [3:0] shift_reg;
    reg [9:0] cycle_counter;
    reg [2:0] bit_counter;

    // State encoding
    localparam S_IDLE = 4'd0;
    localparam S_DET1 = 4'd1;
    localparam S_DET2 = 4'd2;
    localparam S_DET3 = 4'd3;
    localparam S_DET4 = 4'd4;
    localparam S_DELAY = 4'd5;
    localparam S_COUNT = 4'd6;
    localparam S_DONE  = 4'd7;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= S_IDLE;
            cycle_counter <= 10'd0;
            bit_counter <= 3'd0;
            delay <= 4'd0;
            done <= 1'b0;
            counting <= 1'b0;
        end else begin
            state <= next_state;
            if (state == S_DELAY) begin
                shift_reg <= {shift_reg[2:0], data};
                if (bit_counter < 3'd4) begin
                    bit_counter <= bit_counter + 1'b1;
                end else begin
                    delay <= {shift_reg[2:0], data};
                end
            end
            if (state == S_COUNT) begin
                if (cycle_counter > 10'd0) begin
                    cycle_counter <= cycle_counter - 1'b1;
                end
            end
        end
    end

    always @(*) begin
        next_state = state;
        done = 1'b0;
        counting = 1'b0;
        case (state)
            S_IDLE: begin
                if (data == 1'b1) next_state = S_DET1;
            end
            S_DET1: begin
                if (data == 1'b1) next_state = S_DET2;
                else next_state = S_IDLE;
            end
            S_DET2: begin
                if (data == 1'b0) next_state = S_DET3;
                else next_state = S_IDLE;
            end
            S_DET3: begin
                if (data == 1'b1) next_state = S_DET4;
                else next_state = S_IDLE;
            end
            S_DET4: begin
                next_state = S_DELAY;
                bit_counter = 3'd0;
            end
            S_DELAY: begin
                if (bit_counter == 3'd4) begin
                    delay_reg = delay;
                    cycle_counter = (delay + 4'b0001) * 10'd1000;
                    next_state = S_COUNT;
                end
            end
            S_COUNT: begin
                counting = 1'b1;
                if (cycle_counter == 10'd0) begin
                    done = 1'b1;
                    next_state = S_DONE;
                end
            end
            S_DONE: begin
                done = 1'b1;
                if (ack == 1'b1) next_state = S_IDLE;
            end
        endcase
    end

    assign count = delay_reg - cycle_counter / 10'd1000;

endmodule

module top_module(
	input wire clk,
	input wire reset,
	input wire data,
	output reg [3:0] count,
	output reg counting,
	output reg done,
	input wire ack
);

    reg [3:0] state;
    reg [3:0] bit_count;
    reg [3:0] delay;
    reg [15:0] cycle_count;

    localparam IDLE = 4'b0000;
    localparam SHIFT_PATTERN = 4'b0001;
    localparam LOAD_DELAY = 4'b0010;
    localparam COUNTING = 4'b0011;
    localparam NOTIFY = 4'b0100;

    always @(posedge clk) begin
        if(reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            bit_count <= 0;
            count <= 4'bxxxx;
            delay <= 0;
            cycle_count <= 0;
        end else begin
            case(state)
                IDLE: begin
                    done <= 0;
                    if(data == 1'b1) begin
                        bit_count <= bit_count + 1;
                        state <= (bit_count == 3) ? SHIFT_PATTERN : IDLE;
                    end else begin
                        bit_count <= 0;
                    end
                end

                SHIFT_PATTERN: begin
                    if(bit_count < 4) begin
                        bit_count <= bit_count + 1;
                    end else begin
                        state <= LOAD_DELAY;
                        bit_count <= 0;
                    end
                end

                LOAD_DELAY: begin
                    delay <= {delay[2:0], data};
                    bit_count <= bit_count + 1;
                    if(bit_count == 3) begin
                        counting <= 1;
                        cycle_count <= (({delay[2:0], data} + 1) * 1000) - 1;
                        count <= delay;
                        state <= COUNTING;
                        bit_count <= 0;
                    end
                end

                COUNTING: begin
                    if(cycle_count > 0) begin
                        cycle_count <= cycle_count - 1;
                        if(cycle_count[9:0] == 0) begin
                            count <= (count == 0) ? 0 : count - 1;
                        end
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= NOTIFY;
                    end
                end

                NOTIFY: begin
                    if(ack) begin
                        state <= IDLE;
                    end
                end
            endcase
        end
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    // State definitions
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        MATCH_1101 = 3'b001,
        READ_DELAY = 3'b010,
        COUNTING = 3'b011,
        WAIT_ACK = 3'b100
    } state_t;

    state_t state, next_state;
    reg [3:0] delay;
    reg [2:0] bit_counter;
    reg [11:0] cycle_counter;

    // Sequential logic for state transitions
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Sequential logic for cycle_counter and delay counters
    always @(posedge clk) begin
        if (reset) begin
            cycle_counter <= 12'd0;
            bit_counter <= 3'd0;
            delay <= 4'd0;
        end else begin
            case (state)
                READ_DELAY: begin
                    if (bit_counter < 3'd4) begin
                        // Shift the incoming bits
                        delay <= {delay[2:0], data};
                        bit_counter <= bit_counter + 1;
                    end
                end
                COUNTING: begin
                    if (cycle_counter < 12'd1000) begin
                        cycle_counter <= cycle_counter + 1;
                    end else begin
                        cycle_counter <= 12'd0;
                        if (count > 0) begin
                            count <= count - 1;
                        end
                    end
                end
            endcase
        end
    end

    // Combinational logic for next_state and output control
    always @(*) begin
        // Default assignments
        done = 0;
        counting = 0;
        count = delay;
        next_state = state;

        case (state)
            IDLE: begin
                if (data == 1'b1) begin
                    next_state = MATCH_1101;
                    bit_counter = 3'd0;
                end
            end
            MATCH_1101: begin
                if (bit_counter == 3'd3) begin
                    if ({1'b1, data} == 4'b1101) begin
                        next_state = READ_DELAY;
                        bit_counter = 3'd0;
                    end else begin
                        next_state = IDLE;
                    end
                end else begin
                    bit_counter = bit_counter + 1;
                end
            end
            READ_DELAY: begin
                if (bit_counter == 3'd4) begin
                    next_state = COUNTING;
                    cycle_counter = 12'd0;
                    count = delay;
                end
            end
            COUNTING: begin
                counting = 1;
                if (count == 4'd0 && cycle_counter == 12'd999) begin
                    done = 1;
                    next_state = WAIT_ACK;
                end
            end
            WAIT_ACK: begin
                done = 1;
                if (ack) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

    // State declarations
    typedef enum reg [2:0] {
        IDLE,
        DETECT,
        LOAD_DELAY,
    COUNTDOWN,
        WAIT_ACK
    } state_t;
    state_t state, next_state;

    reg [3:0] delay;
    reg [14:0] cycle_count; // To count up to (delay + 1) * 1000 cycles

    // State machine: State transition
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // State machine: Next state logic
    always @(*) begin
        case (state)
            IDLE:
                if (reset)
                    next_state = DETECT;
                else
                    next_state = IDLE;
            DETECT:
                if ({data, delay[3:1]} == 4'b1101)  // Serially detect '1101'
                    next_state = LOAD_DELAY;
                else
                    next_state = DETECT;
            LOAD_DELAY:
                if (&delay[2:0])  // After 4 bits of delay are loaded
                    next_state = COUNTDOWN;
                else
                    next_state = LOAD_DELAY;
            COUNTDOWN:
                if (cycle_count == 0)
                    next_state = WAIT_ACK;
                else
                    next_state = COUNTDOWN;
            WAIT_ACK:
                if (ack)
                    next_state = DETECT;
                else
                    next_state = WAIT_ACK;
            default: next_state = IDLE;
        endcase
    end

    // State machine: Output logic and data path
    always @(posedge clk) begin
        if (reset) begin
            delay <= 4'b0;
            cycle_count <= 15'b0;
            done <= 0;
            counting <= 0;
        end else begin
            case (state)
                IDLE: begin
                    delay <= 4'b0;
                    cycle_count <= 15'b0;
                    counting <= 0;
                    done <= 0;
                end
                DETECT: begin
                    // Shift in data serially
                    delay <= {delay[2:0], data};
                end
                LOAD_DELAY: begin
                    // Perform no operation in terms of delay loading
                end
                COUNTDOWN: begin
                    counting <= 1;
                    if (cycle_count == 0) begin
                        done <= 1;
                        counting <= 0;
                    end else begin
                        cycle_count <= cycle_count - 1;
                    end
                end
                WAIT_ACK: begin
                    if (ack) begin
                        done <= 0;
                        // Reset to ready for next detection
                    end
                end
            endcase
        end
    end

    // Count logic
    always @(posedge clk) begin
        if (reset) begin
            count <= 4'bx;
        end else if (state == COUNTDOWN) begin
            count <= cycle_count / 1000; // Remaining time divided by 1000
        end else begin
            count <= 4'bx; // Don't care
        end
    end

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state, next_state;
    reg [3:0] shift_reg;
    reg [13:0] counter;
    reg [3:0] delay;

    localparam IDLE      = 4'd0;
    localparam PATTERN   = 4'd1;
    localparam LOAD      = 4'd2;
    localparam COUNT     = 4'd3;
    localparam DONE      = 4'd4;

    // Combinational logic for next state
    always @(*) begin
        next_state = state; // Default is to stay in the current state
        case (state)
            IDLE: begin
                if (reset || ack)
                    next_state = PATTERN;
            end
            PATTERN: begin
                if (shift_reg[3:0] == 4'b1101)
                    next_state = LOAD;
            end
            LOAD: begin
                next_state = COUNT;
            end
            COUNT: begin
                if (counter == 0)
                    next_state = DONE;
            end
            DONE: begin
                if (ack)
                    next_state = PATTERN;
            end
        endcase
    end

    // Sequential logic for state transition and outputs
    always @(posedge clk) begin
        if (reset) begin
            state <= PATTERN;
            shift_reg <= 4'b0;
            counting <= 0;
            done <= 0;
        end else begin
            state <= next_state;
            case (state)
                PATTERN: begin
                    shift_reg <= {shift_reg[2:0], data};
                    if (shift_reg[3:0] == 4'b1101) begin
                        delay <= shift_reg[3:0];
                    end
                end
                LOAD: begin
                    counting <= 1;
                    counter <= (delay + 1) * 1000;
                end
                COUNT: begin
                    if (counter > 0) begin
                        counter <= counter - 1;
                    end else begin
                        counting <= 0;
                    end
                end
                DONE: begin
                    done <= 1;
                    if (ack) begin
                        done <= 0;
                    end
                end
            endcase
        end
    end

    // Output count logic
    assign count = counter[13:10];

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] state, next_state;
    reg [3:0] shift_reg;
    reg [3:0] delay;
    reg [13:0] count_cycles;
    reg [9:0] delay_counter;
    reg [3:0] rem_count;

    localparam IDLE = 4'd0,
               DETECT_1 = 4'd1,
               DETECT_11 = 4'd2,
               DETECT_110 = 4'd3,
               DETECT_1101 = 4'd4,
               LOAD_DELAY = 4'd5,
               COUNT = 4'd6,
               WAIT_ACK = 4'd7;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            count_cycles <= 0;
            delay_counter <= 0;
            shift_reg <= 4'b0;
            rem_count <= 4'b0;
        end else begin
            state <= next_state;
            if (state == LOAD_DELAY) begin
                delay <= shift_reg;
            end
            if (state == COUNT) begin
                count_cycles <= (delay + 4'd1) * 10'd1000;
                rem_count <= delay;
            end else if (count_cycles != 14'd0) begin
                count_cycles <= count_cycles - 1'b1;
                if (delay_counter == 10'd999) begin
                    delay_counter <= 10'd0;
                    if (rem_count != 0)
                        rem_count <= rem_count - 4'b1;
                end else begin
                    delay_counter <= delay_counter + 1'b1;
                end
            end
        end
    end

    always @(*) begin
        next_state = state;
        counting = 1'b0;
        done = 1'b0;
        case (state)
            IDLE: begin
                if (data == 1'b1) next_state = DETECT_1;
            end
            DETECT_1: begin
                if (data == 1'b1) next_state = DETECT_11;
                else next_state = IDLE;
            end
            DETECT_11: begin
                if (data == 1'b0) next_state = DETECT_110;
                else next_state = IDLE;
            end
            DETECT_110: begin
                if (data == 1'b1) next_state = DETECT_1101;
                else next_state = IDLE;
            end
            DETECT_1101: begin
                shift_reg <= {shift_reg[2:0], data};
                next_state = LOAD_DELAY;
            end
            LOAD_DELAY: begin
                next_state = COUNT;
            end
            COUNT: begin
                counting = 1'b1;
                if (count_cycles == 14'd0) next_state = WAIT_ACK;
            end
            WAIT_ACK: begin
                done = 1'b1;
                if (ack == 1'b1) next_state = IDLE;
            end
        endcase
    end

    assign count = (state == COUNT) ? rem_count : 4'bx;

endmodule