module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    reg [2:0] state, next_state;

    // State encoding
    localparam LOW    = 3'b000,
               MIDLOW = 3'b001,
               MIDHI  = 3'b010,
               HIGH   = 3'b011;

    // State transition logic
    always @(*) begin
        case (state)
            HIGH: begin
                if (s == 3'b110)
                    next_state = MIDHI;
                else if (s == 3'b100)
                    next_state = MIDLOW;
                else if (s == 3'b000)
                    next_state = LOW;
                else
                    next_state = HIGH;
            end
            MIDHI: begin
                if (s == 3'b111)
                    next_state = HIGH;
                else if (s == 3'b100)
                    next_state = MIDLOW;
                else if (s == 3'b000)
                    next_state = LOW;
                else
                    next_state = MIDHI;
            end
            MIDLOW: begin
                if (s == 3'b111)
                    next_state = HIGH;
                else if (s == 3'b110)
                    next_state = MIDHI;
                else if (s == 3'b000)
                    next_state = LOW;
                else
                    next_state = MIDLOW;
            end
            LOW: begin
                if (s == 3'b111)
                    next_state = HIGH;
                else if (s == 3'b110)
                    next_state = MIDHI;
                else if (s == 3'b100)
                    next_state = MIDLOW;
                else
                    next_state = LOW;
            end
            default: next_state = LOW;
        endcase
    end

    // Output logic based on state
    always @(*) begin
        fr1 = 0;
        fr2 = 0;
        fr3 = 0;
        dfr = 0;
        case (state)
            HIGH: begin
                // No flow rates once water is above the highest sensor
            end
            MIDHI: begin
                fr1 = 1;  // Normal flow for between s[3] and s[2]
            end
            MIDLOW: begin
                fr1 = 1;
                fr2 = 1;  // Both fr1 and fr2 for between s[2] and s[1]
            end
            LOW: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;  // All flows for below s[1]
                dfr = 1;  // Open the supplemental flow valve
            end
        endcase
    end

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= LOW;  // Reset to LOW state
        else
            state <= next_state;
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	// State encoding
	localparam [1:0] LOW = 2'b00, MID_LOW = 2'b01, MID_HIGH = 2'b10, HIGH = 2'b11;

	reg [1:0] current_state, next_state;

	// State transition
	always @(posedge clk or posedge reset) begin
		if (reset)
			current_state <= LOW;
		else
			current_state <= next_state;
	end

	// Next state logic
	always @(*) begin
		case (current_state)
			LOW: begin
				if (s[3] && s[2] && s[1])
					next_state = HIGH;
				else if (s[2] && s[1])
					next_state = MID_HIGH;
				else if (s[1])
					next_state = MID_LOW;
				else
					next_state = LOW;
			end
			MID_LOW: begin
				if (s[3] && s[2])
					next_state = HIGH;
				else if (s[2])
					next_state = MID_HIGH;
				else
					next_state = LOW;
			end
			MID_HIGH: begin
				if (s[3] && s[2] && s[1])
					next_state = HIGH;
				else if (!s[2])
					next_state = MID_LOW;
				else
					next_state = MID_HIGH;
			end
			HIGH: begin
				if (!s[3])
					next_state = MID_HIGH;
				else
					next_state = HIGH;
			end
			default: next_state = LOW;
		endcase
	end

	// Output logic
	always @(*) begin
		// Default outputs
		fr3 = 0;
		fr2 = 0;
		fr1 = 0;
		dfr = 0;
		case (current_state)
			LOW: begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 1;
			end
			MID_LOW: begin
				fr2 = 1;
				fr1 = 1;
				dfr = ~s[2];  // Increase flow if previous was lower.
			end
			MID_HIGH: begin
				fr1 = 1;
				dfr = ~s[3];  // Increase flow if previous was lower.
			end
			HIGH: begin
				// No flow control asserted.
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State definitions
    typedef enum reg [1:0] {
        LOW = 2'b00,
        MID = 2'b01,
        HIGH = 2'b10,
        ABOVE = 2'b11
    } state_t;

    state_t current_state, next_state;
    reg prev_level_higher;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= LOW;
            {fr3, fr2, fr1, dfr} <= 4'b1111;
            prev_level_higher <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @* begin
        // Default output values
        {fr3, fr2, fr1, dfr} = 4'b0000;
        next_state = current_state;

        case (current_state)
            LOW: begin
                {fr3, fr2, fr1} = 3'b111;
                if (s[1]) begin
                    next_state = MID;
                end
            end

            MID: begin
                {fr2, fr1} = 2'b11;
                if (s[2]) begin
                    next_state = HIGH;
                end else if (!s[1]) begin
                    next_state = LOW;
                end
            end

            HIGH: begin
                fr1 = 1'b1;
                if (s[3]) begin
                    next_state = ABOVE;
                end else if (!s[2]) begin
                    next_state = MID;
                end
            end

            ABOVE: begin
                if (!s[3]) begin
                    next_state = HIGH;
                end
            end
        endcase

        // Check for previous level change to manage dfr
        if (next_state == HIGH && current_state == MID) begin
            dfr = prev_level_higher;
            prev_level_higher = 1;
        end else if (next_state == MID && current_state == LOW) begin
            dfr = prev_level_higher;
            prev_level_higher = 1;
        end else begin
            prev_level_higher = 0;
        end
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding
    typedef enum reg [1:0] {
        LOW = 2'b00,
        BETWEEN_LOW_MID = 2'b01,
        BETWEEN_MID_HIGH = 2'b10,
        HIGH = 2'b11
    } state_t;

    state_t current_state, next_state;
    reg previous_increase;

    // State transition and output logic
    always @(*) begin
        // Default output values
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = previous_increase;

        case (current_state)
            LOW: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1;
                if (s[1]) next_state = BETWEEN_LOW_MID;
                else next_state = LOW;
            end

            BETWEEN_LOW_MID: begin
                fr2 = 1;
                fr1 = 1;
                if (s[2]) begin
                    next_state = BETWEEN_MID_HIGH;
                    dfr = (previous_increase == 0) ? 1 : 0;
                end else if (~s[1]) begin
                    next_state = LOW;
                end else begin
                    next_state = BETWEEN_LOW_MID;
                end
            end

            BETWEEN_MID_HIGH: begin
                fr1 = 1;
                if (s[3]) begin
                    next_state = HIGH;
                end else if (~s[2]) begin
                    next_state = BETWEEN_LOW_MID;
                end else begin
                    next_state = BETWEEN_MID_HIGH;
                end
            end

            HIGH: begin
                dfr = 0;
                if (~s[3]) next_state = BETWEEN_MID_HIGH;
                else next_state = HIGH;
            end
        endcase
    end

    // Sequential state update
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= LOW;
            previous_increase <= 0;
        end else begin
            if (next_state > current_state)
                previous_increase <= 1;
            else if (next_state < current_state)
                previous_increase <= 0;
            current_state <= next_state;
        end
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

    reg [1:0] prev_level;

    // State encoding
    localparam [1:0] ABOVE_S3 = 2'b11,
                     BETWEEN_S3_S2 = 2'b10,
                     BETWEEN_S2_S1 = 2'b01,
                     BELOW_S1 = 2'b00;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            {fr3, fr2, fr1, dfr} <= 4'b1111;
            prev_level <= BELOW_S1;
        end else begin
            casez (s)
                3'b111: begin // Above s[3]
                    {fr3, fr2, fr1, dfr} <= 4'b0000;
                    prev_level <= ABOVE_S3;
                end
                3'b011: begin // Between s[3] and s[2]
                    {fr3, fr2, fr1} <= 3'b001;
                    dfr <= (prev_level != BETWEEN_S3_S2);
                    prev_level <= BETWEEN_S3_S2;
                end
                3'b001: begin // Between s[2] and s[1]
                    {fr3, fr2, fr1} <= 3'b011;
                    dfr <= (prev_level == BELOW_S1 || prev_level == BETWEEN_S3_S2);
                    prev_level <= BETWEEN_S2_S1;
                end
                3'b000: begin // Below s[1]
                    {fr3, fr2, fr1, dfr} <= 4'b1111;
                    prev_level <= BELOW_S1;
                end
                default: begin
                    {fr3, fr2, fr1, dfr} <= 4'b0000; // Default to safe state
                end
            endcase
        end
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    typedef enum reg [1:0] {
        HIGH = 2'b11,      // Sensors s[1], s[2], s[3] asserted
        MID_HIGH = 2'b10,  // Sensors s[1], s[2] asserted
        MID_LOW = 2'b01,   // Sensor s[1] asserted
        LOW = 2'b00        // No sensors asserted
    } state_t;

    reg [1:0] current_state, next_state;
    reg previous_rising;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= LOW; // Reset to LOW state
            previous_rising <= 1'b0;
        end else begin
            current_state <= next_state;
            previous_rising <= (s > current_state); // Track rising edge
        end
    end

    always @(*) begin
        // Default outputs
        fr1 = 1'b0;
        fr2 = 1'b0;
        fr3 = 1'b0;
        dfr = 1'b0;

        case (current_state)
            HIGH: begin
                next_state = (s == 3'b111) ? HIGH : MID_HIGH;
            end
            MID_HIGH: begin
                fr1 = 1'b1;
                next_state = (s[3] == 1'b0) ? MID_LOW : MID_HIGH;
            end
            MID_LOW: begin
                fr1 = 1'b1;
                fr2 = 1'b1;
                next_state = (s[2] == 1'b0) ? LOW : MID_LOW;
            end
            LOW: begin
                fr1 = 1'b1;
                fr2 = 1'b1;
                fr3 = 1'b1;
                dfr = 1'b1;
                next_state = (s[1] == 1'b1) ? MID_LOW : LOW;
            end
        endcase

        // Supplemental flow rate control
        if (previous_rising && (current_state != LOW) && (current_state != HIGH)) begin
            dfr = 1'b1;
        end
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding
    typedef enum logic [1:0] {
        LOW = 2'b00,
        BETWEEN_S1_S2 = 2'b01,
        BETWEEN_S2_S3 = 2'b10,
        ABOVE_S3 = 2'b11
    } state_t;

    state_t current_state, next_state;
    state_t previous_state;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= LOW;
            previous_state <= LOW;
        end else begin
            current_state <= next_state;
            previous_state <= current_state;
        end
    end

    // Next state logic
    always_comb begin
        case (s)
            3'b111: next_state = ABOVE_S3;
            3'b011: next_state = BETWEEN_S2_S3;
            3'b001: next_state = BETWEEN_S1_S2;
            default: next_state = LOW;
        endcase
    end

    // Output logic
    always_comb begin
        // Default values
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;

        case (current_state)
            ABOVE_S3: begin
                // No flow rates asserted
            end
            BETWEEN_S2_S3: begin
                fr1 = 1;
                if (previous_state == LOW || previous_state == BETWEEN_S1_S2) begin
                    dfr = 1; // Supplemental flow due to level increase
                end
            end
            BETWEEN_S1_S2: begin
                fr1 = 1;
                fr2 = 1;
                if (previous_state == LOW) begin
                    dfr = 1; // Supplemental flow due to level increase
                end
            end
            LOW: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;
                dfr = 1;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_LOW  = 2'b00, // Below s[1]
        STATE_MID1 = 2'b01, // Between s[2] and s[1]
        STATE_MID2 = 2'b10, // Between s[3] and s[2]
        STATE_HIGH = 2'b11  // Above s[3]
    } state_t;

    reg [1:0] current_state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            // Reset to the state where no sensors are asserted
            current_state <= STATE_LOW;
            fr1 <= 1'b1;
            fr2 <= 1'b1;
            fr3 <= 1'b1;
            dfr <= 1'b1;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        // Default outputs
        fr1 = 1'b0;
        fr2 = 1'b0;
        fr3 = 1'b0;
        dfr = 1'b0;

        case (current_state)
            STATE_LOW: begin
                fr1 = 1'b1;
                fr2 = 1'b1;
                fr3 = 1'b1;
                dfr = 1'b0;
                if (s == 3'b001)
                    next_state = STATE_MID1;
                else
                    next_state = STATE_LOW;
            end
            STATE_MID1: begin
                fr1 = 1'b1;
                fr2 = 1'b1;
                dfr = (s == 3'b111 || s == 3'b011) ? 1'b1 : 1'b0;
                if (s == 3'b011)
                    next_state = STATE_MID2;
                else if (s == 3'b000)
                    next_state = STATE_LOW;
                else
                    next_state = STATE_MID1;
            end
            STATE_MID2: begin
                fr1 = 1'b1;
                dfr = (s == 3'b111 && current_state == STATE_MID1) ? 1'b1 : 1'b0;
                if (s == 3'b111)
                    next_state = STATE_HIGH;
                else if (s == 3'b001)
                    next_state = STATE_MID1;
                else
                    next_state = STATE_MID2;
            end
            STATE_HIGH: begin
                fr1 = 1'b0;
                fr2 = 1'b0;
                fr3 = 1'b0;
                dfr = 1'b0;
                if (s != 3'b111)
                    next_state = (s == 3'b011) ? STATE_MID2 : (s == 3'b001) ? STATE_MID1 : STATE_LOW;
                else
                    next_state = STATE_HIGH;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // state encoding
    typedef enum logic [1:0] {
        LOW = 2'b00,        // Below s[1]
        MID_LOW = 2'b01,    // Between s[2] and s[1]
        MID_HIGH = 2'b10,   // Between s[3] and s[2]
        HIGH = 2'b11        // Above s[3]
    } state_t;

    state_t current_state, next_state;
    reg prev_up; // to track the direction of the last sensor change

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= LOW;
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 1;
            prev_up <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        // default outputs
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;

        next_state = current_state;

        case (current_state)
            LOW: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1;
                if (s == 3'b001)
                    next_state = MID_LOW;
                else if (s == 3'b011)
                    next_state = MID_HIGH;
                else if (s == 3'b111)
                    next_state = HIGH;
            end

            MID_LOW: begin
                fr2 = 1;
                fr1 = 1;
                if (prev_up) dfr = 1;
                if (s == 3'b000)
                    next_state = LOW;
                else if (s == 3'b011)
                    next_state = MID_HIGH;
                else if (s == 3'b111)
                    next_state = HIGH;
            end

            MID_HIGH: begin
                fr1 = 1;
                if (prev_up) dfr = 1;
                if (s == 3'b001)
                    next_state = MID_LOW;
                else if (s == 3'b000)
                    next_state = LOW;
                else if (s == 3'b111)
                    next_state = HIGH;
            end

            HIGH: begin
                // no flow
                if (s == 3'b011)
                    next_state = MID_HIGH;
                else if (s == 3'b001)
                    next_state = MID_LOW;
                else if (s == 3'b000)
                    next_state = LOW;
            end
        endcase

        // Update prev_up flag based on sensor change
        if (s > {1'b0, s[3:2]} || s > {2'b00, s[3]})
            prev_up = 1;
        else if (s < {1'b0, s[3:2]} || s < {2'b00, s[3]})
            prev_up = 0;
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State Encoding
    typedef enum reg [1:0] {
        LOW_LEVEL = 2'b00,
        BETWEEN_S1_S2 = 2'b01,
        BETWEEN_S2_S3 = 2'b10,
        ABOVE_S3 = 2'b11
    } state_t;

    // State Registers
    reg state, next_state;

    // Previous Sensors State
    reg [3:1] prev_s;

    // State Transition Logic
    always @(*) begin
        case (state)
            LOW_LEVEL: begin
                if (s[1]) next_state = BETWEEN_S1_S2;
                else next_state = LOW_LEVEL;
            end
            BETWEEN_S1_S2: begin
                if (s[2]) next_state = BETWEEN_S2_S3;
                else if (!s[1]) next_state = LOW_LEVEL;
                else next_state = BETWEEN_S1_S2;
            end
            BETWEEN_S2_S3: begin
                if (s[3]) next_state = ABOVE_S3;
                else if (!s[2]) next_state = BETWEEN_S1_S2;
                else next_state = BETWEEN_S2_S3;
            end
            ABOVE_S3: begin
                if (!s[3]) next_state = BETWEEN_S2_S3;
                else next_state = ABOVE_S3;
            end
            default: next_state = LOW_LEVEL;
        endcase
    end

    // Sequential State Update
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW_LEVEL;
            prev_s <= 3'b000;
        end else begin
            state <= next_state;
            prev_s <= s;
        end
    end

    // Output Logic
    always @(*) begin
        // Default output values
        {fr3, fr2, fr1, dfr} = 4'b0000;

        case (state)
            LOW_LEVEL: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1;
            end
            BETWEEN_S1_S2: begin
                fr1 = 1;
                fr2 = 1;
                if (prev_s[1] != s[1]) // If the level is increasing
                    dfr = 1;
            end
            BETWEEN_S2_S3: begin
                fr1 = 1;
                if (prev_s[2] != s[2]) // If the level is increasing
                    dfr = 1;
            end
            ABOVE_S3: begin
                // No flow rate is set, all remain 0
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    typedef enum logic [1:0] {
        LOW    = 2'b00,
        MID    = 2'b01,
        HIGH   = 2'b10,
        FULL   = 2'b11
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            LOW: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;
                dfr = 1;
                case (s)
                    3'b000: next_state = LOW;
                    3'b001: next_state = MID;
                    default: next_state = LOW;
                endcase
            end
            MID: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 0;
                if (s == 3'b011) begin
                    next_state = HIGH;
                    dfr = 1;
                end else begin
                    next_state = MID;
                    dfr = 0;
                end
            end
            HIGH: begin
                fr1 = 1;
                fr2 = 0;
                fr3 = 0;
                if (s == 3'b111) begin
                    next_state = FULL;
                    dfr = 1;
                end else begin
                    next_state = HIGH;
                    dfr = 0;
                end
            end
            FULL: begin
                fr1 = 0;
                fr2 = 0;
                fr3 = 0;
                dfr = 0;
                if (s == 3'b110) begin
                    next_state = HIGH;
                end else begin
                    next_state = FULL;
                end
            end
            default: begin
                next_state = LOW;
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;
                dfr = 1;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    typedef enum reg [1:0] {
        ABOVE_S3 = 2'b00,
        BETWEEN_S3_S2 = 2'b01,
        BETWEEN_S2_S1 = 2'b10,
        BELOW_S1 = 2'b11
    } state_t;

    state_t state, next_state;
    reg last_s2, last_s1;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= BELOW_S1;
            last_s2 <= 0;
            last_s1 <= 0;
        end else begin
            state <= next_state;
            if (s[2]) last_s2 <= 1;
            if (s[1]) last_s1 <= 1;
        end
    end

    always @(*) begin
        fr1 = 0;
        fr2 = 0;
        fr3 = 0;
        dfr = 0;
        case (state)
            ABOVE_S3: begin
                if (!s[3]) begin
                    if (s[2]) next_state = BETWEEN_S3_S2;
                    else next_state = BETWEEN_S2_S1;
                end else
                    next_state = ABOVE_S3;
            end
            BETWEEN_S3_S2: begin
                fr1 = 1;
                if (s[3]) next_state = ABOVE_S3;
                else if (!s[2]) begin
                    if (s[1]) next_state = BETWEEN_S2_S1;
                    else next_state = BELOW_S1;
                end else begin
                    next_state = BETWEEN_S3_S2;
                    if (last_s1) dfr = 1;
                end
            end
            BETWEEN_S2_S1: begin
                fr1 = 1;
                fr2 = 1;
                if (s[3]) next_state = ABOVE_S3;
                else if (s[2]) next_state = BETWEEN_S3_S2;
                else if (!s[1]) begin
                    next_state = BELOW_S1;
                end else begin
                    next_state = BETWEEN_S2_S1;
                    if (last_s1) dfr = 1;
                end
            end
            BELOW_S1: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;
                if (s[3]) next_state = ABOVE_S3;
                else if (s[2]) next_state = BETWEEN_S3_S2;
                else if (s[1]) begin
                    next_state = BETWEEN_S2_S1;
                end else
                    next_state = BELOW_S1;
            end
            default: next_state = BELOW_S1;
        endcase
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] prev_state, current_state;

	localparam ABOVE_S3 = 2'd0;
	localparam BETWEEN_S3_S2 = 2'd1;
	localparam BETWEEN_S2_S1 = 2'd2;
	localparam BELOW_S1 = 2'd3;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= BELOW_S1;
			prev_state <= BELOW_S1;
		end else begin
			prev_state <= current_state;
			case (s)
				3'b111: current_state <= ABOVE_S3;
				3'b011: current_state <= BETWEEN_S3_S2;
				3'b001: current_state <= BETWEEN_S2_S1;
				3'b000: current_state <= BELOW_S1;
				default: current_state <= current_state;
			endcase
		end
	end

	always @(*) begin
		{fr3, fr2, fr1, dfr} = 4'b0000; // default value
		case (current_state)
			ABOVE_S3: begin
				{fr3, fr2, fr1, dfr} = 4'b0000;
			end
			BETWEEN_S3_S2: begin
				fr1 = 1'b1;
				if (prev_state < BETWEEN_S3_S2) dfr = 1'b1;
			end
			BETWEEN_S2_S1: begin
				fr1 = 1'b1;
				fr2 = 1'b1;
				if (prev_state < BETWEEN_S2_S1) dfr = 1'b1;
			end
			BELOW_S1: begin
				fr3 = 1'b1;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b1;
			end
			default: begin
				{fr3, fr2, fr1, dfr} = 4'b0000;
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // Define state encoding
    typedef enum logic [1:0] {
        STATE_LOW = 2'b00,       // No sensors asserted, fr1, fr2, fr3, dfr asserted
        STATE_BETWEEN_1_2 = 2'b01, // s[1] asserted, fr1, fr2 asserted
        STATE_BETWEEN_2_3 = 2'b10, // s[1], s[2] asserted, fr1 asserted
        STATE_ABOVE_3 = 2'b11    // s[1], s[2], s[3] asserted, no fr asserted
    } state_t;

    state_t current_state, next_state;
    reg last_level_up;

    // State transition logic
    always @(*) begin
        case (current_state)
            STATE_LOW: begin
                if (s == 3'b000) next_state = STATE_LOW;
                else if (s == 3'b001) next_state = STATE_BETWEEN_1_2;
                else if (s == 3'b011) next_state = STATE_BETWEEN_2_3;
                else if (s == 3'b111) next_state = STATE_ABOVE_3;
            end
            STATE_BETWEEN_1_2: begin
                if (s == 3'b000) next_state = STATE_LOW;
                else if (s == 3'b001) next_state = STATE_BETWEEN_1_2;
                else if (s == 3'b011) next_state = STATE_BETWEEN_2_3;
                else if (s == 3'b111) begin
                    next_state = STATE_ABOVE_3;
                    last_level_up = 1'b1;
                end
            end
            STATE_BETWEEN_2_3: begin
                if (s == 3'b000) next_state = STATE_LOW;
                else if (s == 3'b001) begin
                    next_state = STATE_BETWEEN_1_2;
                    last_level_up = 1'b0;
                end
                else if (s == 3'b011) next_state = STATE_BETWEEN_2_3;
                else if (s == 3'b111) begin
                    next_state = STATE_ABOVE_3;
                    last_level_up = 1'b1;
                end
            end
            STATE_ABOVE_3: begin
                if (s == 3'b000) next_state = STATE_LOW;
                else if (s == 3'b001) begin
                    next_state = STATE_BETWEEN_1_2;
                    last_level_up = 1'b0;
                end
                else if (s == 3'b011) begin
                    next_state = STATE_BETWEEN_2_3;
                    last_level_up = 1'b0;
                end
                else if (s == 3'b111) next_state = STATE_ABOVE_3;
            end
            default: next_state = STATE_LOW;
        endcase
    end

    // Output logic
    always @(*) begin
        fr3 = 1'b0;
        fr2 = 1'b0;
        fr1 = 1'b0;
        dfr = 1'b0;
        case (current_state)
            STATE_LOW: begin
                fr3 = 1'b1;
                fr2 = 1'b1;
                fr1 = 1'b1;
                dfr = 1'b1;
            end
            STATE_BETWEEN_1_2: begin
                fr2 = 1'b1;
                fr1 = 1'b1;
                if (last_level_up)
                    dfr = 1'b1;
            end
            STATE_BETWEEN_2_3: begin
                fr1 = 1'b1;
                if (last_level_up)
                    dfr = 1'b1;
            end
            STATE_ABOVE_3: begin
            end
        endcase
    end

    // State flip-flops
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= STATE_LOW;
            last_level_up <= 1'b0;
        end else begin
            current_state <= next_state;
        end
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    reg [1:0] previous_level;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            fr3 <= 1'b1;
            fr2 <= 1'b1;
            fr1 <= 1'b1;
            dfr <= 1'b1;
            previous_level <= 2'b00;
        end else begin
            case (s)
                3'b111: begin // Above s[3]
                    fr3 <= 1'b0;
                    fr2 <= 1'b0;
                    fr1 <= 1'b0;
                    dfr <= 1'b0;
                    previous_level <= 2'b11;
                end
                3'b011: begin // Between s[3] and s[2]
                    fr3 <= 1'b0;
                    fr2 <= 1'b0;
                    fr1 <= 1'b1;
                    dfr <= (previous_level < 2'b10) ? 1'b1 : 1'b0;
                    previous_level <= 2'b10;
                end
                3'b001: begin // Between s[2] and s[1]
                    fr3 <= 1'b0;
                    fr2 <= 1'b1;
                    fr1 <= 1'b1;
                    dfr <= (previous_level < 2'b01) ? 1'b1 : 1'b0;
                    previous_level <= 2'b01;
                end
                default: begin // Below s[1]
                    fr3 <= 1'b1;
                    fr2 <= 1'b1;
                    fr1 <= 1'b1;
                    dfr <= 1'b1;
                    previous_level <= 2'b00;
                end
            endcase
        end
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] previous_level;

	// State encoding
	localparam LOW = 2'd0;
	localparam BETWEEN_S1_S2 = 2'd1;
	localparam BETWEEN_S2_S3 = 2'd2;
	localparam ABOVE_S3 = 2'd3;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			fr1 <= 1'b1;
			fr2 <= 1'b1;
			fr3 <= 1'b1;
			dfr <= 1'b1;
			previous_level <= LOW;
		end else begin
			case (s)
				3'b111: begin // Above s[3]
					fr1 <= 1'b0;
					fr2 <= 1'b0;
					fr3 <= 1'b0;
					dfr <= 1'b0;
					previous_level <= ABOVE_S3;
				end

				3'b011: begin // Between s[3] and s[2]
					fr1 <= 1'b1;
					fr2 <= 1'b0;
					fr3 <= 1'b0;
					dfr <= (previous_level == BETWEEN_S1_S2) ? 1'b1 : 1'b0;
					previous_level <= BETWEEN_S2_S3;
				end

				3'b001: begin // Between s[2] and s[1]
					fr1 <= 1'b1;
					fr2 <= 1'b1;
					fr3 <= 1'b0;
					dfr <= (previous_level == LOW) ? 1'b1 : 1'b0;
					previous_level <= BETWEEN_S1_S2;
				end

				3'b000: begin // Below s[1]
					fr1 <= 1'b1;
					fr2 <= 1'b1;
					fr3 <= 1'b1;
					dfr <= 1'b1;
					previous_level <= LOW;
				end
			endcase
		end
	end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding for FSM
    typedef enum logic [1:0] {
        LOW_WATER = 2'b00,          // Below s[1]
        BETWEEN_S1_S2 = 2'b01,      // Between s[2] and s[1]
        BETWEEN_S2_S3 = 2'b10,      // Between s[3] and s[2]
        ABOVE_S3 = 2'b11            // Above s[3]
    } state_t;

    state_t state, next_state;
    state_t last_state;

    // State register
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW_WATER;
            last_state <= LOW_WATER;
        end else begin
            state <= next_state;
            last_state <= state;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            LOW_WATER: begin
                if (s[1])
                    next_state = BETWEEN_S1_S2;
                else
                    next_state = LOW_WATER;
            end
            BETWEEN_S1_S2: begin
                if (s[2])
                    next_state = BETWEEN_S2_S3;
                else if (!s[1])
                    next_state = LOW_WATER;
                else
                    next_state = BETWEEN_S1_S2;
            end
            BETWEEN_S2_S3: begin
                if (s[3])
                    next_state = ABOVE_S3;
                else if (!s[2])
                    next_state = BETWEEN_S1_S2;
                else
                    next_state = BETWEEN_S2_S3;
            end
            ABOVE_S3: begin
                if (!s[3])
                    next_state = BETWEEN_S2_S3;
                else
                    next_state = ABOVE_S3;
            end
            default: next_state = LOW_WATER;
        endcase
    end

    // Output logic based on current state and previous state
    always @(*) begin
        fr1 = 0;
        fr2 = 0;
        fr3 = 0;
        dfr = 0;
        case (state)
            LOW_WATER: begin
                fr1 = 1;
                fr2 = 1;
                fr3 = 1;
                dfr = 1;
            end
            BETWEEN_S1_S2: begin
                fr1 = 1;
                fr2 = 1;
                // More flow needed if rising water level
                if (last_state == LOW_WATER)
                    dfr = 1;
            end
            BETWEEN_S2_S3: begin
                fr1 = 1;
                // More flow needed if rising water level
                if (last_state == BETWEEN_S1_S2)
                    dfr = 1;
            end
            ABOVE_S3: begin
                // All output flow rates zero
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State Encoding
    typedef enum reg [1:0] {
        STATE_BELOW_S1 = 2'b00,
        STATE_BETWEEN_S1_S2 = 2'b01,
        STATE_BETWEEN_S2_S3 = 2'b10,
        STATE_ABOVE_S3 = 2'b11
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            // Reset to a state equivalent to if the water level had been low for a long time
            current_state <= STATE_BELOW_S1;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        // Default values
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;
        next_state = current_state;

        case (current_state)
            STATE_BELOW_S1: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1;
                if (s[1]) begin
                    next_state = STATE_BETWEEN_S1_S2;
                end
            end

            STATE_BETWEEN_S1_S2: begin
                fr2 = 1;
                fr1 = 1;
                if (!s[1]) begin
                    next_state = STATE_BELOW_S1;
                end else if (s[2]) begin
                    next_state = STATE_BETWEEN_S2_S3;
                end
            end

            STATE_BETWEEN_S2_S3: begin
                fr1 = 1;
                if (!s[2]) begin
                    next_state = STATE_BETWEEN_S1_S2;
                end else if (s[3]) begin
                    next_state = STATE_ABOVE_S3;
                end
            end

            STATE_ABOVE_S3: begin
                // No flow
                if (!s[3]) begin
                    next_state = STATE_BETWEEN_S2_S3;
                    dfr = 1; // Increase flow rate if going from higher to lower
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    typedef enum reg [1:0] {
        STATE_LOW = 2'b00,
        STATE_MID = 2'b01,
        STATE_HIGH = 2'b10,
        STATE_ABOVE = 2'b11
    } state_t;

    reg [1:0] current_state, next_state;
    reg [1:0] previous_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= STATE_LOW;
            previous_state <= STATE_LOW;
        end else begin
            current_state <= next_state;
            if (current_state != next_state)
                previous_state <= current_state;
        end
    end

    always @(*) begin
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;

        case (current_state)
            STATE_LOW: begin
                if (s == 3'b000) begin
                    fr3 = 1;
                    fr2 = 1;
                    fr1 = 1;
                end
                if (s[1])
                    next_state = STATE_MID;
                else
                    next_state = STATE_LOW;
            end

            STATE_MID: begin
                if (s == 3'b010) begin
                    fr2 = 1;
                    fr1 = 1;
                    if (previous_state == STATE_LOW)
                        dfr = 1;
                end
                if (s[2])
                    next_state = STATE_HIGH;
                else if (!s[1])
                    next_state = STATE_LOW;
                else
                    next_state = STATE_MID;
            end

            STATE_HIGH: begin
                if (s == 3'b110) begin
                    fr1 = 1;
                    if (previous_state == STATE_MID)
                        dfr = 1;
                end
                if (s[3])
                    next_state = STATE_ABOVE;
                else if (!s[2])
                    next_state = STATE_MID;
                else
                    next_state = STATE_HIGH;
            end

            STATE_ABOVE: begin
                if (s == 3'b111) begin
                    // No flow rate
                end
                if (!s[3])
                    next_state = STATE_HIGH;
                else
                    next_state = STATE_ABOVE;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_LOW = 2'b00,      // Below s[1]
        STATE_MID1 = 2'b01,     // Between s[2] and s[1]
        STATE_MID2 = 2'b10,     // Between s[3] and s[2]
        STATE_HIGH = 2'b11      // Above s[3]
    } state_type;

    reg [1:0] current_state, next_state;
    reg [1:0] prev_state;

    // Sequential logic for state transitions
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= STATE_LOW;
            prev_state <= STATE_LOW;
        end else begin
            current_state <= next_state;
            prev_state <= current_state;
        end
    end

    // Combinational logic for state transitions
    always @(*) begin
        case (current_state)
            STATE_LOW: begin
                if (s[3])       next_state = STATE_HIGH;
                else if (s[2])  next_state = STATE_MID2;
                else if (s[1])  next_state = STATE_MID1;
                else            next_state = STATE_LOW;
            end
            STATE_MID1: begin
                if (s[3])       next_state = STATE_HIGH;
                else if (s[2])  next_state = STATE_MID2;
                else if (~s[1]) next_state = STATE_LOW;
                else            next_state = STATE_MID1;
            end
            STATE_MID2: begin
                if (s[3])       next_state = STATE_HIGH;
                else if (~s[2]) next_state = STATE_MID1;
                else if (~s[1]) next_state = STATE_LOW;
                else            next_state = STATE_MID2;
            end
            STATE_HIGH: begin
                if (~s[3])      next_state = STATE_MID2;
                else            next_state = STATE_HIGH;
            end
            default: next_state = STATE_LOW;
        endcase
    end

    // Output logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            fr3 <= 1'b1;
            fr2 <= 1'b1;
            fr1 <= 1'b1;
            dfr <= 1'b1;
        end else begin
            case (current_state)
                STATE_LOW: begin
                    fr3 <= 1;
                    fr2 <= 1;
                    fr1 <= 1;
                    dfr <= 1;
                end
                STATE_MID1: begin
                    fr3 <= 0;
                    fr2 <= 1;
                    fr1 <= 1;
                    dfr <= (prev_state == STATE_LOW) ? 1 : 0;
                end
                STATE_MID2: begin
                    fr3 <= 0;
                    fr2 <= 0;
                    fr1 <= 1;
                    dfr <= (prev_state == STATE_MID1 || prev_state == STATE_LOW) ? 1 : 0;
                end
                STATE_HIGH: begin
                    fr3 <= 0;
                    fr2 <= 0;
                    fr1 <= 0;
                    dfr <= 0;
                end
                default: begin
                    fr3 <= 1;
                    fr2 <= 1;
                    fr1 <= 1;
                    dfr <= 1;
                end
            endcase
        end
    end

endmodule


module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State definitions
    typedef enum reg [2:0] {
        IDLE = 3'b000,     // Waiting for start bit
        START = 3'b001,    // Start bit detected
        DATA = 3'b010,     // Receiving data bits
        STOP = 3'b011,     // Expecting stop bit
        DONE = 3'b100,     // Byte successfully received
        ERROR = 3'b101    // Stop bit error
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count; // To count the number of data bits received
    reg done_reg;

    // Sequential Logic: State Transition and Output Logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 0;
            done_reg <= 0;
        end else begin
            state <= next_state;
            done_reg <= (next_state == DONE);
        end
    end

    // Combinational Logic: Next State Logic
    always @(*) begin
        next_state = state;
        case (state)
            IDLE: begin
                if (in == 0) // Detect start bit
                    next_state = START;
            end

            START: begin
                next_state = DATA;
                bit_count = 0;
            end

            DATA: begin
                if (bit_count == 7)
                    next_state = STOP;
                else
                    bit_count = bit_count + 1;
            end

            STOP: begin
                if (in == 1)
                    next_state = DONE;
                else
                    next_state = ERROR;
            end

            DONE: begin
                if (in == 1)
                    next_state = IDLE;
            end

            ERROR: begin
                if (in == 1) // Wait for a stop bit to return to IDLE
                    next_state = IDLE;
            end
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State encoding
    typedef enum logic [2:0] {
        IDLE        = 3'b000,
        START_BIT   = 3'b001,
        DATA_BITS   = 3'b010,
        STOP_BIT    = 3'b011,
        CHECK_STOP  = 3'b100
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_counter;
    reg done_reg;

    // Next state logic
    always_comb begin
        next_state = state; // Default to current state
        done_reg = 1'b0; // Default output
        case (state)
            IDLE: begin
                if (in == 1'b0) // Detecting start bit
                    next_state = START_BIT;
            end
            START_BIT: begin
                next_state = DATA_BITS;
                bit_counter = 3'd0; // Reset bit counter
            end
            DATA_BITS: begin
                if (bit_counter == 3'd7)
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end
            STOP_BIT: begin
                next_state = CHECK_STOP;
            end
            CHECK_STOP: begin
                if (in == 1'b1) begin
                    done_reg = 1'b1; // Byte correctly received
                    next_state = IDLE;
                end else begin
                    next_state = IDLE; // Go back to IDLE and try to find new byte
                end
            end
            default: begin
                next_state = IDLE; // In case of unexpected state
            end
        endcase
    end

    // Sequential logic for state transitions and output
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_counter <= 3'd0;
        end else begin
            state <= next_state;
            if (state == DATA_BITS)
                bit_counter <= bit_counter + 1;
        end
    end

    // Output assignment
    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // State Encoding
    typedef enum logic [2:0] {
        IDLE    = 3'b000,
        START   = 3'b001,
        DATA    = 3'b010,
        STOP    = 3'b011,
        ERROR   = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_counter;
    reg [7:0] data_byte;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_counter <= 3'b000;
            done <= 1'b0;
        end
        else begin
            current_state <= next_state;

            if (current_state == DATA) begin
                data_byte[bit_counter] <= in;
                bit_counter <= bit_counter + 1;
            end else if (current_state == STOP || current_state == ERROR) begin
                bit_counter <= 3'b000;
            end

            if (current_state == STOP && in == 1'b1) begin
                done <= 1'b1;
            end else begin
                done <= 1'b0;
            end
        end
    end

    always @(*) begin
        case (current_state)
            IDLE: begin
                if (in == 1'b0)
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                if (in == 1'b0)
                    next_state = DATA;
                else
                    next_state = IDLE; // Start bit must be 0
            end
            DATA: begin
                if (bit_counter == 3'b111) // 8 bits received
                    next_state = STOP;
                else
                    next_state = DATA;
            end
            STOP: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            ERROR: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    reg [3:0] state, next_state;
    reg [2:0] bit_counter;
    reg done_reg;

    localparam IDLE      = 4'd0,
               START     = 4'd1,
               DATA_BITS = 4'd2,
               STOP      = 4'd3,
               DONE      = 4'd4,
               ERROR     = 4'd5;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_counter <= 3'd0;
            done_reg <= 1'b0;
        end else begin
            state <= next_state;
            if (state == DATA_BITS)
                bit_counter <= bit_counter + 3'd1;
            else
                bit_counter <= 3'd0;

            if (state == DONE)
                done_reg <= 1'b1;
            else
                done_reg <= 1'b0;
        end
    end

    always @(*) begin
        next_state = state; // Default to stay in current state
        case (state)
            IDLE: begin
                if (in == 1'b0) // Start bit detected
                    next_state = START;
            end
            START: begin
                next_state = DATA_BITS;
            end
            DATA_BITS: begin
                if (bit_counter == 3'd7)
                    next_state = STOP;
            end
            STOP: begin
                if (in == 1'b1) // Stop bit detected
                    next_state = DONE;
                else
                    next_state = ERROR;
            end
            DONE: begin
                if (in == 1'b1) // Wait for line to return to idle to restart
                    next_state = IDLE;
            end
            ERROR: begin
                if (in == 1'b1) // Wait for line to return to idle to restart
                    next_state = IDLE;
            end
            default: next_state = IDLE;
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // State encoding
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_count;
    reg [7:0] data_byte;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 3'd0;
            done <= 1'b0;
        end
        else begin
            current_state <= next_state;
        end
    end

    // Next state logic and output logic
    always_comb begin
        next_state = current_state; // Default to remain in the current state
        done = 1'b0;  // Default done output
        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START;
                end
            end
            START: begin
                if (in == 1'b0) begin
                    next_state = DATA;
                    bit_count = 3'd0;
                end
                else begin
                    next_state = IDLE;  // False start, back to IDLE
                end
            end
            DATA: begin
                data_byte[bit_count] = in;
                if (bit_count == 3'd7) begin
                    next_state = STOP;
                end
                bit_count = bit_count + 3'd1;
            end
            STOP: begin
                if (in == 1'b1) begin
                    done = 1'b1;  // Byte received successfully
                    next_state = IDLE;
                end
                else begin
                    next_state = ERROR;  // Stop bit not correct
                end
            end
            ERROR: begin
                if (in == 1'b1) begin
                    next_state = IDLE; // Wait for line to go idle
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START_BIT = 3'b001,
        DATA_BITS = 3'b010,
        STOP_BIT = 3'b011,
        DONE = 3'b100
    } state_t;

    reg [2:0] state, next_state;
    reg [2:0] bit_count;
    reg [7:0] data_byte;
    reg done_reg;

    assign done = done_reg;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 3'b000;
            data_byte <= 8'b00000000;
            done_reg <= 1'b0;
        end else begin
            state <= next_state;
            if (state == DATA_BITS) begin
                data_byte <= {in, data_byte[7:1]}; // Shift in bits (LSB first)
            end
            if (state == DONE) begin
                done_reg <= 1'b1;
            end else begin
                done_reg <= 1'b0;
            end
        end
    end

    always @(*) begin
        next_state = state; // Default is to remain in the same state
        case (state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START_BIT;
                end
            end
            START_BIT: begin
                next_state = DATA_BITS; // Start bit detected, move to data bits
                bit_count = 3'b000; // Reset bit count for data bits
            end
            DATA_BITS: begin
                if (bit_count == 3'b111) begin
                    next_state = STOP_BIT; // All data bits received, move to stop bit
                end else begin
                    bit_count = bit_count + 3'b001; // Increment bit counter
                end
            end
            STOP_BIT: begin
                if (in == 1) begin
                    next_state = DONE; // Stop bit correct
                end else begin
                    next_state = IDLE; // Wait for a stop bit
                end
            end
            DONE: begin
                next_state = IDLE; // Return to idle after a successful byte capture
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State encoding
    typedef enum reg [2:0] {
        IDLE     = 3'b000,
        START    = 3'b001,
        DATA     = 3'b010,
        STOP     = 3'b011,
        ERROR    = 3'b100
    } state_t;

    reg [2:0] state, next_state;
    reg [3:0] bit_count; // 4 bits to count up to 8 data bits
    reg done_reg;

    assign done = done_reg;

    // State transition logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 4'd0;
            done_reg <= 1'b0;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        next_state = state;
        done_reg = 1'b0; // Default done signal to 0

        case (state)
            IDLE: begin
                if (in == 1'b0) begin // Look for start bit (0)
                    next_state = START;
                end
            end
            START: begin
                next_state = DATA; // Move to DATA state
                bit_count = 4'd0;  // Reset bit counter
            end
            DATA: begin
                if (bit_count == 4'd8) begin
                    next_state = (in == 1'b1) ? STOP : ERROR; // Expect stop bit (1)
                end else begin
                    bit_count = bit_count + 1;
                end
            end
            STOP: begin
                done_reg = 1'b1;   // Byte received successfully
                next_state = IDLE; // Return to IDLE state
            end
            ERROR: begin
                if (in == 1'b1) begin // Wait for the stop bit (1) to complete
                    next_state = IDLE;
                end
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum logic [1:0] {
        IDLE,    // Waiting for start bit
        START,   // Start bit detected, wait for data bits
        DATA,    // Receiving data bits
        STOP     // Data bits received, checking stop bit
    } state_t;

    state_t current_state, next_state;
    logic [2:0] bit_counter;  // Counter for data bits
    logic done_reg;

    // State transition
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_counter <= 3'b000;
            done_reg <= 1'b0;
        end else begin
            current_state <= next_state;
            if (next_state == DATA) begin
                bit_counter <= bit_counter + 1;
            end else if (next_state == STOP || next_state == IDLE) begin
                bit_counter <= 3'b000;
            end
            done_reg <= (current_state == STOP) && (in == 1'b1);
        end
    end

    // Next state logic
    always_comb begin
        next_state = current_state;  // Default to stay in the same state
        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START;
                end
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_counter == 3'b111) begin // 8th data bit
                    next_state = STOP;
                end
            end
            STOP: begin
                if (in == 1'b1) begin
                    next_state = IDLE;
                end else begin
                    next_state = STOP;  // Wait here until stop bit is found
                end
            end
        endcase
    end

    // Output logic
    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State encoding
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count;
    reg done_reg;

    // Output logic
    assign done = done_reg;

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
            done_reg <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == DATA) bit_count <= bit_count + 1;
            else bit_count <= 0;
            done_reg <= (next_state == STOP);
        end
    end

    // Next state logic
    always @* begin
        next_state = current_state; // Default: stay in the same state
        case (current_state)
            IDLE:
                if (!in) next_state = START; // Detect start bit
            START:
                next_state = DATA; // Move to DATA state
            DATA:
                if (bit_count == 8)
                    next_state = (in) ? STOP : ERROR; // Check stop bit after 8 data bits
            STOP:
                if (!in) next_state = START; // Prepare for a new byte
                else next_state = IDLE; // Stay idle while the line is high
            ERROR:
                if (in) next_state = IDLE; // Wait to return to idle
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State encoding
    typedef enum logic [2:0] {
        IDLE        = 3'b000,
        START_BIT   = 3'b001,
        DATA_BITS   = 3'b010,
        STOP_BIT    = 3'b011,
        ERROR       = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_count; // To count 8 data bits
    reg done_reg;

    // State transition logic
    always @(posedge clk) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: begin
                if (in == 1'b0)
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end

            START_BIT: begin
                next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_count == 3'd7)
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end

            STOP_BIT: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            ERROR: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            default: next_state = IDLE;
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset) begin
            bit_count <= 3'b0;
            done_reg <= 1'b0;
        end else begin
            done_reg <= 1'b0;
            case (current_state)
                DATA_BITS: begin
                    bit_count <= bit_count + 1'b1;
                end
                STOP_BIT: begin
                    if (in == 1'b1)
                        done_reg <= 1'b1;
                    bit_count <= 3'b0;
                end
                default: begin
                    bit_count <= 3'b0;
                end
            endcase
        end
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // State encoding
    typedef enum logic[2:0] {
        IDLE      = 3'b000,
        START_BIT = 3'b001,
        DATA_BITS = 3'b010,
        STOP_BIT  = 3'b011,
        ERROR     = 3'b100
    } state_t;

    state_t state, next_state;

    // Count for data bits
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state     <= IDLE;
            bit_count <= 3'd0;
            done      <= 1'b0;
        end else begin
            state <= next_state;

            if (state == DATA_BITS) begin
                bit_count <= bit_count + 3'd1;
            end else begin
                bit_count <= 3'd0;
            end

            if (state == STOP_BIT && in == 1'b1) begin
                done <= 1'b1;
            end else begin
                done <= 1'b0;
            end
        end
    end

    always @(*) begin
        case (state)
            IDLE: begin
                if (in == 1'b0)  // Detect start bit (0)
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end

            START_BIT: begin
                next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_count == 3'd7)
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end

            STOP_BIT: begin
                if (in == 1'b1)  // Check for stop bit (1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            ERROR: begin
                if (in == 1'b1)  // Wait for idle state (stop bit)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    reg [3:0] state, next_state;
    reg [7:0] data_bits;
    reg done_reg;

    // State encoding
    localparam IDLE     = 4'd0,
               START    = 4'd1,
               DATA_0   = 4'd2,
               DATA_1   = 4'd3,
               DATA_2   = 4'd4,
               DATA_3   = 4'd5,
               DATA_4   = 4'd6,
               DATA_5   = 4'd7,
               DATA_6   = 4'd8,
               DATA_7   = 4'd9,
               STOP     = 4'd10,
               ERROR    = 4'd11;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            done_reg <= 1'b0;
        end
        else begin
            state <= next_state;
            if (state == STOP && in == 1'b1)
                done_reg <= 1'b1;
            else
                done_reg <= 1'b0;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (in == 1'b0)
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                next_state = DATA_0;
            end
            DATA_0: begin
                next_state = DATA_1;
            end
            DATA_1: begin
                next_state = DATA_2;
            end
            DATA_2: begin
                next_state = DATA_3;
            end
            DATA_3: begin
                next_state = DATA_4;
            end
            DATA_4: begin
                next_state = DATA_5;
            end
            DATA_5: begin
                next_state = DATA_6;
            end
            DATA_6: begin
                next_state = DATA_7;
            end
            DATA_7: begin
                next_state = STOP;
            end
            STOP: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            ERROR: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            default: next_state = IDLE;
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE,       // Waiting for start bit
        START,      // Checking start bit
        DATA,       // Receiving data bits
        STOP,       // Checking stop bit
        WAITSTOP    // Wait for a valid stop bit
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 3'd0;
            done <= 1'b0;
        end
        else begin
            state <= next_state;
            if (state == DATA)
                bit_count <= bit_count + 1;
            else
                bit_count <= 3'd0;
        end
    end

    always @(*) begin
        next_state = state;
        done = 1'b0;
        case (state)
            IDLE: begin
                if (in == 1'b0)  // Start bit detected
                    next_state = START;
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_count == 3'd7)
                    if (in == 1'b1)
                        next_state = STOP;
                    else
                        next_state = WAITSTOP;
            end
            STOP: begin
                done = 1'b1;
                if (in == 1'b0)
                    next_state = START;
                else
                    next_state = IDLE;
            end
            WAITSTOP: begin
                if (in == 1'b1)
                    next_state = IDLE;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    // State definitions
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_count;
    reg done_reg;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 3'd0;
            done_reg <= 1'b0;
        end else begin
            current_state <= next_state;
            done_reg <= (current_state == STOP);
            if (current_state == DATA)
                bit_count <= bit_count + 3'd1;
            else
                bit_count <= 3'd0;
        end
    end

    always @* begin
        case (current_state)
            IDLE: begin
                if (in == 1'b0) // Start bit detected
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_count == 3'd7)
                    next_state = STOP;
                else
                    next_state = DATA;
            end
            STOP: begin
                if (in == 1'b1) // Correct stop bit
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            ERROR: begin
                if (in == 1'b1) // Wait for idle to find stop bit
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            default: next_state = IDLE;
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // State encoding
    typedef enum logic [3:0] {
        IDLE       = 4'b0000,
        START      = 4'b0001,
        DATA_0     = 4'b0010,
        DATA_1     = 4'b0011,
        DATA_2     = 4'b0100,
        DATA_3     = 4'b0101,
        DATA_4     = 4'b0110,
        DATA_5     = 4'b0111,
        DATA_6     = 4'b1000,
        DATA_7     = 4'b1001,
        STOP       = 4'b1010,
        ERROR      = 4'b1011
    } state_t;

    state_t state, next_state;
    reg [7:0] data_byte; // Storage for received data bits
    integer bit_count;

    // Synchronous state transition logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic and output
    always @(*) begin
        next_state = state; // Default stay in the same state
        done = 1'b0;        // Default done output is 0

        case (state)
            IDLE: begin
                if (in == 1'b0) begin // Detect start bit
                    next_state = START;
                end
            end

            START: begin
                if (in == 1'b0) begin
                    next_state = DATA_0;
                    bit_count = 0;
                end else begin
                    next_state = ERROR; // If start bit was not '0', go to error
                end
            end

            DATA_0, DATA_1, DATA_2, DATA_3, DATA_4, DATA_5, DATA_6, DATA_7: begin
                data_byte[bit_count] = in; // Capture the incoming data bit
                next_state = state + 1;    // Move to the next data state
                bit_count = bit_count + 1;
            end

            STOP: begin
                if (in == 1'b1) begin // Check for valid stop bit
                    done = 1'b1;
                    next_state = IDLE;
                end else begin
                    next_state = ERROR; // If stop bit was not '1', go to error
                end
            end

            ERROR: begin
                if (in == 1'b1) begin // Wait for a line idle (logic 1) to resync
                    next_state = IDLE;
                end
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg done
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_counter;
    reg [7:0] data_byte;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_counter <= 0;
            done <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == DATA) begin
                data_byte[bit_counter] <= in;
                bit_counter <= bit_counter + 1;
            end
        end
    end

    always @(*) begin
        done = 0;
        case (current_state)
            IDLE: begin
                if (in == 0)
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                if (in == 0)
                    next_state = DATA;
                else
                    next_state = IDLE;
            end
            DATA: begin
                if (bit_counter == 7)
                    next_state = STOP;
                else
                    next_state = DATA;
            end
            STOP: begin
                if (in == 1) begin
                    next_state = IDLE;
                    done = 1;
                end else
                    next_state = ERROR;
            end
            ERROR: begin
                if (in == 1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // State encoding
    typedef enum logic [2:0] {
        IDLE      = 3'd0,
        START_BIT = 3'd1,
        DATA_BITS = 3'd2,
        STOP_BIT  = 3'd3,
        DONE      = 3'd4
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 3'd0;
            done <= 1'b0;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        next_state = state; // Default to hold state
        done = 1'b0;        // Default done signal

        case (state)
            IDLE: begin
                if (~in) // Detect start bit (0)
                    next_state = START_BIT;
            end

            START_BIT: begin
                next_state = DATA_BITS;
                bit_count = 3'd0;
            end

            DATA_BITS: begin
                if (bit_count == 3'd7)
                    next_state = STOP_BIT;
                else
                    bit_count = bit_count + 1;
            end

            STOP_BIT: begin
                if (in) // Detect stop bit (1)
                    next_state = DONE;
                else
                    next_state = IDLE; // Go back to IDLE if stop bit not detected
            end

            DONE: begin
                done = 1'b1; // Signal the reception is done
                if (~in) // Look for the next start bit
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end

            default: begin
                next_state = IDLE; // Default state
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START_BIT = 3'b001,
        DATA_BITS = 3'b010,
        STOP_BIT = 3'b011,
        WAIT_STOP = 3'b100
    } state_t;

    state_t state, next_state;
    reg [3:0] bit_counter;  // To count the 8 data bits.

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_counter <= 4'b0;
            done <= 1'b0;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        next_state = state;
        done = 1'b0;

        case (state)
            IDLE: begin
                if (in == 1'b0)  // Detected start bit
                    next_state = START_BIT;
            end

            START_BIT: begin
                next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_counter < 8) begin
                    next_state = DATA_BITS;
                end else begin
                    next_state = STOP_BIT;
                end
            end

            STOP_BIT: begin
                if (in == 1'b1) begin  // Correct stop bit
                    done = 1'b1;       // Byte received correctly
                    next_state = IDLE;
                end else begin
                    next_state = WAIT_STOP;
                end
            end

            WAIT_STOP: begin
                if (in == 1'b1) begin  // Waiting for idle
                    next_state = IDLE;
                end
            end

            default: begin
                next_state = IDLE;
            end
        endcase
    end

    always_ff @(posedge clk) begin
        if (state == DATA_BITS) begin
            bit_counter <= bit_counter + 1;
        end else if (state != DATA_BITS) begin
            bit_counter <= 4'b0;
        end
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    reg [2:0] state, next_state;
    reg [3:0] bit_count;  // 4 bits to count from 0 to 8
    reg [7:0] data_reg;   // To hold received byte
    reg done_reg;

    // Output logic
    assign done = done_reg;

    // State transition logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 4'd0;
            data_reg <= 8'd0;
            done_reg <= 1'b0;
        end else begin
            state <= next_state;
            if (state == DATA) begin
                data_reg <= {in, data_reg[7:1]};
                bit_count <= bit_count + 1;
            end else if (state != DATA) begin
                bit_count <= 4'd0;
            end

            if (state == STOP && in == 1'b1) begin
                done_reg <= 1'b1;
            end else begin
                done_reg <= 1'b0;
            end
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (in == 1'b0)
                    next_state = START;
                else
                    next_state = IDLE;
            end

            START: begin
                next_state = DATA;
            end

            DATA: begin
                if (bit_count == 4'd8)
                    next_state = STOP;
                else
                    next_state = DATA;
            end

            STOP: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            ERROR: begin
                if (in == 1'b1)
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    // Define the states
    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011,
        ERROR = 3'b100
    } state_t;

    // State registers
    state_t current_state, next_state;

    // Bit counter for data bits
    reg [2:0] bit_counter;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_counter <= 3'b000;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        // Default state
        next_state = current_state;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin // Start bit detected
                    next_state = START;
                end
            end
            START: begin
                next_state = DATA;
                bit_counter = 3'b000;
            end
            DATA: begin
                if (bit_counter == 3'b111) begin
                    next_state = STOP;
                end else begin
                    next_state = DATA;
                end
                bit_counter = bit_counter + 1;
            end
            STOP: begin
                if (in == 1'b1) begin // Correct stop bit
                    done = 1'b1;
                    next_state = IDLE;
                end else begin
                    next_state = ERROR;
                end
            end
            ERROR: begin
                if (in == 1'b1) begin // Wait for line to be idle
                    next_state = IDLE;
                end else begin
                    next_state = ERROR;
                end
            end
            default: begin
                next_state = IDLE;
            end
        endcase
    end

endmodule