module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 3'd4;
        else
            q <= (q + 3'd1) % 3'd7;
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);
    always @(posedge clk) begin
        if (a)
            q <= 3'd4;
        else
            q <= q + 1;
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            q <= 4;
        end else begin
            q <= q + 1;
        end
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 3'b100;
        else
            q <= q + 3'b001;
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 4;
        else
            q <= q + 1;
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            q <= 4;
        end else begin
            if (q == 6) begin
                q <= 0;
            end else begin
                q <= q + 1;
            end
        end
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 3'd4;
        else if (q == 3'd6)
            q <= 3'd0;
        else
            q <= q + 3'd1;
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            q <= 3'd4;
        end else begin
            q <= (q == 3'd6) ? 3'd0 : (q + 1);
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 3'd4;
        else
            q <= (q == 3'd6) ? 3'd0 : q + 1;
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 4;
        else if (q == 4)
            q <= 5;
        else if (q == 5)
            q <= 6;
        else if (q == 6)
            q <= 0;
        else
            q <= q + 1;
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b0) begin
                q <= 3'b100;
            end else begin
                q <= q;
            end
        end else begin
            q <= q + 1;
            if (q == 3'b110) begin
                q <= 3'b000;
            end
        end
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            q <= 3'b100;
        end else begin
            if (q == 3'b110) begin
                q <= 3'b000;
            end else begin
                q <= q + 1;
            end
        end
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

always @(posedge clk) begin
    if (a)
        q <= 4;
    else if (q == 6)
        q <= 0;
    else
        q <= q + 1;
end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            q <= 3'd4;
        end else begin
            if (q == 3'd6) begin
                q <= 3'd0;
            end
            else begin
                q <= q + 3'd1;
            end
        end
    end
endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

    always @(posedge clk) begin
        if (a)
            q <= 3'b100;
        else if (q == 3'b110)
            q <= 3'b000;
        else
            q <= q + 1;
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

    always @(posedge clk) begin
        if (a == 1) begin
            q <= 3'b100; // binary for 4
        end else begin
            if (q == 3'b110)
                q <= 3'b000; // reset q to 0 when it reaches 6
            else
                q <= q + 1;
        end
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            q <= 3'b100;
        end else begin
            if (q == 3'b110)
                q <= 3'b000;
            else
                q <= q + 1;
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a)
            q <= 3'b100;
        else
            q <= q + 1;
    end
endmodule


module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Reset state
        end else begin
            q <= {q[3:0], q[4] ^ q[2]}; // Shift and feedback using taps at positions 5 and 3
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Active-high synchronous reset to 1
        end else begin
            q <= {q[3:0], q[4] ^ q[2]}; // Shift and feedback taps at bit positions 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001;
        end else begin
            q <= {q[3:0], q[4] ^ q[2]};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001;
        end else begin
            q <= {q[3:0], q[4] ^ q[2]};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 5'b00001;
        else begin
            q[0] <= q[4];
            q[1] <= q[0];
            q[2] <= q[1];
            q[3] <= q[2] ^ q[4];
            q[4] <= q[3];
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

always @(posedge clk) begin
    if (reset) begin
        q <= 5'b00001;
    end else begin
        q[4] <= q[0]; // Since tap is at position 5 (LSB = position 1)
        q[3] <= q[4];
        q[2] <= q[3];
        q[1] <= q[2];
        q[0] <= q[1] ^ q[0]; // XOR the output and tap position 3
    end
end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Active-high reset to initial value 1
        end else begin
            q[0] <= q[1];
            q[1] <= q[2];
            q[2] <= q[3];
            q[3] <= q[4];
            q[4] <= q[0] ^ q[2]; // XOR taps at positions 5 and 3
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Synchronous reset to state 1
        end else begin
            q <= {q[3:0], q[4] ^ q[2]}; // Shift, XOR taps at bit positions 5 and 3 (4 and 2 in array)
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Initialize to 1 on reset
        end else begin
            // Implementing Galois LFSR with taps at bit positions 5 and 3
            q <= {q[3:0], q[4] ^ q[2]};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 5'b00001; // Reset to 1
        else begin
            q[0] <= q[4];             // Shift the most significant bit to the least significant bit
            q[1] <= q[0];             // Shift each bit
            q[2] <= q[1];             // Shift each bit
            q[3] <= q[2];             // Shift each bit
            q[4] <= q[3] ^ q[4];      // XOR the tap position bit 3 with bit 5 (MSB)
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

always @(posedge clk) begin
    if (reset) begin
        q <= 5'b00001; // Reset to 1
    end else begin
        q <= {q[3:0], q[4] ^ q[2]}; // Shift and feedback with taps at bit positions 5 and 3
    end
end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001; // Active-high synchronous reset to 1
        end else begin
            q[4] <= q[0]; // Feedback from q[0] to q[4]
            q[3] <= q[4] ^ q[0]; // XOR tap positions 5 and 3
            q[2] <= q[3];
            q[1] <= q[2];
            q[0] <= q[1];
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 5'b00001;
        end else begin
            q[0] <= q[4];
            q[1] <= q[0];
            q[2] <= q[1];
            q[3] <= q[2];
            q[4] <= q[3] ^ q[4];
        end
    end

endmodule


module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
          0: out = a + b;
          1: out = a - b;
        endcase

        // Check if out is zero
        result_is_zero = (out == 8'b0) ? 1'b1 : 1'b0;
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        result_is_zero = (out == 8'h00);
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        result_is_zero = (out == 8'b0); // Correctly check if output is zero
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
          0: out = a + b;
          1: out = a - b;
        endcase

        if (out == 0)
            result_is_zero = 1;
        else
            result_is_zero = 0;
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        result_is_zero = (out == 8'b0);
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        result_is_zero = (out == 8'b00000000);
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        result_is_zero = (out == 8'b0) ? 1 : 0;
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
            default: out = 8'd0;
        endcase

        result_is_zero = (out == 8'd0);
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		case (do_sub)
			0: out = a + b;
			1: out = a - b;
		endcase

		if (out == 8'b00000000)
			result_is_zero = 1;
		else
			result_is_zero = 0;
	end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
            0: out = a + b;
            1: out = a - b;
        endcase

        if (out == 8'b0)
            result_is_zero = 1;
        else
            result_is_zero = 0;
    end

endmodule


module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
    case (code)
        8'h45: begin
            out = 4'd0;
            valid = 1'b1;
        end
        8'h16: begin
            out = 4'd1;
            valid = 1'b1;
        end
        8'h1e: begin
            out = 4'd2;
            valid = 1'b1;
        end
        8'h26: begin
            out = 4'd3;
            valid = 1'b1;
        end
        8'h25: begin
            out = 4'd4;
            valid = 1'b1;
        end
        8'h2e: begin
            out = 4'd5;
            valid = 1'b1;
        end
        8'h36: begin
            out = 4'd6;
            valid = 1'b1;
        end
        8'h3d: begin
            out = 4'd7;
            valid = 1'b1;
        end
        8'h3e: begin
            out = 4'd8;
            valid = 1'b1;
        end
        8'h46: begin
            out = 4'd9;
            valid = 1'b1;
        end
        default: begin
            out = 4'd0;
            valid = 1'b0;
        end
    endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

    always @(*) begin
        valid = 1'b0;
        out = 4'b0000;
        case (code)
            8'h45: begin out = 4'b0000; valid = 1'b1; end // key 0
            8'h16: begin out = 4'b0001; valid = 1'b1; end // key 1
            8'h1e: begin out = 4'b0010; valid = 1'b1; end // key 2
            8'h26: begin out = 4'b0011; valid = 1'b1; end // key 3
            8'h25: begin out = 4'b0100; valid = 1'b1; end // key 4
            8'h2e: begin out = 4'b0101; valid = 1'b1; end // key 5
            8'h36: begin out = 4'b0110; valid = 1'b1; end // key 6
            8'h3d: begin out = 4'b0111; valid = 1'b1; end // key 7
            8'h3e: begin out = 4'b1000; valid = 1'b1; end // key 8
            8'h46: begin out = 4'b1001; valid = 1'b1; end // key 9
            default: begin out = 4'b0000; valid = 1'b0; end
        endcase
    end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

    always @* begin
        case (code)
            8'h45: begin out = 4'd0; valid = 1'b1; end
            8'h16: begin out = 4'd1; valid = 1'b1; end
            8'h1e: begin out = 4'd2; valid = 1'b1; end
            8'h26: begin out = 4'd3; valid = 1'b1; end
            8'h25: begin out = 4'd4; valid = 1'b1; end
            8'h2e: begin out = 4'd5; valid = 1'b1; end
            8'h36: begin out = 4'd6; valid = 1'b1; end
            8'h3d: begin out = 4'd7; valid = 1'b1; end
            8'h3e: begin out = 4'd8; valid = 1'b1; end
            8'h46: begin out = 4'd9; valid = 1'b1; end
            default: begin out = 4'd0; valid = 1'b0; end
        endcase
    end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
    case (code)
        8'h45: begin out = 4'd0; valid = 1; end
        8'h16: begin out = 4'd1; valid = 1; end
        8'h1e: begin out = 4'd2; valid = 1; end
        8'h26: begin out = 4'd3; valid = 1; end
        8'h25: begin out = 4'd4; valid = 1; end
        8'h2e: begin out = 4'd5; valid = 1; end
        8'h36: begin out = 4'd6; valid = 1; end
        8'h3d: begin out = 4'd7; valid = 1; end
        8'h3e: begin out = 4'd8; valid = 1; end
        8'h46: begin out = 4'd9; valid = 1; end
        default: begin out = 4'd0; valid = 0; end
    endcase
end

endmodule


module top_module (
    input [7:0] in,
    output [7:0] out
);
    assign out[7] = in[0];
    assign out[6] = in[1];
    assign out[5] = in[2];
    assign out[4] = in[3];
    assign out[3] = in[4];
    assign out[2] = in[5];
    assign out[1] = in[6];
    assign out[0] = in[7];
endmodule

module top_module (
    input [7:0] in,
    output [7:0] out
);
    assign out[0] = in[7];
    assign out[1] = in[6];
    assign out[2] = in[5];
    assign out[3] = in[4];
    assign out[4] = in[3];
    assign out[5] = in[2];
    assign out[6] = in[1];
    assign out[7] = in[0];
endmodule

module top_module (
	input [7:0] in,
	output [7:0] out
);
    assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule


module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0010: out = 0;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b0101: out = 0;
            4'b1001: out = 1;
            4'b1010: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 0;
            4'b1101: out = 1;
            4'b1110: out = 1;
            4'b1111: out = 1;
            default: out = 1; // Choosing to output 1 for don't-care conditions
        endcase
    end

endmodule

module top_module (
	input a,
	input b,
	input c,
	input d,
	output reg out
);

	always @(*) begin
		case ({c, d, a, b})
			4'b0001, 4'b0010, 4'b0011,
			4'b1110, 4'b1111, 4'b1101, 4'b1100,
			4'b1010, 4'b1011, 4'b1001: out = 1'b1;
			default: out = 1'b0;
		endcase
	end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0001: out = 0;
            4'b0010: out = 1;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b0101: out = 0;
            4'b1001: out = 1;
            4'b1010: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 0;
            4'b1101: out = 1;
            4'b1110: out = 1;
            4'b1111: out = 1;
            default: out = 1'bx; // For don't-cares, assign out to 'x' or any preferred value
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0010: out = 1'b0;
            4'b0110: out = 1'b0;
            4'b1110: out = 1'b0;
            4'b1010: out = 1'b0;
            4'b0001: out = 1'b0;
            4'b0000: out = 1'b0;
            4'b1111: out = 1'b1;
            4'b1110: out = 1'b1;
            4'b1011: out = 1'b1;
            4'b1010: out = 1'b1;
            4'b1001: out = 1'b1;
            4'b1000: out = 1'b1;
            4'b1101: out = 1'b1;
            4'b1100: out = 1'b1;
            default: out = 1'bx; // Handle don't cares by assigning don't-care values
        endcase
    end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0001: out = 0;
            4'b0010: out = 1;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b0101: out = 0;
            4'b1100: out = 0;
            4'b1101: out = 1;
            4'b1110: out = 1;
            4'b1111: out = 1;
            4'b1000: out = 0;
            4'b1001: out = 1;
            4'b1010: out = 1;
            4'b1011: out = 1;
            default: out = 0; // Assign a default value for unused don't-care cases
        endcase
    end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0010: out = 0;
            4'b0001: out = 1;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b1101: out = 1;
            4'b0101: out = 0;
            4'b0110: out = 1;
            4'b0111: out = 1;
            4'b1000: out = 0;
            4'b1010: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 0;
            default: out = 1;  // Choose '1' for don't-cares for convenience
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0001: out = 1'b0;
            4'b0010: out = 1'b1;
            4'b0011: out = 1'b1;
            4'b0100: out = 1'b0;
            4'b0101: out = 1'b0;
            4'b1100: out = 1'b0;
            4'b1101: out = 1'b1;
            4'b1110: out = 1'b1;
            4'b1111: out = 1'b1;
            4'b1000: out = 1'b0;
            4'b1001: out = 1'b1;
            4'b1010: out = 1'b1;
            4'b1011: out = 1'b1;
            default: out = 1'b0; // Handles don't-care conditions
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0010, 4'b0011, 4'b0111, 4'b1010, 4'b1011, 4'b1110, 4'b1111: out = 1;
            default: out = 0;
        endcase
    end

endmodule

module top_module (
	input a,
	input b,
	input c,
	input d,
	output reg out
);

	always @(*) begin
		case ({c, d, a, b})
			4'b0010: out = 0;
			4'b0100: out = 0;
			4'b0110: out = 0;
			4'b0111: out = 1;
			4'b1110: out = 0;
			4'b1100: out = 1;
			4'b1101: out = 1;
			4'b1111: out = 1;
			4'b1010: out = 1;
			4'b1001: out = 1;
			4'b1000: out = 1;
			4'b1011: out = 1;
			default: out = 1; // Covering the don't care conditions
		endcase
	end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

always @(*) begin
    case ({c, d, a, b})
        4'b0010, 4'b0011, 4'b1101, 4'b1110, 4'b1111, 4'b1010, 4'b1011: out = 1;
        default: out = 0;
    endcase
end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0001: out = 1'b0;
            4'b0010: out = 1'b1;
            4'b0011: out = 1'b1;
            4'b0100: out = 1'b0;
            4'b0101: out = 1'b0;
            4'b1100: out = 1'b0;
            4'b1101: out = 1'b1;
            4'b1110: out = 1'b1;
            4'b1111: out = 1'b1;
            4'b1000: out = 1'b0;
            4'b1001: out = 1'b1;
            4'b1010: out = 1'b1;
            4'b1011: out = 1'b1;
            default: out = 1'b0; // Handling don't-care conditions
        endcase
    end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0001: out = 0;
            4'b0010: out = 1;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b0101: out = 0;
            4'b1010: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 0;
            4'b1101: out = 1;
            4'b1110: out = 1;
            4'b1111: out = 1;
            default: out = 0; // Using 0 for don't cares
        endcase
    end

endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0010: out = 0;
            4'b0001: out = 0;
            4'b0100: out = 0;
            4'b1100: out = 0;
            4'b0011: out = 1;
            4'b1010: out = 1;
            4'b1110: out = 1;
            4'b1011: out = 1;
            4'b1101: out = 1;
            4'b1111: out = 1;
            default: out = 1; // Assign 1 for don't-care conditions
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0010: out = 0;
            4'b0001: out = 0;
            4'b0110: out = 0;
            4'b1110: out = 0;
            4'b1010: out = 0;
            4'b0000: out = 0;
            4'b0100: out = 1;
            4'b0111: out = 1;
            4'b1111: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 1;
            4'b1001: out = 1;
            4'b1101: out = 1;
            4'b1000: out = 1;
            default: out = 1; // Handling don't care cases and unmapped values
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c, d, a, b})
            4'b0001, 4'b0010, 4'b0011,
            4'b0110, 4'b0111,
            4'b1010, 4'b1011,
            4'b1110, 4'b1111: out = 1;
            default: out = 0;
        endcase
    end
endmodule

module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);
    always @(*) begin
        case ({c,d,a,b})
            4'b0000: out = 1'b0; // don't-care, choosing 0
            4'b0001: out = 1'b0;
            4'b0010: out = 1'b1;
            4'b0011: out = 1'b1;
            4'b0100: out = 1'b0;
            4'b0101: out = 1'b0;
            4'b0110: out = 1'b0; // don't-care, choosing 0
            4'b0111: out = 1'b0; // don't-care, choosing 0
            4'b1000: out = 1'b0;
            4'b1001: out = 1'b1;
            4'b1010: out = 1'b1;
            4'b1011: out = 1'b1;
            4'b1100: out = 1'b0;
            4'b1101: out = 1'b1;
            4'b1110: out = 1'b1;
            4'b1111: out = 1'b1;
            default: out = 1'b0; // default case to handle all other cases
        endcase
    end
endmodule

module top_module (
	input a,
	input b,
	input c,
	input d,
	output reg out
);

    always @(*) begin
        case ({c, d, a, b})
            4'b0000: out = 0;
            4'b0001: out = 1;
            4'b0010: out = 1;
            4'b0011: out = 1;
            4'b0100: out = 0;
            4'b0101: out = 0;
            4'b0110: out = 1; // Don't-care case, choosing 1 for convenience
            4'b0111: out = 1; // Don't-care case, choosing 1 for convenience
            4'b1000: out = 0;
            4'b1001: out = 1;
            4'b1010: out = 1;
            4'b1011: out = 1;
            4'b1100: out = 0;
            4'b1101: out = 1;
            4'b1110: out = 1;
            4'b1111: out = 1;
            default: out = 0; // This default case is added for safety.
        endcase
    end

endmodule


module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			q <= q + 1'b1;
		end
	end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			q <= q + 1;
		end
	end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset)
			q <= 4'b0000;
		else
			q <= q + 1;
	end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'b0000;
        else
            q <= q + 4'b0001;
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

always @(posedge clk) begin
    if (reset) begin
        q <= 4'd0;
    end else begin
        q <= q + 1;
    end
end

endmodule


module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

    // Using assign statement
    assign out_assign = (sel_b1 & sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 & sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

    // Implementing 2-to-1 mux using an assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Implementing 2-to-1 mux using a procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);
    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);
    // Using assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if(sel_b1 && sel_b2) begin
            out_always = b;
        end else begin
            out_always = a;
        end
    end

endmodule

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

    // Using assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2) begin
            out_always = b;
        end else begin
            out_always = a;
        end
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);
    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using a procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end
endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Implementation using assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Implementation using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 & sel_b2) ? b : a;

    // Using a procedural if statement
    always @(*) begin
        if (sel_b1 & sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using always block with procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule


module top_module(
    input a,
    input b,
    input c,
    output out
);

    assign out = (~b & ~c & a) | (~b & c) | (b & ~c) | (b & c);

endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & c) | (~a & b & ~c) | (~a & ~b & ~c);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & ~c & a) | (~b & c) | (b & a);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (~c) | a;
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & ~c) | a;
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b &  a) | ( b & ~a) | c;
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & ~c) | (~a & b) | (a & b);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & ~c) | (b & c);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);

    assign out = (~b & c) | (b & c) | (~c & (b | a));

endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & c) | (~b & ~c & a);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = b | c;
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & c) | (~c);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & c) | (b & c) | (b & ~c) | (~a & b);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (~b & ~c & a) | (~b & c) | (b & c);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & ~c) | a;
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & c) | (~b & c) | (b & ~c & a);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
    assign out = (~b & c) | (b & c) | (~a & b) | (a & b);
endmodule


module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum logic [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // State table
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (~r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        case (current_state)
            STATE_A: g = 3'b000;
            STATE_B: g = 3'b100; // g1 = 1
            STATE_C: g = 3'b010; // g2 = 1
            STATE_D: g = 3'b001; // g3 = 1
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'd0,
        STATE_B = 2'd1,
        STATE_C = 2'd2,
        STATE_D = 2'd3
    } state_t;

    // State variables
    reg [1:0] current_state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // State table
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000;
        case (current_state)
            STATE_B: g[1] = 1; // g1
            STATE_C: g[2] = 1; // g2
            STATE_D: g[3] = 1; // g3
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State transition logic (combinational)
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                // Returns back to state A directly since no further actions defined for D
                next_state = STATE_A;
            end
            default:
                next_state = STATE_A;
        endcase
    end

    // State flip-flops (sequential)
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // Output logic
    always @(*) begin
        g = 3'b000;  // Default all grants to 0
        case (current_state)
            STATE_B: g[1] = 1'b1;  // Grant for device 1
            STATE_C: g[2] = 1'b1;  // Grant for device 2
            STATE_D: g[3] = 1'b1;  // Grant for device 3
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {S_A = 2'd0, S_B = 2'd1, S_C = 2'd2, S_D = 2'd3} state_t;
    state_t state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= S_A;
        else
            state <= next_state;
    end

    // State transition logic
    always @(*) begin
        case (state)
            S_A: begin
                if (r[1])
                    next_state = S_B;
                else if (r[2])
                    next_state = S_C;
                else if (r[3])
                    next_state = S_D;
                else
                    next_state = S_A;
            end
            S_B: begin
                if (r[1])
                    next_state = S_B;
                else
                    next_state = S_A;
            end
            S_C: begin
                if (r[2])
                    next_state = S_C;
                else
                    next_state = S_A;
            end
            S_D: begin
                next_state = S_A;
            end
            default: next_state = S_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default outputs
        case (state)
            S_B: g[1] = 1;
            S_C: g[2] = 1;
            S_D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t state, next_state;

    // Combinational logic for state transition
    always @(*) begin
        case (state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end

            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end

            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end

            STATE_D: begin
                next_state = STATE_A;
            end

            default: next_state = STATE_A;
        endcase
    end

    // Sequential logic for state flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= STATE_A;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default grant values
        case (state)
            STATE_B: g[1] = 1'b1;
            STATE_C: g[2] = 1'b1;
            STATE_D: g[3] = 1'b1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum logic [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= STATE_A;
        else
            state <= next_state;
    end

    // State transition logic
    always @(*) begin
        case (state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000;  // Default all grants to 0
        case (state)
            STATE_B: g[1] = 1;  // Grant g1
            STATE_C: g[2] = 1;  // Grant g2
            STATE_D: g[3] = 1;  // Grant g3
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops (sequential logic)
    always @(posedge clk) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // State table (combinational logic)
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B; // Highest priority
                else if (r[2])
                    next_state = STATE_C; // Second priority
                else if (r[3])
                    next_state = STATE_D; // Lowest priority
                else
                    next_state = STATE_A;
            end

            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end

            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end

            STATE_D: begin
                if (!r[1] && !r[2] && r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end

            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default is no grant
        case (current_state)
            STATE_B: g[1] = 1'b1;
            STATE_C: g[2] = 1'b1;
            STATE_D: g[3] = 1'b1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    // State registers
    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // default
        case (current_state)
            STATE_B: g[1] = 1'b1;
            STATE_C: g[2] = 1'b1;
            STATE_D: g[3] = 1'b1;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State register
    always @(posedge clk) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A; // No request that's why D came, go back to A
            end
            default:
                next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000;
        case (current_state)
            STATE_B: g[1] = 1'b1;
            STATE_C: g[2] = 1'b1;
            STATE_D: g[3] = 1'b1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output reg [3:1] g
);

	// State declarations
	typedef enum reg [1:0] {STATE_A, STATE_B, STATE_C, STATE_D} state_t;
	state_t state, next_state;

	// State Transition
	always @(posedge clk) begin
		if (!resetn)
			state <= STATE_A;
		else
			state <= next_state;
	end

	// Next State Logic
	always @(*) begin
		case (state)
			STATE_A: begin
				if (r[1])
					next_state = STATE_B;
				else if (r[2])
					next_state = STATE_C;
				else if (r[3])
					next_state = STATE_D;
				else
					next_state = STATE_A;
			end

			STATE_B: begin
				if (r[1])
					next_state = STATE_B;
				else
					next_state = STATE_A;
			end

			STATE_C: begin
				if (r[2])
					next_state = STATE_C;
				else
					next_state = STATE_A;
			end

			STATE_D: begin
				next_state = STATE_A;
			end

			default: next_state = STATE_A;
		endcase
	end

	// Output Logic
	always @(*) begin
		g = 3'b000; // Default
		case (state)
			STATE_B: g[1] = 1;
			STATE_C: g[2] = 1;
			STATE_D: g[3] = 1;
		endcase
	end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            default: begin // STATE_D
                next_state = STATE_A; // Return to STATE_A since no requests are handled in STATE_D
            end
        endcase
    end

    // Output logic
    always @(*) begin
        case (current_state)
            STATE_B: begin
                g = 3'b001; // Grant to r[1] - g1
            end
            STATE_C: begin
                g = 3'b010; // Grant to r[2] - g2
            end
            STATE_D: begin
                g = 3'b100; // Grant to r[3] - g3
            end
            default: begin // STATE_A or any unknown state
                g = 3'b000; // No grants
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // State table (next state logic)
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            default: begin // STATE_D
                next_state = STATE_A;
            end
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000;
        case (current_state)
            STATE_B: g[1] = 1;
            STATE_C: g[2] = 1;
            STATE_D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State Encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State Flip-Flops
    always @(posedge clk) begin
        if (!resetn)
            current_state <= A; // Reset to state A
        else
            current_state <= next_state;
    end

    // State Table (Next State Logic)
    always @(*) begin
        case (current_state)
            A: begin
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else if (r[3])
                    next_state = D;
                else
                    next_state = A;
            end
            B: begin
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end
            C: begin
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            D: begin
                next_state = A;
            end
            default: begin
                next_state = A;
            end
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default output
        case (current_state)
            B: g[1] = 1;
            C: g[2] = 1;
            D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output reg [3:1] g
);

	// State encoding
	localparam A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

	reg [1:0] state, next_state;

	// State table (state transition logic)
	always @(*) begin
		case (state)
			A: begin
				if (r[1])
					next_state = B;
				else if (r[2])
					next_state = C;
				else if (r[3])
					next_state = D;
				else
					next_state = A;
			end
			B: begin
				if (r[1])
					next_state = B;
				else
					next_state = A;
			end
			C: begin
				if (r[2])
					next_state = C;
				else
					next_state = A;
			end
			D: begin
				// In state D, there's no transition to another state
				next_state = A;
			end
			default: next_state = A;
		endcase
	end

	// State flip-flops
	always @(posedge clk or negedge resetn) begin
		if (!resetn)
			state <= A;
		else
			state <= next_state;
	end

	// Output logic
	always @(*) begin
		g = 3'b000; // Default all grants to 0
		case (state)
			B: g[1] = 1;
			C: g[2] = 1;
			// Note: Output for state D is 0 for all g as per description
			default: g = 3'b000;
		endcase
	end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State register
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;
        else
            current_state <= next_state;
    end

    // Next state logic (state table)
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        // Default all grants to 0
        g = 3'b000;

        case (current_state)
            STATE_B: g[1] = 1;
            STATE_C: g[2] = 1;
            STATE_D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State declarations
    typedef enum logic [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always_ff @(posedge clk or negedge resetn) begin
        if (!resetn) begin
            current_state <= STATE_A; // Reset state
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always_comb begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // Output logic
    always_comb begin
        g = 3'b000; // Default output

        case (current_state)
            STATE_B: g[1] = 1;
            STATE_C: g[2] = 1;
            STATE_D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State transition logic (next state logic)
    always @(*) begin
        case (current_state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;
            end
            default: next_state = STATE_A;
        endcase
    end

    // State flip-flops (state registers)
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= STATE_A;  // Reset to state A
        else
            current_state <= next_state;
    end

    // Output logic
    always @(*) begin
        g = 3'b000;  // Default no grant
        case (current_state)
            STATE_B: g[1] = 1;  // Grant device 1
            STATE_C: g[2] = 1;  // Grant device 2
            STATE_D: g[3] = 1;  // Grant device 3
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t state, next_state;

    // State flip-flops (Registers)
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= STATE_A;
        else
            state <= next_state;
    end

    // State table (Next state logic)
    always @(*) begin
        case (state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A;
            end
            STATE_B: begin
                if (r[1])
                    next_state = STATE_B;
                else
                    next_state = STATE_A;
            end
            STATE_C: begin
                if (r[2])
                    next_state = STATE_C;
                else
                    next_state = STATE_A;
            end
            STATE_D: begin
                next_state = STATE_A;  // State D immediately transitions back to A
            end
            default:
                next_state = STATE_A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000;  // Default assignment
        case (state)
            STATE_A: g = 3'b000;
            STATE_B: g = 3'b001;
            STATE_C: g = 3'b010;
            STATE_D: g = 3'b100;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum logic [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= STATE_A;
        else
            state <= next_state;
    end

    // State table
    always @(*) begin
        case (state)
            STATE_A: begin
                if (r[1])
                    next_state = STATE_B;
                else if (r[2])
                    next_state = STATE_C;
                else if (!r[3])
                    next_state = STATE_D;
                else
                    next_state = STATE_A; // Stay in A if no requests
            end
            STATE_B: begin
                if (!r[1])
                    next_state = STATE_A;
                else
                    next_state = STATE_B;
            end
            STATE_C: begin
                if (!r[2])
                    next_state = STATE_A;
                else
                    next_state = STATE_C;
            end
            STATE_D: begin
                // No going back from STATE_D since it maps to STATE_A
                next_state = STATE_A;
            end
            default: next_state = STATE_A; // Default state
        endcase
    end

    // Output logic for grants
    assign g[1] = (state == STATE_B);
    assign g[2] = (state == STATE_C);
    assign g[3] = (state == STATE_D);

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        STATE_A = 2'b00,
        STATE_B = 2'b01,
        STATE_C = 2'b10,
        STATE_D = 2'b11
    } state_t;

    state_t state, next_state;

    // State flip-flops
    always @(posedge clk) begin
        if (!resetn) begin
            state <= STATE_A;
        end else begin
            state <= next_state;
        end
    end

    // State table
    always @(*) begin
        case (state)
            STATE_A: begin
                if (r[1]) begin
                    next_state = STATE_B;
                end else if (r[2]) begin
                    next_state = STATE_C;
                end else if (r[3]) begin
                    next_state = STATE_D;
                end else begin
                    next_state = STATE_A;
                end
            end
            STATE_B: begin
                if (r[1]) begin
                    next_state = STATE_B;
                end else begin
                    next_state = STATE_A;
                end
            end
            STATE_C: begin
                if (r[2]) begin
                    next_state = STATE_C;
                end else begin
                    next_state = STATE_A;
                end
            end
            STATE_D: begin
                if (r[3]) begin
                    next_state = STATE_D;
                end else begin
                    next_state = STATE_A;
                end
            end
            default: begin
                next_state = STATE_A;
            end
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default to no grants
        case (state)
            STATE_B: g[1] = 1'b1; // Grant to device 1
            STATE_C: g[2] = 1'b1; // Grant to device 2
            STATE_D: g[3] = 1'b1; // Grant to device 3
        endcase
    end

endmodule


module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 4'b0001;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd0;
        end
        else begin
            if (q == 4'd9) begin
                q <= 4'd0;
            end
            else begin
                q <= q + 4'd1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'b0000;
        else if (q == 4'b1001)
            q <= 4'b0000;
        else
            q <= q + 1;
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd0;
        end else begin
            if (q == 4'd9) begin
                q <= 4'd0;
            end else begin
                q <= q + 1'b1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd0;
        end else if (q == 4'd9) begin
            q <= 4'd0;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else begin
            if (q == 4'b1001) begin
                q <= 4'b0000;
            end else begin
                q <= q + 1'b1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000; // Synchronous reset to 0
        end
        else if (q == 4'b1001) begin
            q <= 4'b0000; // If counter is at 9, reset to 0
        end
        else begin
            q <= q + 1'b1; // Increment counter
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd0;
        end else if (q == 4'd9) begin
            q <= 4'd0;
        end else begin
            q <= q + 1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else begin
            if (q == 4'b1001)
                q <= 4'b0000;
            else
                q <= q + 1'b1;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else begin
            if (q == 4'b1001) begin
                q <= 4'b0000;
            end else begin
                q <= q + 1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1'b1;
        end
    end

endmodule


module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    // FSM State Definitions
    typedef enum reg [1:0] {
        IDLE = 2'b00,   // Waiting for the first byte with in[3] = 1
        BYTE_1 = 2'b01, // First byte received, waiting for second byte
        BYTE_2 = 2'b10  // Second byte received, waiting for third byte
    } state_t;

    reg [1:0] state, next_state;
    reg done_reg;

    // State Register
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next State Logic and Output Logic
    always @(*) begin
        // Default values
        next_state = state;
        done_reg = 1'b0;

        case (state)
            IDLE: begin
                if (in[3] == 1'b1)
                    next_state = BYTE_1;
            end
            BYTE_1: begin
                next_state = BYTE_2;
            end
            BYTE_2: begin
                done_reg = 1'b1; // Signal done on third byte
                next_state = IDLE;
            end
            default: next_state = IDLE;
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    reg [1:0] state, next_state;
    reg [1:0] byte_count;

    // State encoding
    localparam IDLE = 2'b00, BYTE1 = 2'b01, BYTE2 = 2'b10, BYTE3 = 2'b11;

    // State transition
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic and byte count
    always @(*) begin
        next_state = state; // default
        byte_count = 2'b00;
        case (state)
            IDLE: begin
                if (in[3] == 1) begin
                    next_state = BYTE1;
                    byte_count = 2'b01;
                end
            end
            BYTE1: begin
                next_state = BYTE2;
                byte_count = 2'b10;
            end
            BYTE2: begin
                next_state = BYTE3;
                byte_count = 2'b11;
            end
            BYTE3: begin
                if (in[3] == 1) begin
                    next_state = BYTE1;
                    byte_count = 2'b01;
                end else begin
                    next_state = IDLE;
                end
            end
        endcase
    end

    // Output logic
    assign done = (state == BYTE3);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    reg [1:0] state, next_state;
    reg [1:0] byte_count;

    // State encoding
    localparam IDLE = 2'd0,
               BYTE1 = 2'd1,
               BYTE2 = 2'd2,
               DONE = 2'd3;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            byte_count <= 2'd0;
        end else if (state == BYTE1 || state == BYTE2) begin
            byte_count <= byte_count + 1;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: begin
                if (in[3] == 1) begin
                    next_state = BYTE1;
                end
            end
            BYTE1: begin
                next_state = BYTE2;
            end
            BYTE2: begin
                next_state = DONE;
            end
            DONE: begin
                if (in[3] == 1) begin
                    next_state = BYTE1;
                end else begin
                    next_state = IDLE;
                end
            end
        endcase
    end

    assign done = (state == DONE);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    // State encoding
    typedef enum reg [1:0] {
        IDLE = 2'b00,
        BYTE1 = 2'b01,
        BYTE2 = 2'b10,
        BYTE3 = 2'b11
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always_comb begin
        case (state)
            IDLE: begin
                if (in[3])
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
            BYTE1: begin
                next_state = BYTE2;
            end
            BYTE2: begin
                next_state = BYTE3;
            end
            BYTE3: begin
                next_state = IDLE;
            end
            default: next_state = IDLE;
        endcase
    end

    assign done = (state == BYTE3);

endmodule

module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output done
);

    typedef enum reg [1:0] {
        IDLE = 2'b00,
        BYTE1 = 2'b01,
        BYTE2 = 2'b10,
        BYTE3 = 2'b11
    } state_t;

    reg [1:0] state, next_state;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        case (state)
            IDLE: begin
                if (in[3] == 1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end

            BYTE1: begin
                next_state = BYTE2;
            end

            BYTE2: begin
                next_state = BYTE3;
            end

            BYTE3: begin
                next_state = IDLE;
            end

            default: next_state = IDLE;
        endcase
    end

    assign done = (state == BYTE3);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output reg done
);

    reg [1:0] state, next_state;

    // State encoding
    localparam WAIT_FIRST_BYTE = 2'b00;
    localparam BYTE_ONE        = 2'b01;
    localparam BYTE_TWO        = 2'b10;
    localparam BYTE_THREE      = 2'b11;

    // State transition
    always @(posedge clk) begin
        if (reset)
            state <= WAIT_FIRST_BYTE;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (state)
            WAIT_FIRST_BYTE: begin
                if (in[3])
                    next_state = BYTE_ONE;
                else
                    next_state = WAIT_FIRST_BYTE;
            end
            BYTE_ONE: begin
                next_state = BYTE_TWO;
            end
            BYTE_TWO: begin
                next_state = BYTE_THREE;
            end
            BYTE_THREE: begin
                next_state = WAIT_FIRST_BYTE;
            end
            default: begin
                next_state = WAIT_FIRST_BYTE;
            end
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset)
            done <= 0;
        else if (state == BYTE_THREE)
            done <= 1;
        else
            done <= 0;
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output reg done
);

    // State encoding
    typedef enum reg [1:0] {
        IDLE  = 2'b00,
        BYTE1 = 2'b01,
        BYTE2 = 2'b10,
        BYTE3 = 2'b11
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (in[3] == 1'b1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
            BYTE1: next_state = BYTE2;
            BYTE2: next_state = BYTE3;
            BYTE3: next_state = IDLE;
            default: next_state = IDLE;
        endcase
    end

    // State flip-flops with synchronous reset
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        if (state == BYTE3)
            done = 1'b1;
        else
            done = 1'b0;
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output reg done
);

    reg [1:0] state, next_state;

    localparam WAIT   = 2'b00,
               BYTE1  = 2'b01,
               BYTE2  = 2'b10,
               BYTE3  = 2'b11;

    // State transition logic
    always @(*) begin
        case (state)
            WAIT:  next_state = (in[3] == 1'b1) ? BYTE1 : WAIT;
            BYTE1: next_state = BYTE2;
            BYTE2: next_state = BYTE3;
            BYTE3: next_state = (in[3] == 1'b1) ? BYTE1 : WAIT;
            default: next_state = WAIT;
        endcase
    end

    // State flip-flops with synchronous reset
    always @(posedge clk) begin
        if (reset)
            state <= WAIT;
        else
            state <= next_state;
    end

    // Output logic
    always @(posedge clk) begin
        if (reset)
            done <= 1'b0;
        else
            done <= (state == BYTE3);
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    // FSM state declaration
    typedef enum logic [1:0] {
        IDLE = 2'b00,
        BYTE1 = 2'b01,
        BYTE2 = 2'b10,
        BYTE3 = 2'b11
    } state_t;

    state_t current_state, next_state;
    logic done_reg;

    assign done = done_reg;

    always_ff @(posedge clk) begin
        if (reset) begin
            current_state <= IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    always_comb begin
        done_reg = 1'b0;
        next_state = current_state;

        case (current_state)
            IDLE: begin
                if (in[3] == 1'b1) begin
                    next_state = BYTE1;
                end
            end

            BYTE1: begin
                next_state = BYTE2;
            end

            BYTE2: begin
                next_state = BYTE3;
            end

            BYTE3: begin
                done_reg = 1'b1;
                if (in[3] == 1'b1) begin
                    next_state = BYTE1;
                end else begin
                    next_state = IDLE;
                end
            end

            default: begin
                next_state = IDLE;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    // State encoding
    typedef enum logic [1:0] {
        IDLE = 2'b00,
        BYTE_1 = 2'b01,
        BYTE_2 = 2'b10,
        BYTE_3 = 2'b11
    } state_t;

    state_t state, next_state;

    // State transition
    always_ff @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always_comb begin
        case (state)
            IDLE: begin
                if (in[3] == 1) begin
                    next_state = BYTE_1;
                end else begin
                    next_state = IDLE;
                end
            end
            BYTE_1: begin
                next_state = BYTE_2;
            end
            BYTE_2: begin
                next_state = BYTE_3;
            end
            BYTE_3: begin
                if (in[3] == 1) begin
                    next_state = BYTE_1;
                end else begin
                    next_state = IDLE;
                end
            end
            default: begin
                next_state = IDLE;
            end
        endcase
    end

    // Output logic
    assign done = (state == BYTE_3);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    typedef enum reg [1:0] {
        WAIT_BYTE_1 = 2'b00,
        BYTE_2 = 2'b01,
        BYTE_3 = 2'b10
    } state_t;

    reg [1:0] state, next_state;
    assign done = (state == BYTE_3); // Signal done in the cycle after BYTE_3

    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT_BYTE_1;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        case(state)
            WAIT_BYTE_1: begin
                if (in[3] == 1) begin
                    next_state = BYTE_2;   // Found start of a new message
                end
            end
            BYTE_2: begin
                next_state = BYTE_3;       // Transition to byte 3
            end
            BYTE_3: begin
                next_state = WAIT_BYTE_1;  // Go back to waiting for a new message
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    reg [1:0] state, next_state;
    reg [1:0] byte_counter;

    // State encoding
    localparam IDLE   = 2'd0;
    localparam BYTE_1 = 2'd1;
    localparam BYTE_2 = 2'd2;
    localparam BYTE_3 = 2'd3;

    // State transition logic
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (in[3] == 1'b1) begin
                    next_state = BYTE_1;
                end else begin
                    next_state = IDLE;
                end
            end
            BYTE_1: next_state = BYTE_2;
            BYTE_2: next_state = BYTE_3;
            BYTE_3: begin
                if (in[3] == 1'b1) begin
                    next_state = BYTE_1; // Possible start of a new message
                end else begin
                    next_state = IDLE;
                end
            end
            default: next_state = IDLE;
        endcase
    end

    // Output logic
    assign done = (state == BYTE_3);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output reg done
);

    reg [1:0] state, next_state;
    reg [1:0] byte_count;

    // State encoding
    localparam IDLE = 2'd0;
    localparam BYTE1 = 2'd1;
    localparam BYTE2 = 2'd2;
    localparam BYTE3 = 2'd3;

    // State transition logic
    always @(*) begin
        case (state)
            IDLE: next_state = (in[3] == 1) ? BYTE1 : IDLE;
            BYTE1: next_state = BYTE2;
            BYTE2: next_state = BYTE3;
            BYTE3: next_state = (in[3] == 1) ? BYTE1 : IDLE;
            default: next_state = IDLE;
        endcase
    end

    // State register
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Byte count logic
    always @(posedge clk) begin
        if (reset) begin
            byte_count <= 2'd0;
        end else if (state == BYTE3) begin
            byte_count <= 2'd0;
        end else if (state != IDLE) begin
            byte_count <= byte_count + 2'd1;
        end
    end

    // Output logic
    always @(posedge clk) begin
        if (reset) begin
            done <= 1'b0;
        end else if (state == BYTE3 && byte_count == 2'd2) begin
            done <= 1'b1;
        end else begin
            done <= 1'b0;
        end
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    typedef enum reg [1:0] {
        WAIT_FOR_FIRST_BYTE = 2'b00,
        SECOND_BYTE = 2'b01,
        THIRD_BYTE = 2'b10
    } state_type;

    state_type state, next_state;
    reg done_reg;

    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT_FOR_FIRST_BYTE;
            done_reg <= 0;
        end else begin
            state <= next_state;
            done_reg <= (state == THIRD_BYTE);
        end
    end

    always @(*) begin
        next_state = state; // Default to stay in the same state
        case (state)
            WAIT_FOR_FIRST_BYTE: begin
                if (in[3] == 1'b1) begin
                    next_state = SECOND_BYTE;
                end
            end
            SECOND_BYTE: begin
                next_state = THIRD_BYTE;
            end
            THIRD_BYTE: begin
                next_state = WAIT_FOR_FIRST_BYTE;
            end
        endcase
    end

    assign done = done_reg;

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);
    // State encoding
    parameter IDLE = 2'b00,
              BYTE1 = 2'b01,
              BYTE2 = 2'b10,
              BYTE3 = 2'b11;

    reg [1:0] state, next_state;
    reg done_reg;

    assign done = done_reg;

    // State transition
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (in[3] == 1'b1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
            BYTE1: begin
                next_state = BYTE2;
            end
            BYTE2: begin
                next_state = BYTE3;
            end
            BYTE3: begin
                next_state = IDLE;
            end
            default: begin
                next_state = IDLE;
            end
        endcase
    end

    // Output logic
    always @(posedge clk) begin
        if (reset) begin
            done_reg <= 1'b0;
        end else if (state == BYTE3) begin
            done_reg <= 1'b1;
        end else begin
            done_reg <= 1'b0;
        end
    end

endmodule

module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output reg done
);

    // State Encoding
    typedef enum reg [1:0] {
        WAIT_FOR_FIRST_BYTE = 2'b00,
        BYTE_ONE_RECEIVED   = 2'b01,
        BYTE_TWO_RECEIVED   = 2'b10
    } state_t;

    state_t state, next_state;

    // State Transition Logic
    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT_FOR_FIRST_BYTE;
        end else begin
            state <= next_state;
        end
    end

    // Next State Logic
    always @(*) begin
        next_state = state; // default to hold state
        done = 0;
        case (state)
            WAIT_FOR_FIRST_BYTE: begin
                if (in[3] == 1) begin
                    next_state = BYTE_ONE_RECEIVED;
                end
            end
            BYTE_ONE_RECEIVED: begin
                next_state = BYTE_TWO_RECEIVED;
            end
            BYTE_TWO_RECEIVED: begin
                done = 1;
                next_state = WAIT_FOR_FIRST_BYTE;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    parameter IDLE = 2'b00, BYTE1 = 2'b01, BYTE2 = 2'b10, BYTE3 = 2'b11;
    reg [1:0] state, next_state;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        case(state)
            IDLE: next_state = (in[3] == 1'b1) ? BYTE1 : IDLE;
            BYTE1: next_state = BYTE2;
            BYTE2: next_state = BYTE3;
            BYTE3: next_state = (in[3] == 1'b1) ? BYTE1 : IDLE;
            default: next_state = IDLE;
        endcase
    end

    assign done = (state == BYTE3);

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output reg done
);

    typedef enum reg [1:0] {
        IDLE = 2'b00,
        BYTE1 = 2'b01,
        BYTE2 = 2'b10,
        BYTE3 = 2'b11
    } state_t;

    state_t state, next_state;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    always @(*) begin
        done = 0;
        case (state)
            IDLE: begin
                if (in[3] == 1'b1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
            BYTE1: next_state = BYTE2;
            BYTE2: next_state = BYTE3;
            BYTE3: begin
                done = 1;
                if (in[3] == 1'b1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input [7:0] in,
    input reset,
    output done
);

    // State Encoding
    typedef enum logic [1:0] {
        IDLE  = 2'd0,
        BYTE1 = 2'd1,
        BYTE2 = 2'd2,
        BYTE3 = 2'd3
    } state_t;

    state_t state, next_state;

    // State Transition
    always_ff @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end

    // Next State Logic
    always_comb begin
        next_state = state; // Default state assignment
        case (state)
            IDLE: begin
                if (in[3] == 1)
                    next_state = BYTE1;
            end
            BYTE1: begin
                next_state = BYTE2;
            end
            BYTE2: begin
                next_state = BYTE3;
            end
            BYTE3: begin
                if (in[3] == 1)
                    next_state = BYTE1;
                else
                    next_state = IDLE;
            end
        endcase
    end

    // Output Logic
    assign done = (state == BYTE3);

endmodule

module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output done
);

    reg [1:0] state, next_state;
    reg done_reg;

    localparam WAIT = 2'b00,
               BYTE1 = 2'b01,
               BYTE2 = 2'b10,
               BYTE3 = 2'b11;

    // State Transition
    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT;
        end else begin
            state <= next_state;
        end
    end

    // Next State Logic
    always @(*) begin
        done_reg = 0;
        case (state)
            WAIT: begin
                if (in[3] == 1'b1) begin
                    next_state = BYTE1;
                end else begin
                    next_state = WAIT;
                end
            end
            BYTE1: begin
                next_state = BYTE2;
            end
            BYTE2: begin
                next_state = BYTE3;
            end
            BYTE3: begin
                next_state = WAIT;
                done_reg = 1;
            end
            default: begin
                next_state = WAIT;
            end
        endcase
    end

    // Output Logic
    assign done = done_reg;

endmodule


module top_module (
    input a,
    input b,
    input sel,
    output out
);
    assign out = sel ? b : a;
endmodule

module top_module (
	input a,
	input b,
	input sel,
	output out
);

	assign out = (sel) ? b : a;

endmodule

module top_module (
    input a,
    input b,
    input sel,
    output out
);
    assign out = (sel == 1'b0) ? a : b;
endmodule


module top_module (
	input [3:0] in,
	output out_and,
	output out_or,
	output out_xor
);

    assign out_and = in[3] & in[2] & in[1] & in[0];
    assign out_or = in[3] | in[2] | in[1] | in[0];
    assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];

endmodule

module top_module (
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and = in[0] & in[1] & in[2] & in[3];
    assign out_or = in[0] | in[1] | in[2] | in[3];
    assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];

endmodule