---------------custom config-------------- run: mode: autoline save: en: True pub: prefix: SimpleSPI subdir: MyExperimentsSimple gpt: model: qwen-max rtlgen_model: qwen-max autoline: result_path: results/myproject_simple_spi cga: enabled: True max_iter: 15 target_coverage: 85.0 probset: path: data/myproject/spi_controller_simple.jsonl mutant_path: None more_info_paths: [] only: ['spi_controller_simple'] promptscript: pychecker timeout: 300 save_compile: False debug: max: 3 itermax: 10 update_desc: False TBcheck: discrim_mode: col_70_wrong_row_25_correct ------------------------------------------ ------config info (custom + default)------ run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: 20260406_142058 custom_path: config/myproject_simple_spi.yaml mode: autoline hostname: localhost pid: 1920 pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0] save: en: True root: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/ pub: prefix: SimpleSPI dir: saves/0406~0412/ subdir: MyExperimentsSimple/ log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: qwen-max key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: qwen-max iverilog: dir: task_id: autoline: result_path: results/myproject_simple_spi cga: enabled: True max_iter: 15 target_coverage: 85.0 probset: path: data/myproject/spi_controller_simple.jsonl mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['spi_controller_simple'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 3 reboot: 1 py_rollback: 2 onlyrun: None promptscript: pychecker timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_70_wrong_row_25_correct correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: False save_finalcodes: True error_interruption: False _initialized: True ------------------------------------------ --------------default config-------------- run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: None custom_path: None mode: qwen-max save: en: True root: None pub: prefix: None dir: saves/$weekrange$/ subdir: log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: 4o key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: None iverilog: dir: task_id: autoline: result_path: results cga: enabled: True max_iter: 10 target_coverage: 100.0 probset: path: None mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['lemmings3', 'lemmings4', 'ece241_2013_q8', '2014_q3fsm', 'm2014_q6', 'review2015_fsm', 'rule110', 'fsm_ps2'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 5 reboot: 1 py_rollback: 2 onlyrun: None promptscript: None timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_full_wrong correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: True save_finalcodes: True error_interruption: False ------------------------------------------ 2026-04-06 14:20:58 | INFO | all configurations are loaded, starting the main process... 2026-04-06 14:20:58 | INFO | 2026-04-06 14:20:58 | INFO | ######################### task 1/1 [spi_controller_simple] ######################### 2026-04-06 14:21:38 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (39.56s used) 2026-04-06 14:22:02 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (23.55s used) 2026-04-06 14:55:47 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (2025.00s used) 2026-04-06 14:56:28 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (41.46s used) 2026-04-06 14:59:12 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (164.09s used) 2026-04-06 14:59:12 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used) 2026-04-06 15:23:48 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (1475.45s used) 2026-04-06 15:24:31 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (43.01s used) 2026-04-06 15:24:31 | INFO | [spi_controller_simple] 2026-04-06 15:24:31 | INFO | [spi_controller_simple] [TBsim] iverilog simulation failed! Debuging... (debug_iter = 1) 2026-04-06 16:43:36 | ERROR | [spi_controller_simple] Error when running TBsim, iter: 1. Message: list index out of range | location: autoline/TB_autoline.py, func: run_stages_core, line: 361 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317 2026-04-06 16:43:36 | WARNING | [spi_controller_simple] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 366 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317 2026-04-06 16:44:20 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (26.01s used) 2026-04-06 16:45:07 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (47.46s used) 2026-04-06 16:46:01 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (53.87s used) 2026-04-06 16:46:53 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (51.75s used) 2026-04-06 16:49:35 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (162.36s used) 2026-04-06 16:49:35 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used) 2026-04-06 16:54:38 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (302.79s used) 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (55.60s used) 2026-04-06 16:55:34 | INFO | [spi_controller_simple] 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] iverilog compilation : passed! 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] python simulation : passed! 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBsim] TBsim finished : True! 2026-04-06 16:55:34 | INFO | [spi_controller_simple] 2026-04-06 16:55:34 | INFO | [spi_controller_simple] rtl list not found, generating naive rtls for testbench checking 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: missing_assignment | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_bit | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33 2026-04-06 16:55:34 | INFO | [spi_controller_simple] 20 mutation-based RTLs generated (from reference RTL) 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Capturing Reference RTL outputs as ground truth... 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Capturing Reference RTL outputs as ground truth... 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Reference RTL check results: failed scenarios = [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10], passed scenarios = [] 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Captured Reference RTL outputs for 10 scenarios 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Captured outputs for 10 scenarios 2026-04-06 16:55:34 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination 2026-04-06 16:55:35 | POSITIVE | [spi_controller_simple] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 0/10 2026-04-06 16:55:35 | INFO | [spi_controller_simple] [TBcheck] Testbench passed the funccheck 2026-04-06 16:55:35 | INFO | [spi_controller_simple] [TBcheck] self funccheck finished. Next Action: [pass] 2026-04-06 16:55:35 | INFO | [spi_controller_simple] 2026-04-06 16:55:35 | INFO | [spi_controller_simple] [spi_controller_simple] Starting Coverage-Guided Agent (CGA)... 2026-04-06 16:55:35 | INFO | [spi_controller_simple] [spi_controller_simple] Running Semantic Analysis (Layer 0)... 2026-04-06 16:55:35 | INFO | [spi_controller_simple] FSM detected: state (4 states) 2026-04-06 16:55:35 | INFO | [spi_controller_simple] Total function points identified: 8 2026-04-06 16:55:35 | INFO | [spi_controller_simple] Energy allocator initialized: 8 targets 2026-04-06 16:55:35 | INFO | [spi_controller_simple] Diversity injector initialized with history file: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/test_history.json 2026-04-06 16:55:35 | INFO | [spi_controller_simple] Quality evaluator initialized 2026-04-06 16:55:35 | INFO | [spi_controller_simple] --- CGA Iter 0 (Baseline) --- 2026-04-06 16:55:38 | INFO | [spi_controller_simple] Baseline Coverage: 77.55% 2026-04-06 16:55:38 | INFO | [spi_controller_simple] --- CGA Iter 1 / 15 --- 2026-04-06 16:55:38 | INFO | [spi_controller_simple] Target: Exception_DefaultCase 2026-04-06 16:55:38 | INFO | [spi_controller_simple] Asking LLM to fix missing logic (Current: 77.55%)... 2026-04-06 16:56:28 | ERROR | [spi_controller_simple] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1295 2026-04-06 16:56:28 | ERROR | [spi_controller_simple] [CGA-1] Verilator compilation failed: | location: autoline/TB_cga.py, func: run, line: 1301 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301 2026-04-06 16:56:28 | ERROR | [spi_controller_simple] obj_dir not created - compilation failed early | location: autoline/TB_cga.py, func: run, line: 1302 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301 2026-04-06 16:56:28 | INFO | [spi_controller_simple] [CGA-1] Asking LLM to fix compilation errors... 2026-04-06 16:57:11 | ERROR | [spi_controller_simple] Verilator Compile Failed. | location: utils/verilator_call.py, func: verilator_run_coverage, line: 242 | caller: location: autoline/TB_cga.py, func: run, line: 1324 2026-04-06 16:57:11 | INFO | [spi_controller_simple] Quality Evaluation: diversity=1.00 2026-04-06 16:57:11 | WARNING | [spi_controller_simple] Regression or Failure. Discarding changes. | location: autoline/TB_cga.py, func: run, line: 1416 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301 2026-04-06 16:57:11 | INFO | [spi_controller_simple] --- CGA Iter 2 / 15 --- 2026-04-06 16:57:11 | INFO | [spi_controller_simple] Target: Condition_4 2026-04-06 16:57:11 | INFO | [spi_controller_simple] Asking LLM to fix missing logic (Current: 77.55%)... 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Quality Evaluation: diversity=0.49 2026-04-06 16:58:11 | SUCCESS | [spi_controller_simple] Coverage Improved! +16.33% (77.55% -> 93.88%) 2026-04-06 16:58:11 | SUCCESS | [spi_controller_simple] Target coverage reached! 2026-04-06 16:58:11 | INFO | [spi_controller_simple] CGA Finished. Final Coverage: 93.88% 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Energy report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/energy_report.txt 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Diversity report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/diversity_report.txt 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Quality evaluation report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/CGA/quality_evaluation_report.txt 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Semantic Coverage: 72.02% 2026-04-06 16:58:11 | INFO | [spi_controller_simple] Saved optimized TB to: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_142058/spi_controller_simple/final_TB.v 2026-04-06 16:58:11 | INFO | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking begins 2026-04-06 16:58:11 | FAILED | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking failed! 2026-04-06 16:58:11 | INFO | [spi_controller_simple] [TBeval] [spi_controller_simple] Eval 2/2b is skipped because Eval 1 failed 2026-04-06 16:58:11 | INFO | [spi_controller_simple] 2026-04-06 16:58:11 | INFO | ########## Analyze of Chatbench_RunInfo ########## #### pass numbers: Eval2 : 0 Eval1 : 0 Eval0 : 1 total : 1 (Failed: 0) passed TB by autoline reboot action (from TB3_check): 0 passed TB by functional corrector: 0 #### CGA Coverage Info: Average Coverage : 93.88% Max Coverage : 93.88% Min Coverage : 93.88% #### tokens and cost: average prompt tokens: 30199 average completion tokens: 25441 total cost: 2.1304 average cost: 2.1304 #### time: average time: 9432.35s #### debug info table: FUNCTIONAL debug info table: (debugged here means functional debugging) | un-func-debugged | func-debugged | total | failed | 0 | 0 | 0 | Eval0 | 0 | 1 | 1 | Eval1 | 0 | 0 | 0 | Eval2 | 0 | 0 | 0 | #### Eval2 ratio: #### CGA Coverage Detail List: Task ID | Coverage ---------------------------------------- spi_controller_simple | 93.88% loose Eval2 pass metric applied: 0.8