---------------custom config-------------- run: mode: autoline save: en: True pub: prefix: SimpleSPI subdir: MyExperimentsSimple gpt: model: qwen-max rtlgen_model: qwen-max autoline: result_path: results/myproject_simple_spi cga: enabled: True max_iter: 15 target_coverage: 85.0 probset: path: data/myproject/spi_controller_simple.jsonl mutant_path: None more_info_paths: [] only: ['spi_controller_simple'] promptscript: pychecker timeout: 300 save_compile: False debug: max: 3 itermax: 10 update_desc: False TBcheck: discrim_mode: col_70_wrong_row_25_correct ------------------------------------------ ------config info (custom + default)------ run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: 20260406_130913 custom_path: config/myproject_simple_spi.yaml mode: autoline hostname: localhost pid: 25443 pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0] save: en: True root: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260406_130913/ pub: prefix: SimpleSPI dir: saves/0406~0412/ subdir: MyExperimentsSimple/ log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: qwen-max key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: qwen-max iverilog: dir: task_id: autoline: result_path: results/myproject_simple_spi cga: enabled: True max_iter: 15 target_coverage: 85.0 probset: path: data/myproject/spi_controller_simple.jsonl mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['spi_controller_simple'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 3 reboot: 1 py_rollback: 2 onlyrun: None promptscript: pychecker timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_70_wrong_row_25_correct correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: False save_finalcodes: True error_interruption: False _initialized: True ------------------------------------------ --------------default config-------------- run: version: 2.0 author: Ruidi Qiu - Technical University of Munich time: None custom_path: None mode: qwen-max save: en: True root: None pub: prefix: None dir: saves/$weekrange$/ subdir: log: en: True dir: logs/ notes: None cfg_pmode: iwantall debug_en: False level: TRACE message: en: True dir: messages/ format: json iverilog: en: True subdir: ivcode_nodebug load: prompt: path: config/initial_prompts/prompt1.txt pick_idx: [] stage_template: path: config/templates/stage_template0301.txt gpt: model: 4o key_path: config/key_API.json temperature: None json_mode: False chatgpt: start_form: chat one_time_talk: False rtlgen_model: None iverilog: dir: task_id: autoline: result_path: results cga: enabled: True max_iter: 10 target_coverage: 100.0 probset: path: None mutant_path: None gptgenRTL_path: None more_info_paths: [] only: ['lemmings3', 'lemmings4', 'ece241_2013_q8', '2014_q3fsm', 'm2014_q6', 'review2015_fsm', 'rule110', 'fsm_ps2'] exclude: [] exclude_json: None filter: [{}] checklist: max: 3 debug: max: 5 reboot: 1 py_rollback: 2 onlyrun: None promptscript: None timeout: 300 TBcheck: rtl_num: 20 correct_max: 3 discrim_mode: col_full_wrong correct_mode: naive rtl_compens_en: True rtl_compens_max_iter: 3 itermax: 10 update_desc: False save_compile: True save_finalcodes: True error_interruption: False ------------------------------------------ 2026-04-06 13:09:13 | INFO | all configurations are loaded, starting the main process... 2026-04-06 13:09:13 | INFO | 2026-04-06 13:09:13 | INFO | ######################### task 1/1 [spi_controller_simple] ######################### 2026-04-06 13:09:41 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (27.44s used) 2026-04-06 13:10:22 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (40.66s used) 2026-04-06 13:11:20 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (58.14s used) 2026-04-06 13:12:54 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (94.01s used) 2026-04-06 13:15:32 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (158.74s used) 2026-04-06 13:15:32 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used)