module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIG
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= STATE_WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @* begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = STATE_DIG;
                    digging = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = STATE_DIG;
                    digging = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (bump_left) begin
                        next_state = STATE_WALK_RIGHT;
                    end else if (bump_right) begin
                        next_state = STATE_WALK_LEFT;
                    end else begin
                        if (walk_left) begin
                            next_state = STATE_WALK_LEFT;
                        end else begin
                            next_state = STATE_WALK_RIGHT;
                        end
                    end
                end else begin
                    next_state = STATE_FALL;
                end
            end

            STATE_DIG: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else begin
                    next_state = STATE_DIG;
                end
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALLING,
        DIGGING,
        WAIT_FOR_GROUND
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= WALK_LEFT;
        else
            current_state <= next_state;
    end

    always_ff @(current_state or bump_left or bump_right or ground or dig) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        next_state = current_state;

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                } else if (dig) begin
                    next_state = DIGGING;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else if (dig) begin
                    next_state = DIGGING;
                end
            end

            FALLING: begin
                aaah = 1;
                if (ground) begin
                    next_state = (walk_left) ? WALK_LEFT : WALK_RIGHT;
                end
            end

            DIGGING: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end
            end

            default: next_state = WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [1:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALLING,
        DIGGING
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state; // Default to current state
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_RIGHT;
                end else if (bump_right) begin
                    next_state = WALK_LEFT;
                end else if (dig) begin
                    next_state = DIGGING;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_RIGHT;
                end else if (bump_right) begin
                    next_state = WALK_LEFT;
                end else if (dig) begin
                    next_state = DIGGING;
                end
            end

            FALLING: begin
                aaah = 1;
                if (ground) begin
                    if (current_state == FALLING) begin
                        next_state = (walk_left) ? WALK_LEFT : WALK_RIGHT; // Resume previous direction
                    end
                end
            end

            DIGGING: begin
                digging = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (ground) begin
                    next_state = WALK_LEFT; // Resume left walking as default after digging
                end
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALLING,
        DIGGING
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        aaah <= (current_state == FALLING);
        digging <= (current_state == DIGGING);
        walk_left <= (current_state == WALK_LEFT);
        walk_right <= (current_state == WALK_RIGHT);
    end

    always_comb begin
        next_state = current_state;

        case (current_state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALLING;
                end else if (dig) begin
                    next_state = DIGGING;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALLING;
                end else if (dig) begin
                    next_state = DIGGING;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end
            end

            FALLING: begin
                if (ground) begin
                    if (bump_left) begin
                        next_state = WALK_RIGHT;
                    end else if (bump_right) begin
                        next_state = WALK_LEFT;
                    end else begin
                        next_state = (walk_left) ? WALK_LEFT : WALK_RIGHT;
                    end
                end
            end

            DIGGING: begin
                if (!ground) begin
                    next_state = FALLING;
                end
                // Bumps and ground do not affect digging
            end

            default: begin
                next_state = WALK_LEFT; // Fallback to a default state
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        S_WALK_LEFT,
        S_WALK_RIGHT,
        S_FALL,
        S_DIG
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= S_WALK_LEFT;
        else
            state <= next_state;
    end

    always_ff @(state or bump_left or bump_right or ground or dig) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        next_state = state;

        case (state)
            S_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = S_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = S_DIG;
                    digging = 1;
                end else if (bump_right)
                    next_state = S_WALK_RIGHT;
            end

            S_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = S_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = S_DIG;
                    digging = 1;
                end else if (bump_left)
                    next_state = S_WALK_LEFT;
            end

            S_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (walk_left)
                        next_state = S_WALK_LEFT;
                    else
                        next_state = S_WALK_RIGHT;
                end
            end

            S_DIG: begin
                digging = 1;
                if (!ground)
                    next_state = S_FALL;
                else if (bump_left || bump_right)
                    next_state = S_DIG;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

typedef enum reg [1:0] {
    WALK_LEFT = 2'b00,
    WALK_RIGHT = 2'b01,
    FALL = 2'b10,
    DIGGING = 2'b11
} state_t;

state_t current_state, next_state;

always_ff @(posedge clk or posedge areset) begin
    if (areset) begin
        current_state <= WALK_LEFT;
    end else begin
        current_state <= next_state;
    end
end

always_comb begin
    // Default outputs
    walk_left = 0;
    walk_right = 0;
    aaah = 0;
    digging = 0;
    next_state = current_state;

    case (current_state)
        WALK_LEFT: begin
            walk_left = 1;
            if (!ground) begin
                next_state = FALL;
                aaah = 1;
            end else if (dig) begin
                next_state = DIGGING;
                digging = 1;
            end else if (bump_left) begin
                next_state = WALK_RIGHT;
            end
        end

        WALK_RIGHT: begin
            walk_right = 1;
            if (!ground) begin
                next_state = FALL;
                aaah = 1;
            end else if (dig) begin
                next_state = DIGGING;
                digging = 1;
            end else if (bump_right) begin
                next_state = WALK_LEFT;
            end
        end

        FALL: begin
            aaah = 1;
            if (ground) begin
                if (current_state == FALL) begin
                    if (walk_left) next_state = WALK_LEFT;
                    else if (walk_right) next_state = WALK_RIGHT;
                end
            end
        end

        DIGGING: begin
            digging = 1;
            if (!ground) begin
                next_state = FALL;
                aaah = 1;
            end else if (ground) begin
                next_state = WALK_LEFT;
                if (walk_left) walk_left = 1;
                else if (walk_right) walk_right = 1;
            end
        end
    endcase
end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIG
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            state <= STATE_WALK_LEFT;
        else
            state <= next_state;
    end

    always @(*) begin
        next_state = state;
        aaah = 0;
        digging = 0;

        case (state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                walk_right = 0;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                } else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_FALL: begin
                walk_left = 0;
                walk_right = 0;
                if (ground) begin
                    if (bump_left)
                        next_state = STATE_WALK_RIGHT;
                    else if (bump_right)
                        next_state = STATE_WALK_LEFT;
                    else if (dig)
                        next_state = STATE_DIG;
                    else
                        next_state = (walk_left) ? STATE_WALK_LEFT : STATE_WALK_RIGHT;
                end else begin
                    aaah = 1;
                end
            end

            STATE_DIG: begin
                walk_left = 0;
                walk_right = 0;
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end
            end

            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

typedef enum logic [1:0] {
	WALK_LEFT,
	WALK_RIGHT,
	FALLING,
	DIGGING
} state_t;

state_t current_state, next_state;

always_ff @(posedge clk or posedge areset) begin
	if (areset) begin
		current_state <= WALK_LEFT;
	end else begin
		current_state <= next_state;
	end
end

always_comb begin
	next_state = current_state;
	walk_left = 1'b0;
	walk_right = 1'b0;
	aaah = 1'b0;
	digging = 1'b0;

	case (current_state)
		WALK_LEFT: begin
			walk_left = 1'b1;
			if (~ground) begin
				next_state = FALLING;
				aaah = 1'b1;
			end else if (dig) begin
				next_state = DIGGING;
				digging = 1'b1;
			end else if (bump_right) begin
				next_state = WALK_RIGHT;
			end
		end

		WALK_RIGHT: begin
			walk_right = 1'b1;
			if (~ground) begin
				next_state = FALLING;
				aaah = 1'b1;
			end else if (dig) begin
				next_state = DIGGING;
				digging = 1'b1;
			end else if (bump_left) begin
				next_state = WALK_LEFT;
			end
		end

		FALLING: begin
			aaah = 1'b1;
			if (ground) begin
				if (current_state == FALLING) next_state = (walk_left ? WALK_LEFT : WALK_RIGHT);
			end
		end

		DIGGING: begin
			digging = 1'b1;
			if (~ground) begin
				next_state = FALLING;
				aaah = 1'b1;
			end
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIG
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= STATE_WALK_LEFT;
        else
            current_state <= next_state;
    end

    always_ff @(current_state, bump_left, bump_right, ground, dig) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        next_state = current_state;

        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                aaah = 0;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                aaah = 0;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (current_state == STATE_WALK_LEFT)
                        next_state = STATE_WALK_LEFT;
                    else
                        next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_DIG: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end
            end

            default: begin
                next_state = STATE_WALK_LEFT;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

	typedef enum reg [2:0] {
		WALK_LEFT,
		WALK_RIGHT,
		FALLING,
		DIGGING,
	} state_t;

	state_t state, next_state;

	always @(posedge clk or posedge areset) begin
		if (areset)
			state <= WALK_LEFT;
		else
			state <= next_state;
	end

	always @(*) begin
		next_state = state;
		aaah = 0;
		digging = 0;
		walk_left = 0;
		walk_right = 0;

		case (state)
			WALK_LEFT: begin
				walk_left = 1;
				if (!ground) begin
					aaah = 1;
					next_state = FALLING;
				end else if (dig) begin
					next_state = DIGGING;
					digging = 1;
				end else if (bump_right) begin
					next_state = WALK_RIGHT;
				end
			end

			WALK_RIGHT: begin
				walk_right = 1;
				if (!ground) begin
					aaah = 1;
					next_state = FALLING;
				end else if (dig) begin
					next_state = DIGGING;
					digging = 1;
				end else if (bump_left) begin
					next_state = WALK_LEFT;
				end
			end

			FALLING: begin
				aaah = 1;
				if (ground) begin
					if (walk_left)
						next_state = WALK_LEFT;
					else
						next_state = WALK_RIGHT;
				end
			end

			DIGGING: begin
				digging = 1;
				if (!ground) begin
					aaah = 1;
					next_state = FALLING;
				end else if (ground) begin
					next_state = WALK_LEFT; // Default back to the left when done
				end
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIG,
        STATE_WAIT_GROUND
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= STATE_WALK_LEFT;
        else
            state <= next_state;
    end

    always_ff @(state or bump_left or bump_right or ground or dig) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                } else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                } else if (dig) begin
                    next_state = STATE_DIG;
                end
            end

            STATE_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (walk_left)
                        next_state = STATE_WALK_LEFT;
                    else
                        next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_DIG: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALL,
        DIGGING
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= WALK_LEFT;
        else
            current_state <= next_state;
    end

    always_comb begin
        next_state = current_state;
        aaah = 1'b0; // Default no aaah sound
        digging = 1'b0; // Default not digging
        walk_left = 1'b0; // Default not walking left
        walk_right = 1'b0; // Default not walking right

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1'b1;
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1'b1;
                end else if (dig) begin
                    next_state = DIGGING;
                    digging = 1'b1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1'b1;
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1'b1;
                end else if (dig) begin
                    next_state = DIGGING;
                    digging = 1'b1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end
            end

            FALL: begin
                aaah = 1'b1;
                if (ground) begin
                    if (current_state == WALK_LEFT)
                        next_state = WALK_LEFT;
                    else if (current_state == WALK_RIGHT)
                        next_state = WALK_RIGHT;
                end
            end

            DIGGING: begin
                digging = 1'b1;
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1'b1;
                end else if (ground) begin
                    next_state = (current_state == WALK_LEFT) ? WALK_LEFT : WALK_RIGHT;
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALLING,
        DIGGING,
        DIGGING_FALL
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (dig) begin
                    next_state = DIGGING;
                    digging = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (dig) begin
                    next_state = DIGGING;
                    digging = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end
            end

            FALLING: begin
                aaah = 1;
                if (ground) begin
                    if (walk_left) begin
                        next_state = WALK_LEFT;
                    end else if (walk_right) begin
                        next_state = WALK_RIGHT;
                    end
                end
            end

            DIGGING: begin
                digging = 1;
                if (!ground) begin
                    next_state = DIGGING_FALL;
                    aaah = 1;
                end
            end

            DIGGING_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (walk_left) begin
                        next_state = WALK_LEFT;
                    end else if (walk_right) begin
                        next_state = WALK_RIGHT;
                    end
                end
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

	typedef enum reg [2:0] {
		STATE_WALK_LEFT,
		STATE_WALK_RIGHT,
		STATE_FALL,
		STATE_DIG
	} state_t;

	state_t state, next_state;

	always @(posedge clk or posedge areset) begin
		if (areset) begin
			state <= STATE_WALK_LEFT;
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		walk_left = 0;
		walk_right = 0;
		aaah = 0;
		digging = 0;
		next_state = state;

		case (state)
			STATE_WALK_LEFT: begin
				walk_left = 1;
				if (!ground) begin
					aaah = 1;
					next_state = STATE_FALL;
				end else if (bump_right) begin
					next_state = STATE_WALK_RIGHT;
				end else if (dig) begin
					digging = 1;
					next_state = STATE_DIG;
				end
			end

			STATE_WALK_RIGHT: begin
				walk_right = 1;
				if (!ground) begin
					aaah = 1;
					next_state = STATE_FALL;
				end else if (bump_left) begin
					next_state = STATE_WALK_LEFT;
				end else if (dig) begin
					digging = 1;
					next_state = STATE_DIG;
				end
			end

			STATE_FALL: begin
				aaah = 1;
				if (ground) begin
					if (walk_left) next_state = STATE_WALK_LEFT;
					else if (walk_right) next_state = STATE_WALK_RIGHT;
				end
			end

			STATE_DIG: begin
				digging = 1;
				if (!ground) begin
					aaah = 1;
					next_state = STATE_FALL;
				end else if (ground && (bump_left || bump_right)) begin
					next_state = STATE_DIG; // Stay in DIG if bumped
				end
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIG
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= STATE_WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state, bump_left, bump_right, ground, dig) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;
        next_state = current_state;

        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = STATE_DIG;
                    digging = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (dig) begin
                    next_state = STATE_DIG;
                    digging = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_FALL: begin
                aaah = 1;
                if (ground) begin
                    if (current_state == STATE_WALK_LEFT) begin
                        next_state = STATE_WALK_LEFT;
                    end else begin
                        next_state = STATE_WALK_RIGHT;
                    end
                end
            end

            STATE_DIG: begin
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (!dig) begin
                    next_state = (walk_left) ? STATE_WALK_LEFT : STATE_WALK_RIGHT;
                end
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

typedef enum logic [1:0] {
    WALK_LEFT,
    WALK_RIGHT,
    FALLING,
    DIGGING
} state_t;

state_t current_state, next_state;

always_ff @(posedge clk or posedge areset) begin
    if (areset)
        current_state <= WALK_LEFT;
    else
        current_state <= next_state;
end

always_comb begin
    next_state = current_state;
    walk_left = 0;
    walk_right = 0;
    aaah = 0;
    digging = 0;

    case (current_state)
        WALK_LEFT: begin
            walk_left = 1;
            if (!ground) begin
                next_state = FALLING;
                aaah = 1;
            end else if (bump_right) begin
                next_state = WALK_RIGHT;
            end else if (dig) begin
                next_state = DIGGING;
            end
        end

        WALK_RIGHT: begin
            walk_right = 1;
            if (!ground) begin
                next_state = FALLING;
                aaah = 1;
            end else if (bump_left) begin
                next_state = WALK_LEFT;
            end else if (dig) begin
                next_state = DIGGING;
            end
        end

        FALLING: begin
            aaah = 1;
            if (ground) begin
                if (walk_left)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end
        end

        DIGGING: begin
            digging = 1;
            if (!ground) begin
                next_state = FALLING;
                aaah = 1;
            end else if (bump_left || bump_right) begin
                next_state = DIGGING;
            end
        end

    endcase
end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum logic [2:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL,
        STATE_DIGGING,
        STATE_WAIT
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= STATE_WALK_LEFT;
        else
            current_state <= next_state;
    end

    always_ff @(current_state, bump_left, bump_right, ground, dig) begin
        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;
                digging = 0;
                if (!ground) begin
                    next_state = STATE_FALL;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else if (dig) begin
                    next_state = STATE_DIGGING;
                end else begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                aaah = 0;
                digging = 0;
                if (!ground) begin
                    next_state = STATE_FALL;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else if (dig) begin
                    next_state = STATE_DIGGING;
                end else begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_FALL: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1;
                digging = 0;
                if (ground) begin
                    if (current_state == STATE_FALL) begin
                        if (walk_left)
                            next_state = STATE_WALK_LEFT;
                        else
                            next_state = STATE_WALK_RIGHT;
                    end else
                        next_state = STATE_WALK_LEFT; // Default direction after falling starts
                end else begin
                    next_state = STATE_FALL;
                end
            end

            STATE_DIGGING: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 0;
                digging = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                end else if (ground && !dig) begin
                    next_state = STATE_WALK_LEFT; // Default direction after digging ends
                end else begin
                    next_state = STATE_DIGGING;
                end
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum reg [2:0] {
        ST_WALK_LEFT,
        ST_WALK_RIGHT,
        ST_FALL,
        ST_DIG
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= ST_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        // Default outputs
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        digging = 0;

        case (state)
            ST_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    aaah = 1; // Start falling
                    next_state = ST_FALL;
                end else if (dig) begin
                    digging = 1; // Start digging
                    next_state = ST_DIG;
                end else if (bump_right) begin
                    next_state = ST_WALK_RIGHT; // Switch direction
                end else if (bump_left) begin
                    next_state = ST_WALK_LEFT; // Remain in state
                end else begin
                    next_state = ST_WALK_LEFT; // Remain in state
                end
            end

            ST_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    aaah = 1; // Start falling
                    next_state = ST_FALL;
                end else if (dig) begin
                    digging = 1; // Start digging
                    next_state = ST_DIG;
                end else if (bump_left) begin
                    next_state = ST_WALK_LEFT; // Switch direction
                end else if (bump_right) begin
                    next_state = ST_WALK_RIGHT; // Remain in state
                end else begin
                    next_state = ST_WALK_RIGHT; // Remain in state
                end
            end

            ST_FALL: begin
                aaah = 1; // Indicating falling
                if (ground) begin
                    next_state = (walk_left) ? ST_WALK_LEFT : ST_WALK_RIGHT; // Resume walking
                end else begin
                    next_state = ST_FALL; // Continue falling
                end
            end

            ST_DIG: begin
                digging = 1; // Indicating digging
                if (!ground) begin
                    aaah = 1; // Start falling
                    next_state = ST_FALL;
                end else begin
                    next_state = ST_DIG; // Continue digging
                end
            end

            default: begin
                next_state = ST_WALK_LEFT; // Default state
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output reg walk_left,
	output reg walk_right,
	output reg aaah,
	output reg digging
);

	typedef enum reg [1:0] {
		WALK_LEFT = 2'b00,
		WALK_RIGHT = 2'b01,
		FALLING = 2'b10,
		DIGGING = 2'b11
	} state_t;

	state_t state, next_state;

	always @(posedge clk or posedge areset) begin
		if (areset)
			state <= WALK_LEFT;
		else
			state <= next_state;
	end

	always @* begin
		aaah = 0;
		digging = 0;
		walk_left = 0;
		walk_right = 0;
		next_state = state;

		case (state)
			WALK_LEFT: begin
				if (!ground) begin
					aaah = 1;
					next_state = FALLING;
				end else if (dig) begin
					next_state = DIGGING;
					digging = 1;
				end else if (bump_right) begin
					next_state = WALK_RIGHT;
				end else begin
					walk_left = 1;
				end
			end

			WALK_RIGHT: begin
				if (!ground) begin
					aaah = 1;
					next_state = FALLING;
				end else if (dig) begin
					next_state = DIGGING;
					digging = 1;
				end else if (bump_left) begin
					next_state = WALK_LEFT;
				end else begin
					walk_right = 1;
				end
			end

			FALLING: begin
				if (ground) begin
					next_state = (bump_left) ? WALK_RIGHT : (bump_right) ? WALK_LEFT : (state == WALK_LEFT) ? WALK_LEFT : WALK_RIGHT;
				end else begin
					aaah = 1;
				end
			end

			DIGGING: begin
				if (!ground) begin
					next_state = FALLING;
					aaah = 1;
				end else begin
					digging = 1;
					walk_left = (bump_left) ? 0 : 1;
					walk_right = (bump_right) ? 0 : 1;
				end
			end
		endcase
	end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output reg walk_left,
    output reg walk_right,
    output reg aaah,
    output reg digging
);

    typedef enum bit [1:0] {WALK_LEFT, WALK_RIGHT, FALLING, DIGGING} state_t;
    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= WALK_LEFT;
        else
            current_state <= next_state;
    end

    always_ff @(posedge clk) begin
        aaah <= (current_state == FALLING);
        digging <= (current_state == DIGGING);
    end

    always_comb begin
        next_state = current_state;
        walk_left = 0;
        walk_right = 0;

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALLING;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else if (dig) begin
                    next_state = DIGGING;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALLING;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else if (dig) begin
                    next_state = DIGGING;
                end
            end

            FALLING: begin
                if (ground) begin
                    if (current_state == FALLING) begin
                        if (walk_left) next_state = WALK_LEFT;
                        else if (walk_right) next_state = WALK_RIGHT;
                    end
                end
            end

            DIGGING: begin
                if (!ground) begin
                    next_state = FALLING;
                end
            end
        endcase
    end
endmodule


module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b0001_0010; // 12:00 AM in BCD
            mm <= 8'b0000_0000; // 00 minutes
            ss <= 8'b0000_0000; // 00 seconds
            pm <= 1'b0;         // AM
        end else if (ena) begin
            if (ss == 8'b0101_1001) begin // 59 seconds
                ss <= 8'b0000_0000; // reset seconds
                if (mm == 8'b0101_1001) begin // 59 minutes
                    mm <= 8'b0000_0000; // reset minutes
                    if (hh == 8'b0001_0010) begin // 12 hours
                        hh <= 8'b0001_0001; // reset to 1 hour
                        pm <= ~pm; // toggle AM/PM
                    end else if (hh == 8'b0001_0001) begin // 1 hour
                        hh <= 8'b0001_0010; // set to 2 hours
                    end else if (hh == 8'b0001_0010) begin // 2 hours
                        hh <= 8'b0001_0011; // set to 3 hours
                    end else if (hh == 8'b0001_0011) begin // 3 hours
                        hh <= 8'b0001_0100; // set to 4 hours
                    end else if (hh == 8'b0001_0100) begin // 4 hours
                        hh <= 8'b0001_0101; // set to 5 hours
                    end else if (hh == 8'b0001_0101) begin // 5 hours
                        hh <= 8'b0001_0110; // set to 6 hours
                    end else if (hh == 8'b0001_0110) begin // 6 hours
                        hh <= 8'b0001_0111; // set to 7 hours
                    end else if (hh == 8'b0001_0111) begin // 7 hours
                        hh <= 8'b0001_1000; // set to 8 hours
                    end else if (hh == 8'b0001_1000) begin // 8 hours
                        hh <= 8'b0001_1001; // set to 9 hours
                    end else if (hh == 8'b0001_1001) begin // 9 hours
                        hh <= 8'b0001_1010; // set to 10 hours
                    end else if (hh == 8'b0001_1010) begin // 10 hours
                        hh <= 8'b0001_1011; // set to 11 hours
                    end else if (hh == 8'b0001_1011) begin // 11 hours
                        hh <= 8'b0001_1100; // set to 12 hours
                    end
                end else begin
                    mm <= mm + 1; // increment minutes
                end
            end else begin
                ss <= ss + 1; // increment seconds
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    // Initialize the clock
    initial begin
        hh = 8'b00001100; // Initial hour: 12
        mm = 8'b00000000; // Initial minutes: 00
        ss = 8'b00000000; // Initial seconds: 00
        pm = 1'b0;        // Initial state: AM
    end

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00001100; // Reset to 12
            mm <= 8'b00000000; // Reset to 00
            ss <= 8'b00000000; // Reset to 00
            pm <= 1'b0;        // Reset to AM
        end else if (ena) begin
            // Increment seconds
            if (ss == 8'b00111001) begin // 59 in decimal
                ss <= 8'b00000000; // Reset seconds
                // Increment minutes
                if (mm == 8'b00111001) begin // 59 in decimal
                    mm <= 8'b00000000; // Reset minutes
                    // Increment hours
                    if (hh == 8'b00001100) begin // 12 in decimal
                        hh <= 8'b00000001; // Set to 1
                        pm <= ~pm; // Toggle AM/PM
                    end else if (hh == 8'b00000001 && pm == 1'b1) begin // Transition from 1 PM to 2 PM
                        hh <= 8'b00000010; // Set to 2
                    end else if (hh < 8'b00001100) begin
                        hh <= hh + 1; // Increment hour
                    end
                end else begin
                    mm <= mm + 1; // Increment minutes
                end
            end else begin
                ss <= ss + 1; // Increment seconds
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd12;
            mm <= 8'd0;
            ss <= 8'd0;
            pm <= 0;
        end else if (ena) begin
            if (ss < 59) begin
                ss <= ss + 1;
            end else begin
                ss <= 0;
                if (mm < 59) begin
                    mm <= mm + 1;
                end else begin
                    mm <= 0;
                    if (hh < 12) begin
                        hh <= hh + 1;
                    end else begin
                        hh <= 1;
                        pm <= ~pm;
                    end
                end
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	reg [3:0] ss_tens, ss_ones, mm_tens, mm_ones, hh_tens, hh_ones;
	reg [3:0] next_ss_ones, next_mm_ones, next_hh_ones;
	reg next_pm;

	always @(posedge clk) begin
		if (reset) begin
			ss <= 8'b00000000; // 00
			mm <= 8'b00000000; // 00
			hh <= 8'b00001100; // 12
			pm <= 1'b0;        // AM
		end else if (ena) begin
			if (ss == 8'b01011000) begin // 59
				ss <= 8'b00000000; // reset seconds to 00
				if (mm == 8'b00111001) begin // 59
					mm <= 8'b00000000; // reset minutes to 00
					if (hh == 8'b00110000) begin // 12
						hh <= 8'b00000001; // reset hours to 01
						pm <= ~pm; // toggle AM/PM
					end else begin
						hh <= hh + 1;
					end
				end else begin
					mm <= mm + 1;
				end
			end else begin
				ss <= ss + 1;
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    // State for seconds, minutes, and hours
    reg [5:0] count_seconds = 0; // 0-59
    reg [5:0] count_minutes = 0; // 0-59
    reg [3:0] count_hours = 0;   // 1-12

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd12; // Reset hours to 12
            mm <= 8'd0;  // Reset minutes to 0
            ss <= 8'd0;  // Reset seconds to 0
            pm <= 0;     // Reset PM indicator to AM
            count_seconds <= 0;
            count_minutes <= 0;
            count_hours <= 0;
        end else if (ena) begin
            if (count_seconds == 59) begin
                count_seconds <= 0;
                ss <= 8'd0;
                if (count_minutes == 59) begin
                    count_minutes <= 0;
                    mm <= 8'd0;
                    if (count_hours == 11) begin
                        count_hours <= 0;
                        hh <= (hh == 8'd12) ? 8'd1 : hh + 1; // Toggle AM/PM
                        pm <= ~pm; // Toggle PM
                    end else begin
                        count_hours <= count_hours + 1;
                        hh <= (count_hours == 11) ? 8'd12 : hh + 1;
                    end
                end else begin
                    count_minutes <= count_minutes + 1;
                    mm <= mm + 1;
                end
            end else begin
                count_seconds <= count_seconds + 1;
                ss <= ss + 1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010000; // Reset to 12 (BCD)
            mm <= 8'b00000000; // Reset minutes to 00
            ss <= 8'b00000000; // Reset seconds to 00
            pm <= 1'b0;        // Reset to AM
        end else if (ena) begin
            if (ss == 8'b00111001) begin // 59 in BCD
                ss <= 8'b00000000; // Reset seconds to 0
                if (mm == 8'b01011000) begin // 59 in BCD
                    mm <= 8'b00000000; // Reset minutes to 0
                    if (hh == 8'b00010000) begin // 12 in BCD
                        hh <= 8'b00000001; // Reset hours to 01 (next hour)
                        pm <= ~pm; // Toggle PM/AM
                    end else begin
                        hh <= hh + 8'b00000001; // Increment hour
                    end
                end else begin
                    mm <= mm + 8'b00000001; // Increment minutes
                end
            end else begin
                ss <= ss + 8'b00000001; // Increment seconds
            end
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'd12;
			mm <= 8'd0;
			ss <= 8'd0;
			pm <= 0; // start with AM
		end else if (ena) begin
			if (ss == 8'd59) begin
				ss <= 8'd0;
				if (mm == 8'd59) begin
					mm <= 8'd0;
					if (hh == 8'd12) begin
						hh <= 8'd1; // wrap around 12 to 1
						pm <= ~pm; // toggle AM/PM
					end else begin
						hh <= hh + 1;
					end
				end else begin
					mm <= mm + 1;
				end
			end else begin
				ss <= ss + 1;
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010000; // 12 in BCD
            mm <= 8'b00000000; // 00 in BCD
            ss <= 8'b00000000; // 00 in BCD
            pm <= 0;           // AM
        end else if (ena) begin
            if (ss == 59) begin
                ss <= 0;
                if (mm == 59) begin
                    mm <= 0;
                    if (hh == 8'b00011000) begin // 12 in BCD
                        hh <= 8'b00010000; // Set to 12 BCD
                        pm <= ~pm;       // Toggle AM/PM
                    end else begin
                        hh <= hh + 1;   // Increment hour
                    end
                end else begin
                    mm <= mm + 1; // Increment minute
                end
            end else begin
                ss <= ss + 1; // Increment second
            end
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'b00010000; // 12 in BCD
			mm <= 8'b00000000; // 00 in BCD
			ss <= 8'b00000000; // 00 in BCD
			pm <= 1'b0; // AM
		end else if (ena) begin
			if (ss == 8'b00111001) begin // 59 in BCD
				ss <= 8'b00000000; // Reset seconds to 00
				if (mm == 8'b01011000) begin // 59 in BCD
					mm <= 8'b00000000; // Reset minutes to 00
					if (hh == 8'b00010000) begin // 12 in BCD
						hh <= 8'b00000001; // Reset hours to 01
						pm <= ~pm; // Toggle AM/PM
					end else begin
						hh <= hh + 1; // Increment hours
					end
				end else begin
					mm <= mm + 1; // Increment minutes
				end
			end else begin
				ss <= ss + 1; // Increment seconds
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

always @(posedge clk) begin
    if (reset) begin
        hh <= 8'd12;   // Reset hours to 12
        mm <= 8'd0;    // Reset minutes to 0
        ss <= 8'd0;    // Reset seconds to 0
        pm <= 1'b0;    // Reset PM indicator to AM
    end else if (ena) begin
        // Increment seconds
        if (ss < 59) begin
            ss <= ss + 1;
        end else begin
            ss <= 0;
            // Increment minutes
            if (mm < 59) begin
                mm <= mm + 1;
            end else begin
                mm <= 0;
                // Increment hours
                if (hh < 12) begin
                    hh <= hh + 1;
                end else begin
                    hh <= 1; // Reset hours to 1 after 12
                    pm <= ~pm; // Toggle PM/AM
                end
            end
        end
    end
end

endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    reg [5:0] sec_counter;
    reg [5:0] min_counter;

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd1; // Start from 01
            mm <= 8'd0; // Start from 00
            ss <= 8'd0; // Start from 00
            pm <= 1'b0; // Start as AM
            sec_counter <= 6'd0;
            min_counter <= 6'd0;
        end else if (ena) begin
            if (sec_counter == 6'd59) begin
                sec_counter <= 6'd0;
                if (min_counter == 6'd59) begin
                    min_counter <= 6'd0;
                    if (hh == 8'd12) begin
                        pm <= ~pm; // Toggle AM/PM
                    end
                    hh <= (hh == 8'd12) ? 8'd1 : hh + 1; // 1-12 hours
                end else begin
                    min_counter <= min_counter + 1;
                end
            end else begin
                sec_counter <= sec_counter + 1;
            end

            ss <= sec_counter; // Update seconds output
            mm <= min_counter; // Update minutes output
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010000; // 12 in BCD
            mm <= 8'b00000000; // 00 in BCD
            ss <= 8'b00000000; // 00 in BCD
            pm <= 0;           // AM
        end else if (ena) begin
            if (ss == 8'b00111001) begin // 59 in BCD
                ss <= 8'b00000000;      // Reset seconds to 00
                if (mm == 8'b01011000) begin // 59 in BCD
                    mm <= 8'b00000000;      // Reset minutes to 00
                    if (hh == 8'b00010100) begin // 12 in BCD
                        hh <= 8'b00010000;     // Reset hours to 12
                        pm <= ~pm;            // Toggle AM/PM
                    end else begin
                        hh <= hh + 1;         // Increment hour
                    end
                end else begin
                    mm <= mm + 1;             // Increment minute
                end
            end else begin
                ss <= ss + 1;                 // Increment second
            end
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	// State for clock: hours, minutes, seconds
	// BCD: 00-59 for minutes and seconds, 01-12 for hours
	initial begin
		hh = 8'b00000000; // Initialize to 12:00 AM
		mm = 8'b00000000;
		ss = 8'b00000000;
		pm = 0; // Start with AM
	end

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'b00000000; // Reset hours to 00
			mm <= 8'b00000000; // Reset minutes to 00
			ss <= 8'b00000000; // Reset seconds to 00
			pm <= 0; // Reset to AM
		end else if (ena) begin
			if (ss == 8'b00111001) begin // 59 seconds
				ss <= 8'b00000000; // Reset seconds to 00
				if (mm == 8'b00111001) begin // 59 minutes
					mm <= 8'b00000000; // Reset minutes to 00
					if (hh == 8'b00001100) begin // 12 hours
						hh <= 8'b00000001; // Set to 01
						pm <= ~pm; // Toggle AM/PM
					end else if (hh == 8'b00000001 && pm) begin // If we are on 1 PM, go to 2 PM
						hh <= 8'b00000010; // Increment hours
					end else if (hh < 8'b00001101) begin // for hours less than 12
						hh <= hh + 1; // Increment hours
					end else begin
						hh <= 8'b00001100; // If hours are more than 12, reset to 12
					end
				end else begin
					mm <= mm + 1; // Increment minutes
				end
			end else begin
				ss <= ss + 1; // Increment seconds
			end
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'b00010000; // Start at 12:00 (in BCD)
			mm <= 8'b00000000; // 00 minutes
			ss <= 8'b00000000; // 00 seconds
			pm <= 1'b0; // AM state
		end else if (ena) begin
			if (ss == 8'b00111001) begin // 59 seconds
				ss <= 8'b00000000; // Reset seconds
				if (mm == 8'b00111001) begin // 59 minutes
					mm <= 8'b00000000; // Reset minutes
					if (hh == 8'b00010000) begin // 12 hours
						hh <= 8'b00000001; // Set to 01
						pm <= ~pm; // Toggle AM/PM
					end else begin
						hh <= hh + 1; // Increment hour
					end
				end else begin
					mm <= mm + 1; // Increment minutes
				end
			end else begin
				ss <= ss + 1; // Increment seconds
			end
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'b00010000; // 12 in BCD
			mm <= 8'b00000000; // 00 in BCD
			ss <= 8'b00000000; // 00 in BCD
			pm <= 0; // AM
		end else if (ena) begin
			ss <= ss + 1;
			if (ss == 8'b00111001) begin // 59 in BCD
				ss <= 8'b00000000;
				mm <= mm + 1;
				if (mm == 8'b00111001) begin // 59 in BCD
					mm <= 8'b00000000;
					hh <= hh + 1;
					if (hh == 8'b00010000) begin // 12 in BCD
						hh <= 8'b00000001; // 01 in BCD
						pm <= ~pm; // toggle AM/PM
					end else if (hh == 8'b00000001 && pm == 1) begin
						hh <= 8'b00010000; // 12 in BCD
					end
				end
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd1;    // Reset hour to 01
            mm <= 8'd0;    // Reset minutes to 00
            ss <= 8'd0;    // Reset seconds to 00
            pm <= 1'b0;    // Reset PM indicator to AM
        end else if (ena) begin
            if (ss == 8'd59) begin
                ss <= 8'd0;
                if (mm == 8'd59) begin
                    mm <= 8'd0;
                    if (hh == 8'd12) begin
                        hh <= 8'd1;
                        pm <= ~pm; // Toggle PM/AM
                    end else begin
                        hh <= hh + 8'd1;
                    end
                end else begin
                    mm <= mm + 8'd1;
                end
            end else begin
                ss <= ss + 8'd1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00001100; // 12 in BCD
            mm <= 8'b00000000; // 00 in BCD
            ss <= 8'b00000000; // 00 in BCD
            pm <= 0;           // AM
        end else if (ena) begin
            ss <= ss + 1;
            if (ss == 59) begin
                ss <= 0;
                mm <= mm + 1;
                if (mm == 59) begin
                    mm <= 0;
                    hh <= hh + 1;
                    if (hh == 12) begin
                        pm <= ~pm; // Toggle AM/PM
                    end
                    if (hh == 13) begin
                        hh <= 1; // Reset hour to 01 after 12
                    end
                end
            end
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

	reg [5:0] seconds_count;
	reg [5:0] minutes_count;
	reg [3:0] hours_count;

	always @(posedge clk) begin
		if (reset) begin
			hh <= 8'd12;
			mm <= 8'd0;
			ss <= 8'd0;
			seconds_count <= 6'd0;
			minutes_count <= 6'd0;
			hours_count <= 4'd0;
			pm <= 1'b0;
		end else if (ena) begin
			if (seconds_count == 6'd59) begin
				seconds_count <= 6'd0;
				ss <= ss + 8'd1;

				if (minutes_count == 6'd59) begin
					minutes_count <= 6'd0;
					mm <= mm + 8'd1;

					if (hh == 8'd12) begin
						hh <= 8'd1;
						pm <= ~pm; // Toggle AM/PM
					end else begin
						hh <= hh + 8'd1;
					end
				end else begin
					minutes_count <= minutes_count + 6'd1;
				end
			end else begin
				seconds_count <= seconds_count + 6'd1;
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
);

    // BCD counters for seconds and minutes
    reg [5:0] sec_counter; // 0-59
    reg [5:0] min_counter; // 0-59

    // Main clock process
    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'b00010000;  // Reset to 12:00 AM (12 in BCD)
            mm <= 8'b00000000;  // Reset minutes to 0
            ss <= 8'b00000000;  // Reset seconds to 0
            pm <= 0;            // Reset to AM
            sec_counter <= 0;
            min_counter <= 0;
        end else if (ena) begin
            if (sec_counter == 59) begin
                sec_counter <= 0;
                ss <= (ss == 59) ? 0 : ss + 1;
                if (ss == 59) begin
                    if (min_counter == 59) begin
                        min_counter <= 0;
                        mm <= 0;
                        hh <= (hh == 8'b00010000) ? 8'b00000001 : hh + 1; // 12 to 1
                        pm <= ~pm; // Toggle AM/PM
                    end else begin
                        min_counter <= min_counter + 1;
                        mm <= (mm == 59) ? 0 : mm + 1;
                    end
                end
            end else begin
                sec_counter <= sec_counter + 1;
                ss <= (ss == 59) ? 0 : ss + 1;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss
);
    always @(posedge clk) begin
        if (reset) begin
            hh <= 8'd12;  // Reset hours to 12
            mm <= 8'd0;   // Reset minutes to 0
            ss <= 8'd0;   // Reset seconds to 0
            pm <= 1'b0;   // Reset PM indicator to AM
        end else if (ena) begin
            if (ss < 8'd59) begin
                ss <= ss + 1;  // Increment seconds
            end else begin
                ss <= 8'd0;  // Reset seconds
                if (mm < 8'd59) begin
                    mm <= mm + 1;  // Increment minutes
                end else begin
                    mm <= 8'd0;  // Reset minutes
                    if (hh < 8'd12) begin
                        hh <= hh + 1;  // Increment hours
                    end else begin
                        hh <= 8'd1;  // Reset hours after 12
                        pm <= ~pm;   // Toggle PM/AM
                    end
                end
            end
        end
    end
endmodule