module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'd1;
		end else if (q < 4'd10) begin
			q <= q + 1;
		end else begin
			q <= 4'd1;
		end
	end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0001; // Reset to 1
		end else if (q < 4'b1010) begin
			q <= q + 1; // Count from 1 to 10
		end else begin
			q <= 4'b0001; // Reset to 1 after reaching 10
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0001; // Reset to 1
	end else if (q < 4'b1010) begin
		q <= q + 1; // Count up to 10
	end else begin
		q <= 4'b0001; // Reset to 1 after reaching 10
	end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset)
			q <= 4'b0001; // Reset to 1
		else if (q < 4'b1010)
			q <= q + 1; // Count up to 10
	end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0001; // Reset to 1
		end else if (q < 4'b1010) begin
			q <= q + 1; // Increment counter
		end else begin
			q <= 4'b0001; // Reset to 1 after reaching 10
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0001; // Reset to 1
	end else if (q < 4'b1010) begin
		q <= q + 1; // Count from 1 to 10
	end else begin
		q <= 4'b0001; // Reset back to 1 after reaching 10
	end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0001; // Reset the counter to 1
	end else if (q < 4'b1010) begin
		q <= q + 1; // Increment the counter
	end else begin
		q <= 4'b0001; // Reset back to 1 after reaching 10
	end
end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'd1;
        end else begin
            if (q < 4'd10) begin
                q <= q + 1;
            end else begin
                q <= 4'd1;
            end
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0001;
	end else if (q < 4'b1010) begin
		q <= q + 1;
	end else begin
		q <= 4'b0001;
	end
end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

always @(posedge clk) begin
    if (reset) begin
        q <= 4'b0001; // Reset counter to 1
    end else if (q < 4'b1010) begin
        q <= q + 1; // Count up to 10
    end else begin
        q <= 4'b0001; // Reset to 1 after reaching 10
    end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 4'b0001; // Reset counter to 1
		end else begin
			if (q < 4'b1010) begin
				q <= q + 1; // Count from 1 to 10
			end else begin
				q <= 4'b0001; // Roll over to 1 after reaching 10
			end
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset counter to 1
        end else if (q == 4'b1010) begin
            q <= 4'b0001; // Wrap around to 1 after counting to 10
        end else begin
            q <= q + 1; // Increment counter
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset to 1
        end else begin
            if (q < 4'b1010) begin // Count from 1 to 10
                q <= q + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // reset to 1
        end else begin
            if (q < 4'b1010) begin
                q <= q + 1; // count up to 10
            end else begin
                q <= 4'b0001; // reset to 1 after reaching 10
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0001; // Reset to 1
        end else if (q < 4'b1010) begin // Count from 1 to 10
            q <= q + 1;
        end else begin
            q <= 4'b0001; // Reset to 1 after reaching 10
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0001;
		end else if (q == 4'b1010) begin
			q <= 4'b0001;
		end else begin
			q <= q + 1;
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0001; // Reset the counter to 1
	end else if (q < 4'b1010) begin
		q <= q + 1; // Count from 1 to 10
	end else begin
		q <= 4'b0001; // Reset to 1 after counting to 10
	end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset)
			q <= 4'b0001; // Reset to 1
		else if (q < 4'b1010)
			q <= q + 1; // Count up
		else
			q <= 4'b0001; // Reset to 1 after counting to 10
	end
endmodule


module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

	always @(posedge clk) begin
		if (a) begin
			if (q == 3'd4)
				q <= 3'd4;
			else
				q <= q + 1;
		end else begin
			if (q != 3'd0)
				q <= q - 1;
		end
	end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'd0)
                q <= 3'd4;
            else if (q == 3'd1)
                q <= 3'd0;
            else
                q <= q + 1'b1;
        end
    end

    initial begin
        q = 3'd0;
    end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

	always @(posedge clk) begin
		if (a) begin
			if (q == 3'b111)
				q <= 3'b000;
			else
				q <= q + 1;
		end
	end

	always @(negedge clk) begin
		if (!a)
			q <= q;
	end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b100) begin
                q <= 3'b100;
            end else begin
                q <= q + 1;
            end
        end else begin
            if (q > 0) begin
                q <= q - 1;
            end
        end
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            q <= q + 1;
        end else begin
            q <= 0;
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            if (q == 3'd4) begin
                q <= 3'd4;
            end else if (q == 3'd5) begin
                q <= 3'd6;
            end else if (q == 3'd6) begin
                q <= 3'd0;
            end else begin
                q <= q + 1;
            end
        end else begin
            q <= q;
        end
    end
endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

	always @(posedge clk) begin
		if (a) begin
			if (q == 3'b111)
				q <= 3'b000; // wrap around if maximum value reached
			else
				q <= q + 1; // increment q
		end
	end

	always @(negedge clk) begin
		if (!a)
			q <= q; // hold value on the negative edge if a is 0
	end

endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

	always @(posedge clk) begin
		if (a) begin
			if (q == 3'b111)
				q <= 3'b000;
			else
				q <= q + 1;
		end else begin
			q <= q;
		end
	end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b111)
                q <= 3'b000;
            else
                q <= q + 1;
        end
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b111) q <= 3'b000; // Reset to 0 if the counter reaches 7
            else q <= q + 1; // Increment the counter
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            if (q == 3'd5)
                q <= 3'd6;
            else if (q == 3'd6)
                q <= 3'd0;
            else
                q <= q + 3'd1;
        end
    end

    always @(negedge clk) begin
        if (!a)
            q <= q; // Hold value on negative clock edge when a is low
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a == 1) begin
            if (q < 6)
                q <= q + 1;
            else
                q <= 0;
        end else begin
            q <= q;
        end
    end

    initial begin
        q = 3'b000; // Initial value for q
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b111)
                q <= 3'b000; // Wrap around if q reaches 7
            else
                q <= q + 1; // Increment q
        end else begin
            q <= q; // Hold q value if a is 0
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 4)
                q <= 4;
            else if (q == 5)
                q <= 6;
            else if (q == 6)
                q <= 0;
            else
                q <= q + 1;
        end else begin
            q <= q;
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b100)
                q <= 3'b101; // Increment when q is 4
            else
                q <= q + 1;  // Increment otherwise
        end
    end

    always @(negedge clk) begin
        if (!a) begin
            q <= 3'b000; // Reset q to 0 when a is 0
        end
    end
endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);

    always @(posedge clk) begin
        if (a) begin
            if (q == 3'd7)
                q <= 3'd0;
            else
                q <= q + 3'd1;
        end else begin
            q <= q;
        end
    end

endmodule

module top_module (
    input clk,
    input a,
    output reg [2:0] q
);
    always @(posedge clk) begin
        if (a) begin
            if (q == 3'b100)
                q <= 3'b101; // Transition from 4 to 5
            else if (q == 3'b101)
                q <= 3'b110; // Transition from 5 to 6
            else if (q == 3'b110)
                q <= 3'b000; // Transition from 6 to 0
            else
                q <= q + 1;   // Increment otherwise
        end
    end

    initial begin
        q = 3'b000; // Initialize q to 0
    end
endmodule

module top_module (
	input clk,
	input a,
	output reg [2:0] q
);

	always @(posedge clk) begin
		if (a) begin
			if (q == 4)
				q <= 4;
			else
				q <= q + 1;
		end else begin
			if (q == 0)
				q <= 0;
			else if (q == 5)
				q <= 6;
			else if (q == 6)
				q <= 0;
			else
				q <= q - 1;
		end
	end

	initial begin
		q = 3'b000; // Initialize q
	end

endmodule


module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001; // Reset to 1
		end else begin
			q <= {q[3:0], q[4] ^ q[2]}; // Shift and XOR for taps at positions 5 and 3
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q[4] <= q[3]; // Shift left
            q[3] <= q[2];
            q[2] <= q[1];
            q[1] <= q[0] ^ q[4]; // Tap at position 5
            q[0] <= q[0] ^ q[2]; // Tap at position 3
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3] ^ q[4], q[4:1]}; // Galois LFSR feedback
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001; // Reset to 1
		end else begin
			// Galois LFSR with taps at positions 5 and 3
			q[4] <= q[3] ^ q[4]; // tap positions 5 and 3
			q[3] <= q[2];
			q[2] <= q[1];
			q[1] <= q[0];
			q[0] <= 1'b0; // Shift in zero
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3], q[2], q[1], q[0], q[4] ^ q[2]}; // Galois LFSR with taps at bit positions 5 and 3
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001;  // Reset to 1
		end else begin
			// Galois LFSR with taps at position 5 and 3
			q <= {q[3:0], q[4] ^ q[2]};
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001; // Reset to 1
		end else begin
			q <= {q[3:0], q[4] ^ q[2]}; // Shift and tap feedback
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001;  // Reset to 1
		end else begin
			q <= {q[3:0], (q[4] ^ q[2])};  // Shift and XOR tap bits at positions 5 and 3
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            // Galois LFSR with taps at positions 5 and 3
            q <= {q[3] ^ q[4], q[4:1]};
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3] ^ q[4], q[4:1]}; // Galois LFSR with taps at 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3:0], (q[4] ^ q[2])}; // Shift and XOR for taps at positions 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001;  // Reset LFSR to 1
        end else begin
            q <= {q[3] ^ q[4], q[4:1]};  // Galois LFSR with taps at positions 5 and 3
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001;
        end else begin
            q <= {q[3]^q[4], q[4], q[3], q[2], q[1]}; // XORing taps at position 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3:0], q[4] ^ q[2]}; // Shift and XOR for taps at positions 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // reset to 1
        end else begin
            q <= {q[3] ^ q[4], q[4:1]}; // LFSR logic with taps at 5 and 3
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            // Galois LFSR with taps at positions 5 and 3
            q <= {q[3] ^ q[4], q[4], q[3], q[2], q[1]}; // Shift and XOR for next state
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3] ^ q[4], q[4:1]}; // Shift and XOR feedback from taps 5 and 3
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q
);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 5'b00001; // Reset to 1
        end else begin
            q <= {q[3:0], q[4] ^ q[2]}; // Shift and feedback using taps at positions 5 and 3
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 5'b00001; // Reset output to 1
		end else begin
			q <= {q[3:0], q[4] ^ q[2]}; // Shift and XOR for Galois LFSR with taps at 5 and 3
		end
	end
endmodule


module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub)
            out = a - b;
        else
            out = a + b;

        result_is_zero = (out == 8'b0); // Fixed condition to check if out is zero
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		if (do_sub)
			out = a - b;
		else
			out = a + b;

		result_is_zero = (out == 8'b0);
	end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub) begin
            out = a - b;
        end else begin
            out = a + b;
        end

        result_is_zero = (out == 8'b0);
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		if (do_sub)
			out = a - b;
		else
			out = a + b;

		result_is_zero = (out == 8'b0) ? 1'b1 : 1'b0;
	end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		if (do_sub == 1'b0)
			out = a + b;
		else
			out = a - b;

		result_is_zero = (out == 8'b0) ? 1'b1 : 1'b0;
	end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub)
            out = a - b;
        else
            out = a + b;

        result_is_zero = (out == 8'b00000000);
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub) begin
            out = a - b;
        end else begin
            out = a + b;
        end

        result_is_zero = (out == 8'b00000000);
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		case (do_sub)
			1'b0: out = a + b;
			1'b1: out = a - b;
		endcase

		if (out == 8'b0)
			result_is_zero = 1'b1;
		else
			result_is_zero = 1'b0;
	end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub == 1'b0)
            out = a + b;
        else
            out = a - b;

        result_is_zero = (out == 8'b0);
    end

endmodule

module top_module (
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        if (do_sub)
            out = a - b;
        else
            out = a + b;

        result_is_zero = (out == 8'd0);
    end

endmodule

module top_module (
	input do_sub,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out,
	output reg result_is_zero
);

	always @(*) begin
		if (do_sub == 1'b0)
			out = a + b;
		else
			out = a - b;

		if (out == 8'b0)
			result_is_zero = 1'b1;
		else
			result_is_zero = 1'b0;
	end

endmodule


module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);

always @(*) begin
    case (code)
        8'h45: begin out = 4'd0; valid = 1'b1; end
        8'h16: begin out = 4'd1; valid = 1'b1; end
        8'h1e: begin out = 4'd2; valid = 1'b1; end
        8'h26: begin out = 4'd3; valid = 1'b1; end
        8'h25: begin out = 4'd4; valid = 1'b1; end
        8'h2e: begin out = 4'd5; valid = 1'b1; end
        8'h36: begin out = 4'd6; valid = 1'b1; end
        8'h3d: begin out = 4'd7; valid = 1'b1; end
        8'h3e: begin out = 4'd8; valid = 1'b1; end
        8'h46: begin out = 4'd9; valid = 1'b1; end
        default: begin out = 4'd0; valid = 1'b0; end
    endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
	valid = 0;
	out = 4'b0000;

	case (code)
		8'h45: begin out = 4'b0000; valid = 1; end // '0'
		8'h16: begin out = 4'b0001; valid = 1; end // '1'
		8'h1e: begin out = 4'b0010; valid = 1; end // '2'
		8'h26: begin out = 4'b0011; valid = 1; end // '3'
		8'h25: begin out = 4'b0100; valid = 1; end // '4'
		8'h2e: begin out = 4'b0101; valid = 1; end // '5'
		8'h36: begin out = 4'b0110; valid = 1; end // '6'
		8'h3d: begin out = 4'b0111; valid = 1; end // '7'
		8'h3e: begin out = 4'b1000; valid = 1; end // '8'
		8'h46: begin out = 4'b1001; valid = 1; end // '9'
		default: begin out = 4'b0000; valid = 0; end
	endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);
	always @(*) begin
		case (code)
			8'h45: begin out = 4'd0; valid = 1; end
			8'h16: begin out = 4'd1; valid = 1; end
			8'h1e: begin out = 4'd2; valid = 1; end
			8'h26: begin out = 4'd3; valid = 1; end
			8'h25: begin out = 4'd4; valid = 1; end
			8'h2e: begin out = 4'd5; valid = 1; end
			8'h36: begin out = 4'd6; valid = 1; end
			8'h3d: begin out = 4'd7; valid = 1; end
			8'h3e: begin out = 4'd8; valid = 1; end
			8'h46: begin out = 4'd9; valid = 1; end
			default: begin out = 4'd0; valid = 0; end
		endcase
	end
endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @* begin
	valid = 0;
	out = 4'b0000;

	case (code)
		8'h45: begin out = 4'b0000; valid = 1; end // Key 0
		8'h16: begin out = 4'b0001; valid = 1; end // Key 1
		8'h1e: begin out = 4'b0010; valid = 1; end // Key 2
		8'h26: begin out = 4'b0011; valid = 1; end // Key 3
		8'h25: begin out = 4'b0100; valid = 1; end // Key 4
		8'h2e: begin out = 4'b0101; valid = 1; end // Key 5
		8'h36: begin out = 4'b0110; valid = 1; end // Key 6
		8'h3d: begin out = 4'b0111; valid = 1; end // Key 7
		8'h3e: begin out = 4'b1000; valid = 1; end // Key 8
		8'h46: begin out = 4'b1001; valid = 1; end // Key 9
		default: begin out = 4'b0000; valid = 0; end // Invalid
	endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
	valid = 0;
	out = 4'b0000;

	case (code)
		8'h45: begin out = 4'b0000; valid = 1; end // 0
		8'h16: begin out = 4'b0001; valid = 1; end // 1
		8'h1e: begin out = 4'b0010; valid = 1; end // 2
		8'h26: begin out = 4'b0011; valid = 1; end // 3
		8'h25: begin out = 4'b0100; valid = 1; end // 4
		8'h2e: begin out = 4'b0101; valid = 1; end // 5
		8'h36: begin out = 4'b0110; valid = 1; end // 6
		8'h3d: begin out = 4'b0111; valid = 1; end // 7
		8'h3e: begin out = 4'b1000; valid = 1; end // 8
		8'h46: begin out = 4'b1001; valid = 1; end // 9
		default: begin out = 4'b0000; valid = 0; end // No valid key
	endcase
end

endmodule

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);

    always @* begin
        case (code)
            8'h45: begin out = 4'd0; valid = 1; end
            8'h16: begin out = 4'd1; valid = 1; end
            8'h1e: begin out = 4'd2; valid = 1; end
            8'h26: begin out = 4'd3; valid = 1; end
            8'h25: begin out = 4'd4; valid = 1; end
            8'h2e: begin out = 4'd5; valid = 1; end
            8'h36: begin out = 4'd6; valid = 1; end
            8'h3d: begin out = 4'd7; valid = 1; end
            8'h3e: begin out = 4'd8; valid = 1; end
            8'h46: begin out = 4'd9; valid = 1; end
            default: begin out = 4'd0; valid = 0; end
        endcase
    end

endmodule

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);

always @(*) begin
    case (code)
        8'h45: begin out = 4'b0000; valid = 1; end // Key 0
        8'h16: begin out = 4'b0001; valid = 1; end // Key 1
        8'h1e: begin out = 4'b0010; valid = 1; end // Key 2
        8'h26: begin out = 4'b0011; valid = 1; end // Key 3
        8'h25: begin out = 4'b0100; valid = 1; end // Key 4
        8'h2e: begin out = 4'b0101; valid = 1; end // Key 5
        8'h36: begin out = 4'b0110; valid = 1; end // Key 6
        8'h3d: begin out = 4'b0111; valid = 1; end // Key 7
        8'h3e: begin out = 4'b1000; valid = 1; end // Key 8
        8'h46: begin out = 4'b1001; valid = 1; end // Key 9
        default: begin out = 4'b0000; valid = 0; end // Invalid
    endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);
	always @* begin
		case (code)
			8'h45: begin out = 4'b0000; valid = 1; end // 0
			8'h16: begin out = 4'b0001; valid = 1; end // 1
			8'h1e: begin out = 4'b0010; valid = 1; end // 2
			8'h26: begin out = 4'b0011; valid = 1; end // 3
			8'h25: begin out = 4'b0100; valid = 1; end // 4
			8'h2e: begin out = 4'b0101; valid = 1; end // 5
			8'h36: begin out = 4'b0110; valid = 1; end // 6
			8'h3d: begin out = 4'b0111; valid = 1; end // 7
			8'h3e: begin out = 4'b1000; valid = 1; end // 8
			8'h46: begin out = 4'b1001; valid = 1; end // 9
			default: begin out = 4'b0000; valid = 0; end
		endcase
	end
endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @* begin
	valid = 0;
	out = 4'b0000;
	case(code)
		8'h45: out = 4'b0000; valid = 1; // Key 0
		8'h16: out = 4'b0001; valid = 1; // Key 1
		8'h1e: out = 4'b0010; valid = 1; // Key 2
		8'h26: out = 4'b0011; valid = 1; // Key 3
		8'h25: out = 4'b0100; valid = 1; // Key 4
		8'h2e: out = 4'b0101; valid = 1; // Key 5
		8'h36: out = 4'b0110; valid = 1; // Key 6
		8'h3d: out = 4'b0111; valid = 1; // Key 7
		8'h3e: out = 4'b1000; valid = 1; // Key 8
		8'h46: out = 4'b1001; valid = 1; // Key 9
		default: begin
			out = 4'b0000;
			valid = 0;
		end
	endcase
end

endmodule

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);

always @* begin
    case (code)
        8'h45: begin out = 4'd0; valid = 1'b1; end
        8'h16: begin out = 4'd1; valid = 1'b1; end
        8'h1e: begin out = 4'd2; valid = 1'b1; end
        8'h26: begin out = 4'd3; valid = 1'b1; end
        8'h25: begin out = 4'd4; valid = 1'b1; end
        8'h2e: begin out = 4'd5; valid = 1'b1; end
        8'h36: begin out = 4'd6; valid = 1'b1; end
        8'h3d: begin out = 4'd7; valid = 1'b1; end
        8'h3e: begin out = 4'd8; valid = 1'b1; end
        8'h46: begin out = 4'd9; valid = 1'b1; end
        default: begin out = 4'd0; valid = 1'b0; end
    endcase
end

endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
	valid = 0;
	out = 4'b0000;

	case (code)
		8'h45: out = 4'b0000; valid = 1; // Key '0'
		8'h16: out = 4'b0001; valid = 1; // Key '1'
		8'h1e: out = 4'b0010; valid = 1; // Key '2'
		8'h26: out = 4'b0011; valid = 1; // Key '3'
		8'h25: out = 4'b0100; valid = 1; // Key '4'
		8'h2e: out = 4'b0101; valid = 1; // Key '5'
		8'h36: out = 4'b0110; valid = 1; // Key '6'
		8'h3d: out = 4'b0111; valid = 1; // Key '7'
		8'h3e: out = 4'b1000; valid = 1; // Key '8'
		8'h46: out = 4'b1001; valid = 1; // Key '9'
		default: begin
			out = 4'b0000;
			valid = 0;
		end
	endcase
end

endmodule

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);
    always @(*) begin
        case (code)
            8'h45: begin out = 4'b0000; valid = 1; end // Key 0
            8'h16: begin out = 4'b0001; valid = 1; end // Key 1
            8'h1e: begin out = 4'b0010; valid = 1; end // Key 2
            8'h26: begin out = 4'b0011; valid = 1; end // Key 3
            8'h25: begin out = 4'b0100; valid = 1; end // Key 4
            8'h2e: begin out = 4'b0101; valid = 1; end // Key 5
            8'h36: begin out = 4'b0110; valid = 1; end // Key 6
            8'h3d: begin out = 4'b0111; valid = 1; end // Key 7
            8'h3e: begin out = 4'b1000; valid = 1; end // Key 8
            8'h46: begin out = 4'b1001; valid = 1; end // Key 9
            default: begin out = 4'b0000; valid = 0; end // Invalid key
        endcase
    end
endmodule

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

always @(*) begin
	valid = 0;
	out = 4'b0000;

	case (code)
		8'h45: begin out = 4'b0000; valid = 1; end // Key '0'
		8'h16: begin out = 4'b0001; valid = 1; end // Key '1'
		8'h1e: begin out = 4'b0010; valid = 1; end // Key '2'
		8'h26: begin out = 4'b0011; valid = 1; end // Key '3'
		8'h25: begin out = 4'b0100; valid = 1; end // Key '4'
		8'h2e: begin out = 4'b0101; valid = 1; end // Key '5'
		8'h36: begin out = 4'b0110; valid = 1; end // Key '6'
		8'h3d: begin out = 4'b0111; valid = 1; end // Key '7'
		8'h3e: begin out = 4'b1000; valid = 1; end // Key '8'
		8'h46: begin out = 4'b1001; valid = 1; end // Key '9'
		default: begin out = 4'b0000; valid = 0; end
	endcase
end

endmodule


module top_module (
	input [7:0] in,
	output [7:0] out
);
	assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule


module top_module (
    input a,
    input b,
    input c,
    input d,
    output reg out
);

always @* begin
    case ({a, b, c, d})
        4'b0000: out = 1'bx; // d (don't care)
        4'b0001: out = 1'b0;
        4'b0010: out = 1'b1;
        4'b0011: out = 1'b1;
        4'b0100: out = 1'b0;
        4'b0101: out = 1'b0;
        4'b0110: out = 1'bx; // d (don't care)
        4'b0111: out = 1'bx; // d (don't care)
        4'b1000: out = 1'b0;
        4'b1001: out = 1'b1;
        4'b1010: out = 1'b1;
        4'b1011: out = 1'b1;
        4'b1100: out = 1'b0;
        4'b1101: out = 1'b1;
        4'b1110: out = 1'b1;
        4'b1111: out = 1'b1;
        default: out = 1'bx; // unspecified states
    endcase
end

endmodule


module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data, shift the rest
        end else if (count_ena) begin
            q <= q - 1; // Decrement the value in the shift register
        end
    end

endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q
);

	always @(posedge clk) begin
		if (shift_ena) begin
			q <= {data, q[3:1]};
		end else if (count_ena) begin
			q <= q - 1;
		end
	end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data at MSB
        end else if (count_ena) begin
            q <= q - 1; // Decrement the register
        end
    end
endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data at MSB
        end else if (count_ena) begin
            q <= q - 1; // Decrement the value
        end
    end
endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q
);

always @(posedge clk) begin
	if (shift_ena) begin
		q <= {data, q[3:1]}; // Shift in data, MSB first
	end else if (count_ena) begin
		q <= q - 1; // Decrement the counter
	end
end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data MSB first
        end else if (count_ena) begin
            q <= q - 1; // Decrement the value in the shift register
        end
    end

endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (shift_ena) begin
			q <= {data, q[3:1]};
		end else if (count_ena) begin
			q <= q - 1;
		end
	end
endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q
);

	always @(posedge clk) begin
		if (shift_ena) begin
			q <= {data, q[3:1]}; // Shift in from MSB
		end else if (count_ena) begin
			q <= q - 1; // Decrement the value
		end
	end

endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data MSB first
        end else if (count_ena) begin
            q <= q - 1; // Decrement value
        end
    end

endmodule

module top_module(
	input clk,
	input shift_ena,
	input count_ena,
	input data,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (shift_ena) begin
			q <= {data, q[3:1]}; // Shift data in
		end else if (count_ena) begin
			q <= q - 1; // Decrement the value
		end
	end
endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift left and insert data at LSB
        end else if (count_ena) begin
            q <= q - 1; // Decrement the current value
        end
    end
endmodule

module top_module(
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (shift_ena) begin
            q <= {data, q[3:1]}; // Shift in data MSB first
        end else if (count_ena) begin
            q <= q - 1; // Decrement the counter
        end
    end

endmodule


module top_module(
    input in,
    output out
);
    assign out = in;
endmodule

module top_module(
	input in,
	output out);

	assign out = in;

endmodule


module top_module(
    input clk,
    input reset,
    output reg shift_ena
);

    reg [2:0] count;
    reg fsm_state;

    always @(posedge clk) begin
        if (reset) begin
            count <= 3'b000;
            shift_ena <= 1'b1;
            fsm_state <= 1'b1;  // Indicating that we are in the shift enable state
        end else begin
            if (fsm_state) begin
                if (count < 3'b011) begin
                    count <= count + 1;
                    shift_ena <= 1'b1; // Assert shift_ena
                end else begin
                    count <= 3'b000;
                    shift_ena <= 1'b0; // De-assert shift_ena after 4 cycles
                    fsm_state <= 1'b0; // Move to shift disable state
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);
    reg [1:0] count;

    always @(posedge clk) begin
        if (reset) begin
            count <= 2'b00;
            shift_ena <= 1'b1;
        end else if (count < 2'b11) begin
            count <= count + 1;
            shift_ena <= 1'b1;
        end else begin
            shift_ena <= 1'b0;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);

reg [1:0] count;

always @(posedge clk) begin
    if (reset) begin
        shift_ena <= 1'b1;
        count <= 2'b00;
    end else if (count < 2'b11) begin
        count <= count + 1;
    end else begin
        shift_ena <= 1'b0;
    end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena);

	reg [1:0] count;

	always @(posedge clk) begin
		if (reset) begin
			shift_ena <= 1;
			count <= 2'b00;
		end else if (count < 2'b11) begin
			count <= count + 1'b1;
			shift_ena <= 1;
		end else begin
			shift_ena <= 0;
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);

reg [2:0] count; // 3-bit counter to track 4 cycles

always @(posedge clk) begin
    if (reset) begin
        shift_ena <= 1'b1; // Enable shift register
        count <= 3'b000;    // Reset count
    end else if (count < 3'd4) begin
        count <= count + 1; // Increment count
        shift_ena <= 1'b1;  // Keep shift enable high
    end else begin
        shift_ena <= 1'b0;  // Disable shift after 4 cycles
    end
end

endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);
    reg [2:0] count;

    always @(posedge clk) begin
        if (reset) begin
            count <= 3'b000;
            shift_ena <= 1'b1;
        end else if (count < 3'b100) begin
            count <= count + 1;
            shift_ena <= 1'b1;
        end else begin
            shift_ena <= 1'b0;
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena
);

	reg [2:0] count; // 3 bits to count from 0 to 4

	always @(posedge clk) begin
		if (reset) begin
			count <= 3'd0;
			shift_ena <= 1'b1; // Assert shift_ena on reset
		end else if (count < 3'd4) begin
			count <= count + 1'b1;
			shift_ena <= 1'b1; // Keep shift_ena asserted for 4 cycles
		end else begin
			shift_ena <= 1'b0; // De-assert shift_ena after 4 cycles
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);
    reg [2:0] counter; // 3-bit counter to count 4 cycles

    always @(posedge clk) begin
        if (reset) begin
            shift_ena <= 1'b1; // Enable shift register for the first cycle
            counter <= 3'b001; // Start counting from 1
        end else if (counter > 0) begin
            counter <= counter + 1'b1;
            shift_ena <= (counter < 3'b100); // Assert shift_ena for 4 cycles
        end else begin
            shift_ena <= 1'b0; // Deassert shift_ena after 4 cycles
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena
);
	reg [1:0] count;

	always @(posedge clk) begin
		if (reset) begin
			shift_ena <= 1'b1; // Enable on reset
			count <= 2'b00; // Initialize count
		end else if (count < 2'b11) begin
			count <= count + 1; // Increment count
		end else begin
			shift_ena <= 1'b0; // Disable after 4 cycles
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena);

	reg [2:0] count; // 3-bit counter to count up to 4

	always @(posedge clk) begin
		if (reset) begin
			count <= 3'b000;
			shift_ena <= 1'b1; // Assert shift enable on reset
		end else if (count < 3'b011) begin
			count <= count + 3'b001;
			shift_ena <= 1'b1; // Keep shift enable asserted for 4 cycles
		end else begin
			shift_ena <= 1'b0; // Deassert after 4 cycles
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);
    reg [1:0] count;

    always @(posedge clk) begin
        if (reset) begin
            shift_ena <= 1;
            count <= 2'b00;
        end else if (count < 2'b11) begin
            count <= count + 1;
            shift_ena <= 1;
        end else begin
            shift_ena <= 0;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);

    reg [1:0] count; // 2-bit counter for 4 cycles

    always @(posedge clk) begin
        if (reset) begin
            count <= 2'b00;
            shift_ena <= 1'b1; // Assert shift_ena
        end else if (count < 2'b11) begin
            count <= count + 1;
            shift_ena <= 1'b1; // Keep shift_ena asserted for 4 cycles
        end else begin
            shift_ena <= 1'b0; // Deassert shift_ena after 4 cycles
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena);

	reg [1:0] counter;

	always @(posedge clk) begin
		if (reset) begin
			counter <= 2'b00;
			shift_ena <= 1'b1;
		end else if (counter < 2'b11) begin
			counter <= counter + 1;
			shift_ena <= 1'b1;
		end else begin
			shift_ena <= 1'b0;
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);

    reg [2:0] count;

    always @(posedge clk) begin
        if (reset) begin
            count <= 3'b000;
            shift_ena <= 1'b1;
        end else if (count < 3'b100) begin
            count <= count + 1;
        end else begin
            shift_ena <= 1'b0;
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output reg shift_ena
);
    reg [1:0] count;

    always @(posedge clk) begin
        if (reset) begin
            shift_ena <= 1'b1;   // Enable shift register on reset
            count <= 2'b00;      // Initialize count
        end else if (count < 2'b11) begin
            count <= count + 1;  // Increment count for 4 cycles
            shift_ena <= 1'b1;    // Keep shift enable high
        end else begin
            shift_ena <= 1'b0;    // Disable shift register after 4 cycles
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena
);

    reg [2:0] count; // 3-bit counter to count 4 cycles

    always @(posedge clk) begin
        if (reset) begin
            count <= 3'b000;
            shift_ena <= 1'b1; // Assert shift_ena
        end else if (count < 3'b011) begin
            count <= count + 1; // Increment count for 4 cycles
            shift_ena <= 1'b1; // Keep shift_ena asserted
        end else begin
            shift_ena <= 1'b0; // Deassert shift_ena after 4 cycles
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg shift_ena);

	reg [1:0] counter;

	always @(posedge clk) begin
		if (reset) begin
			shift_ena <= 1;
			counter <= 2'b00;
		end else if (counter < 2'b11) begin
			counter <= counter + 1;
			shift_ena <= 1;
		end else begin
			shift_ena <= 0;
		end
	end
endmodule


module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

always @(posedge clk) begin
	if (reset) begin
		q <= 4'b0000;
	end else begin
		q <= q + 1;
	end
end

endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q
);
	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			q <= q + 1;
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			q <= q + 1'b1;
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset)
            q <= 4'b0000;
        else
            q <= q + 1;
    end

endmodule


module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

// Assign statement implementation
assign out_assign = (sel_b1 && sel_b2) ? b : a;

// Procedural if statement implementation
always @(*) begin
    if (sel_b1 && sel_b2)
        out_always = b;
    else
        out_always = a;
end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @* begin
        if (sel_b1 && sel_b2) begin
            out_always = b;
        end else begin
            out_always = a;
        end
    end

endmodule

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

// Assign statement for output
assign out_assign = (sel_b1 & sel_b2) ? b : a;

// Procedural if statement for output
always @* begin
	if (sel_b1 && sel_b2)
		out_always = b;
	else
		out_always = a;
end

endmodule

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

assign out_assign = (sel_b1 && sel_b2) ? b : a;

always @(*) begin
	if (sel_b1 && sel_b2)
		out_always = b;
	else
		out_always = a;
end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Mux using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Mux using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);

assign out_assign = (sel_b1 && sel_b2) ? b : a;

always @* begin
	if (sel_b1 && sel_b2)
		out_always = b;
	else
		out_always = a;
end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statement for mux behavior
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement for mux behavior
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statement
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2) begin
            out_always = b;
        end else begin
            out_always = a;
        end
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @(*) begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

assign out_assign = (sel_b1 && sel_b2) ? b : a;

always @(*) begin
    if (sel_b1 && sel_b2) begin
        out_always = b;
    end else begin
        out_always = a;
    end
end

endmodule

module top_module (
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output out_assign,
    output reg out_always
);

    // Using assign statements
    assign out_assign = (sel_b1 && sel_b2) ? b : a;

    // Using procedural if statement
    always @* begin
        if (sel_b1 && sel_b2)
            out_always = b;
        else
            out_always = a;
    end

endmodule


module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b == 1'b0 && c == 1'b1) || (b == 1'b1) || (b == 1'b0 && c == 1'b0 && a == 1'b1);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b & ~c) | (a & ~b) | (a & b);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
assign out = (b & c) | (b & ~a) | (~b & ~c) | (a & b);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b == 0 && c == 1) || (b == 1 && (c == 0 || c == 1)) || (b == 1 && a == 1);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);

assign out = (b & ~c) | (b & a) | (a & c) | (~b & c);

endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b & ~c) | (a & b) | (a & c) | (~a & b & c);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b & c) | (b & ~a) | (c & ~a) | (c & b);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & ~c) | (a & (b | c)) | (~a & (b | ~c));
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & ~c) | (b & a) | (~b & a) | (a & c);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & ~c) | (a & ~b) | (a & c) | (b & c);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
    assign out = (b & ~c) | (a & b) | (a & ~b) | (a & c);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & c) | (a & (b | c));
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & c) | (b & ~a) | (c & ~a);
endmodule

module top_module(
    input a,
    input b,
    input c,
    output out
);
    assign out = (b & c) | (a & b) | (a & c) | (b & ~c);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b & ~c) | (b & a) | (c & a) | (b & c) | (~b & ~a & c);
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
	assign out = (b & ~c) | (a & (b | c));
endmodule

module top_module(
	input a,
	input b,
	input c,
	output out
);
    assign out = (b & c) | (b & ~a) | (~b & a) | (~c & a);
endmodule


module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    always_ff @(current_state, r) begin
        case (current_state)
            A: begin
                if (r[1]) next_state = B;        // Move to B if r1 is high
                else if (r[2]) next_state = C;   // Move to C if r2 is high
                else if (r[3]) next_state = D;   // Move to D if r3 is high
                else next_state = A;             // Stay in A otherwise
            end
            B: begin
                if (r[1]) next_state = B;        // Stay in B if r1 is high
                else next_state = A;             // Return to A if r1 is low
            end
            C: begin
                if (r[2]) next_state = C;        // Stay in C if r2 is high
                else next_state = A;             // Return to A if r2 is low
            end
            default: next_state = A;           // Default case
        endcase
    end

    always_ff @(current_state) begin
        g = 3'b000; // Default to no grants
        case (current_state)
            B: g[1] = 1; // Grant for device 1
            C: g[2] = 1; // Grant for device 2
            // Device 3 can be granted in state D, but logic to handle that can be added if needed
        endcase
    end
endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    typedef enum logic [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always_ff @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // State transition logic
    always_comb begin
        case (current_state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B; // g1 = 1
                else next_state = A;      // return to A if r1 = 0
            end
            C: begin
                if (r[2]) next_state = C; // g2 = 1
                else next_state = A;      // return to A if r2 = 0
            end
            D: begin
                next_state = A;           // return to A from D
            end
            default: next_state = A;   // safety default
        endcase
    end

    // Output logic
    always_ff @(current_state) begin
        g = 3'b000; // default to zero
        case (current_state)
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            D: g[3] = 1; // Grant to device 3
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            A: begin
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else if (r[3])
                    next_state = D;
                else
                    next_state = A;
            end
            B: begin
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end
            C: begin
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default output
        case (current_state)
            A: begin
                if (r[1])
                    g[1] = 1;
                else if (r[2])
                    g[2] = 1;
                else if (r[3])
                    g[3] = 1;
            end
            B: g[1] = 1;
            C: g[2] = 1;
            D: g[3] = 1;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State transition (next state logic)
    always @(*) begin
        case (current_state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B; // g1 is held
                else next_state = A; // grant to 1 is released
            end
            C: begin
                if (r[2]) next_state = C; // g2 is held
                else next_state = A; // grant to 2 is released
            end
            D: begin
                next_state = A; // no grant
            end
            default: next_state = A;
        endcase
    end

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (~resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // default output
        case (current_state)
            B: g[1] = 1; // grant g1
            C: g[2] = 1; // grant g2
            D: g[3] = 1; // grant g3
            default: g = 3'b000; // no grant
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    typedef enum logic[1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always_ff @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always_comb begin
        case (current_state)
            A: begin
                if (r[1]) begin
                    next_state = B;
                end else if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end

            B: begin
                if (r[1]) begin
                    next_state = B;
                end else begin
                    next_state = A;
                end
            end

            C: begin
                if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end

            default: next_state = A;
        endcase
    end

    // Output logic
    always_comb begin
        g = 3'b000; // Default output
        case (current_state)
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            default: g[3] = 1; // Grant to device 3 (if in state A and it is the only request)
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
    reg [1:0] state, next_state;

    // State Flip-Flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn) begin
            state <= A;
        end else begin
            state <= next_state;
        end
    end

    // Next State Logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end
            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end
            D: begin
                next_state = A; // No specified transitions from D, return to A
            end
            default: next_state = A; // Default case
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default all grants to 0
        case (state)
            A: begin
                if (r[1]) g[1] = 1; // Grant to device 1
                else if (r[2]) g[2] = 1; // Grant to device 2
                else if (r[3]) g[3] = 1; // Grant to device 3
            end
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            D: g[3] = 1; // Grant to device 3
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [2:0] {
        A = 3'b000,
        B = 3'b001,
        C = 3'b010,
        D = 3'b011
    } state_t;

    state_t state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end
            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default to no grants
        case (state)
            A: begin
                if (r[1]) g[1] = 1; // Grant to device 1
                else if (r[2]) g[2] = 1; // Grant to device 2
                else if (r[3]) g[3] = 1; // Grant to device 3
            end
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            default: g = 3'b000; // No grant
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    reg [1:0] state, next_state;

    // State encoding
    localparam A = 2'b00,
               B = 2'b01,
               C = 2'b10,
               D = 2'b11;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end
            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default output
        case (state)
            B: g[1] = 1; // Grant for device 1
            C: g[2] = 1; // Grant for device 2
            D: g[3] = 1; // Grant for device 3
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    reg [1:0] state, next_state;

    // State encoding
    localparam A = 2'b00,
               B = 2'b01,
               C = 2'b10;

    // State transition
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            B: begin
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end
            C: begin
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // default all grants to 0
        case (state)
            A: begin
                if (r[1])
                    g[1] = 1;
                else if (r[2])
                    g[2] = 1;
                else if (r[3])
                    g[3] = 1;
            end
            B: begin
                g[1] = 1; // Grant to device 1
            end
            C: begin
                g[2] = 1; // Grant to device 2
            end
            default: g = 3'b000;
        endcase
    end
endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011;
    reg [2:0] state, next_state;

    // State Flip-Flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next State Logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end
            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end
            D: next_state = A;
            default: next_state = A;
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default all grants to 0
        case (state)
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            D: g[3] = 1; // Grant to device 3
            default: g = 3'b000; // No grants
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // State table
    always @(*) begin
        case (current_state)
            A: begin
                g = 3'b000;
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else if (r[3])
                    next_state = D;
                else
                    next_state = A;
            end
            B: begin
                g = 3'b010; // Grant to device 2
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end
            C: begin
                g = 3'b001; // Grant to device 1
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            D: begin
                g = 3'b100; // Grant to device 3
                next_state = A;
            end
            default: begin
                g = 3'b000;
                next_state = A;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    typedef enum logic [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10
    } state_t;

    state_t current_state, next_state;

    // State flip-flops
    always_ff @(posedge clk or negedge resetn) begin
        if (!resetn)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // State table logic
    always_comb begin
        case (current_state)
            A: begin
                if (r[1]) begin
                    next_state = B;
                end else if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end
            B: begin
                if (r[1]) begin
                    next_state = B;
                end else begin
                    next_state = A;
                end
            end
            C: begin
                if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always_comb begin
        g = 3'b000; // default output
        case (current_state)
            B: g[1] = 1'b1; // grant to device 1
            C: g[2] = 1'b1; // grant to device 2
            default: g[3] = 1'b0; // device 3 gets no grant here
        endcase
    end

endmodule

module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output reg [3:1] g
);

	typedef enum reg [1:0] {
		A = 2'b00,
		B = 2'b01,
		C = 2'b10
	} state_t;

	state_t current_state, next_state;

	// State transition
	always @ (posedge clk or negedge resetn) begin
		if (!resetn)
			current_state <= A;
		else
			current_state <= next_state;
	end

	// Next state logic
	always @* begin
		case (current_state)
			A: begin
				if (r[1]) next_state = B;
				else if (r[2]) next_state = C;
				else if (r[3]) next_state = D;
				else next_state = A;
			end
			B: begin
				if (r[1]) next_state = B;
				else next_state = A;
			end
			C: begin
				if (r[2]) next_state = C;
				else next_state = A;
			end
			default: next_state = A;
		endcase
	end

	// Output logic
	always @* begin
		g = 3'b000;
		case (current_state)
			B: g[1] = 1'b1;
			C: g[2] = 1'b1;
			default: g[3] = 1'b0;
		endcase
	end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    reg [1:0] state, next_state;

    // State encoding
    localparam A = 2'b00,
               B = 2'b01,
               C = 2'b10,
               D = 2'b11;

    // State register
    always @(posedge clk or negedge resetn) begin
        if (!resetn) begin
            state <= A;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) begin
                    next_state = B;
                end else if (r[2]) begin
                    next_state = C;
                end else if (r[3]) begin
                    next_state = D;
                end else begin
                    next_state = A;
                end
            end
            B: begin
                if (r[1]) begin
                    next_state = B;
                end else begin
                    next_state = A;
                end
            end
            C: begin
                if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output logic
    always @(*) begin
        g = 3'b000; // Default output
        case (state)
            B: g[1] = 1; // Grant for device 1
            C: g[2] = 1; // Grant for device 2
            D: g[3] = 1; // Grant for device 3
            default: g = 3'b000; // No grants
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10
    } state_t;

    state_t state, next_state;

    // State flip-flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // State transition
    always @(*) begin
        next_state = state;
        g = 3'b000; // Default output

        case (state)
            A: begin
                if (r[1]) begin
                    next_state = B;
                    g[1] = 1;  // Grant g1
                end else if (r[2]) begin
                    next_state = C;
                    g[2] = 1;  // Grant g2
                end else if (r[3]) begin
                    next_state = A; // Remain in A
                    g[3] = 1;  // Grant g3
                end
            end

            B: begin
                if (r[1]) begin
                    next_state = B; // Stay in B
                    g[1] = 1;  // Grant g1
                end else begin
                    next_state = A;
                end
            end

            C: begin
                if (r[2]) begin
                    next_state = C; // Stay in C
                    g[2] = 1;  // Grant g2
                end else begin
                    next_state = A;
                end
            end

            default: next_state = A; // Fallback
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
    reg [1:0] state, next_state;

    // State Flip-Flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next State Logic
    always @(*) begin
        case (state)
            A: begin
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else if (r[3])
                    next_state = D;
                else
                    next_state = A;
            end

            B: begin
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end

            C: begin
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end

            D: begin
                next_state = A; // D goes to A in any case
            end

            default: next_state = A;
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default all grants to 0
        case (state)
            B: g[1] = 1; // Grant for device 1
            C: g[2] = 1; // Grant for device 2
            D: g[3] = 1; // Grant for device 3
            default: g = 3'b000; // No grant in other states
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t state, next_state;

    // State Flip-Flops
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next State Logic
    always @(*) begin
        case(state)
            A: begin
                if (r[1])
                    next_state = B;
                else if (r[2])
                    next_state = C;
                else if (r[3])
                    next_state = D;
                else
                    next_state = A;
            end
            B: begin
                if (r[1])
                    next_state = B;
                else
                    next_state = A;
            end
            C: begin
                if (r[2])
                    next_state = C;
                else
                    next_state = A;
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default output
        case(state)
            B: g[1] = 1;
            C: g[2] = 1;
            D: g[3] = 1;
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    reg [1:0] state, next_state;

    // State Encoding
    localparam A = 2'd0, B = 2'd1, C = 2'd2, D = 2'd3;

    // State Transition
    always @ (posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Next State Logic
    always @ (*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end

            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end

            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end

            D: begin
                next_state = A;
            end

            default: next_state = A;
        endcase
    end

    // Output Logic
    always @ (*) begin
        g = 3'b000; // Default output
        case (state)
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            D: g[3] = 1; // Grant to device 3
            default: g = 3'b000;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State definitions
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10
    } state_t;

    state_t state, next_state;

    // State transition
    always @(*) begin
        case (state)
            A: begin
                if (r[1]) next_state = B;
                else if (r[2]) next_state = C;
                else if (r[3]) next_state = D;
                else next_state = A;
            end
            B: begin
                if (r[1]) next_state = B;
                else next_state = A;
            end
            C: begin
                if (r[2]) next_state = C;
                else next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // State storage
    always @(posedge clk or negedge resetn) begin
        if (!resetn)
            state <= A;
        else
            state <= next_state;
    end

    // Output logic
    always @(*) begin
        g = 3'b000;  // Default output
        case (state)
            A: begin
                if (r[1]) g[1] = 1;
                else if (r[2]) g[2] = 1;
                else if (r[3]) g[3] = 1;
            end
            B: g[1] = 1;
            C: g[2] = 1;
        endcase
    end

endmodule

module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output reg [3:1] g
);

    // State Encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State Flip-Flops
    always @(posedge clk or negedge resetn) begin
        if (~resetn) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    // Next State Logic
    always @(*) begin
        case (current_state)
            A: begin
                if (r[1]) begin
                    next_state = B;
                end else if (r[2]) begin
                    next_state = C;
                end else if (r[3]) begin
                    next_state = D;
                end else begin
                    next_state = A;
                end
            end
            B: begin
                if (r[1]) begin
                    next_state = B;
                end else begin
                    next_state = A;
                end
            end
            C: begin
                if (r[2]) begin
                    next_state = C;
                end else begin
                    next_state = A;
                end
            end
            D: begin
                next_state = A;
            end
            default: next_state = A;
        endcase
    end

    // Output Logic
    always @(*) begin
        g = 3'b000; // Default output
        case (current_state)
            B: g[1] = 1; // Grant to device 1
            C: g[2] = 1; // Grant to device 2
            D: g[3] = 1; // Grant to device 3
            default: g = 3'b000; // No grants
        endcase
    end

endmodule


module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			if (q == 4'b1001) begin
				q <= 4'b0000; // Reset to 0 after counting to 9
			end else begin
				q <= q + 1; // Increment the counter
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1;
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 0;
		end else begin
			if (q == 9) begin
				q <= 0;
			end else begin
				q <= q + 1;
			end
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000; // Reset counter to 0
		end else if (q == 4'b1001) begin
			q <= 4'b0000; // Reset to 0 after counting to 9
		end else begin
			q <= q + 1; // Increment counter
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else if (q == 4'b1001) begin
            q <= 4'b0000;
        end else begin
            q <= q + 1'b1;
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

	always @(posedge clk) begin
		if (reset) begin
			q <= 4'b0000;
		end else begin
			if (q == 4'b1001) begin
				q <= 4'b0000;
			end else begin
				q <= q + 1;
			end
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output reg [3:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0000;
        end else begin
            if (q == 4'b1001) begin
                q <= 4'b0000;
            end else begin
                q <= q + 1;
            end
        end
    end

endmodule