module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state, bump_left, bump_right, ground) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        case (current_state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                    walk_left = 1;
                end
            end
            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                    walk_right = 1;
                end
            end
            FALL: begin
                if (ground) begin
                    next_state = (bump_left) ? WALK_RIGHT : (bump_right) ? WALK_LEFT : current_state;
                end else begin
                    next_state = FALL;
                    aaah = 1;
                end
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALL
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always_ff @(state, bump_left, bump_right, ground) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        next_state = state;

        case (state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end
                walk_left = 1;
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end
                walk_right = 1;
            end

            FALL: begin
                if (ground) begin
                    next_state = (walk_left) ? WALK_LEFT : WALK_RIGHT;
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        LEFT_WALK = 2'b00,
        RIGHT_WALK = 2'b01,
        FALL = 2'b10
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= LEFT_WALK;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state, bump_left, bump_right, ground) begin
        aaah = 0;
        walk_left = 0;
        walk_right = 0;

        case (current_state)
            LEFT_WALK: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = RIGHT_WALK;
                end else if (bump_left) begin
                    next_state = LEFT_WALK;
                end else begin
                    next_state = LEFT_WALK;
                    walk_left = 1;
                end
            end

            RIGHT_WALK: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = LEFT_WALK;
                end else if (bump_right) begin
                    next_state = RIGHT_WALK;
                end else begin
                    next_state = RIGHT_WALK;
                    walk_right = 1;
                end
            end

            FALL: begin
                if (ground) begin
                    if (current_state == LEFT_WALK) begin
                        next_state = LEFT_WALK;
                    end else begin
                        next_state = RIGHT_WALK;
                    end
                end else begin
                    next_state = FALL;
                    aaah = 1;
                end
            end

            default: next_state = LEFT_WALK;
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset)
            current_state <= WALK_LEFT;
        else
            current_state <= next_state;
    end

    always @(*) begin
        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;
                if (!ground)
                    next_state = FALL;
                else if (bump_right)
                    next_state = WALK_RIGHT;
                else
                    next_state = WALK_LEFT;
            end

            WALK_RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                aaah = 0;
                if (!ground)
                    next_state = FALL;
                else if (bump_left)
                    next_state = WALK_LEFT;
                else
                    next_state = WALK_RIGHT;
            end

            FALL: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1;
                if (ground)
                    next_state = (bump_left) ? WALK_LEFT : (bump_right) ? WALK_RIGHT : current_state;
                else
                    next_state = FALL;
            end

            default: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 0;
                next_state = WALK_LEFT;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        STATE_WALK_LEFT = 2'b00,
        STATE_WALK_RIGHT = 2'b01,
        STATE_FALL_LEFT = 2'b10,
        STATE_FALL_RIGHT = 2'b11
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= STATE_WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state or bump_left or bump_right or ground) begin
        walk_left = 0;
        walk_right = 0;
        aaah = 0;
        case (current_state)
            STATE_WALK_LEFT: begin
                if (!ground) begin
                    aaah = 1;
                    next_state = STATE_FALL_LEFT;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    walk_left = 1;
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_WALK_RIGHT: begin
                if (!ground) begin
                    aaah = 1;
                    next_state = STATE_FALL_RIGHT;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    walk_right = 1;
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_FALL_LEFT: begin
                if (ground) begin
                    next_state = STATE_WALK_LEFT;
                end else begin
                    aaah = 1;
                    next_state = STATE_FALL_LEFT;
                end
            end

            STATE_FALL_RIGHT: begin
                if (ground) begin
                    next_state = STATE_WALK_RIGHT;
                end else begin
                    aaah = 1;
                    next_state = STATE_FALL_RIGHT;
                end
            end

            default: next_state = STATE_WALK_LEFT;
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL
    } state_t;

    state_t state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        aaah <= (state == STATE_FALL);

        case (state)
            STATE_WALK_LEFT: begin
                walk_left <= 1;
                walk_right <= 0;
                if (!ground) begin
                    next_state <= STATE_FALL;
                end else if (bump_right) begin
                    next_state <= STATE_WALK_RIGHT;
                end else if (bump_left) begin
                    next_state <= STATE_WALK_LEFT;
                end else begin
                    next_state <= STATE_WALK_LEFT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_left <= 0;
                walk_right <= 1;
                if (!ground) begin
                    next_state <= STATE_FALL;
                end else if (bump_left) begin
                    next_state <= STATE_WALK_LEFT;
                end else if (bump_right) begin
                    next_state <= STATE_WALK_RIGHT;
                end else begin
                    next_state <= STATE_WALK_RIGHT;
                end
            end

            STATE_FALL: begin
                walk_left <= 0;
                walk_right <= 0;
                if (ground) begin
                    next_state <= (bump_left) ? STATE_WALK_LEFT : (bump_right) ? STATE_WALK_RIGHT : (walk_left) ? STATE_WALK_LEFT : STATE_WALK_RIGHT;
                end else begin
                    next_state <= STATE_FALL;
                end
            end

            default: begin
                next_state <= STATE_WALK_LEFT;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALL
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_comb begin
        next_state = current_state;
        aaah = 0;
        walk_left = 0;
        walk_right = 0;

        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else if (bump_left) begin
                    next_state = WALK_RIGHT;
                end
            end

            WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else if (bump_right) begin
                    next_state = WALK_LEFT;
                end
            end

            FALL: begin
                if (ground) begin
                    if (current_state == WALK_LEFT) begin
                        next_state = WALK_LEFT;
                    end else begin
                        next_state = WALK_RIGHT;
                    end
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= STATE_WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state; // Default to hold state
        walk_left = 0;
        walk_right = 0;
        aaah = 0;

        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_FALL: begin
                aaah = 1; // Falling state
                if (ground) begin
                    next_state = (walk_left ? STATE_WALK_LEFT : STATE_WALK_RIGHT);
                end
            end

        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            WALK_LEFT: begin
                aaah = 0;
                if (!ground) begin
                    next_state = FALL;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                end
            end

            WALK_RIGHT: begin
                aaah = 0;
                if (!ground) begin
                    next_state = FALL;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                end
            end

            FALL: begin
                aaah = 1;
                if (ground) begin
                    if (state == WALK_LEFT) begin
                        next_state = WALK_LEFT;
                    end else begin
                        next_state = WALK_RIGHT;
                    end
                end else begin
                    next_state = FALL;
                end
            end
        endcase
    end

    always @(*) begin
        walk_left = (state == WALK_LEFT);
        walk_right = (state == WALK_RIGHT);
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

	typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
	state_t current_state, next_state;

	always_ff @(posedge clk or posedge areset) begin
		if (areset) begin
			current_state <= WALK_LEFT;
		end else begin
			current_state <= next_state;
		end
	end

	always_ff @(current_state or bump_left or bump_right or ground) begin
		walk_left = 0;
		walk_right = 0;
		aaah = 0;
		next_state = current_state;

		case (current_state)
			WALK_LEFT: begin
				walk_left = 1;
				if (!ground) begin
					next_state = FALL;
					aaah = 1;
				end else if (bump_right) begin
					next_state = WALK_RIGHT;
				end else if (bump_left) begin
					next_state = WALK_RIGHT;
				end
			end

			WALK_RIGHT: begin
				walk_right = 1;
				if (!ground) begin
					next_state = FALL;
					aaah = 1;
				end else if (bump_left) begin
					next_state = WALK_LEFT;
				end else if (bump_right) begin
					next_state = WALK_LEFT;
				end
			end

			FALL: begin
				aaah = 1;
				if (ground) begin
					if (current_state == WALK_LEFT) begin
						next_state = WALK_LEFT;
					end else if (current_state == WALK_RIGHT) begin
						next_state = WALK_RIGHT;
					end
				end
			end
		endcase
	end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;

        case(state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    walk_left = 1;
                end
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else begin
                    walk_right = 1;
                end
            end

            FALL: begin
                if (ground) begin
                    if (next_state == WALK_LEFT && bump_right) begin
                        next_state = WALK_RIGHT;
                    end else if (next_state == WALK_RIGHT && bump_left) begin
                        next_state = WALK_LEFT;
                    end else begin
                        next_state = state; // Remain in FALL until ground is back
                    end
                end else begin
                    aaah = 1; // Continue falling and saying "aaah"
                end
            end

            default: next_state = WALK_LEFT; // Default state
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

	typedef enum reg [1:0] {
		STATE_WALK_LEFT,
		STATE_WALK_RIGHT,
		STATE_FALL
	} state_t;

	state_t current_state, next_state;

	always @(posedge clk or posedge areset) begin
		if (areset) begin
			current_state <= STATE_WALK_LEFT;
		end else begin
			current_state <= next_state;
		end
	end

	always @(*) begin
		case (current_state)
			STATE_WALK_LEFT: begin
				aaah = 0;
				if (!ground) begin
					next_state = STATE_FALL;
				end else if (bump_right) begin
					next_state = STATE_WALK_RIGHT;
				end else begin
					next_state = STATE_WALK_LEFT;
				end
			end

			STATE_WALK_RIGHT: begin
				aaah = 0;
				if (!ground) begin
					next_state = STATE_FALL;
				end else if (bump_left) begin
					next_state = STATE_WALK_LEFT;
				end else begin
					next_state = STATE_WALK_RIGHT;
				end
			end

			STATE_FALL: begin
				aaah = 1;
				if (ground) begin
					if (current_state == STATE_WALK_LEFT) begin
						next_state = STATE_WALK_LEFT;
					end else begin
						next_state = STATE_WALK_RIGHT;
					end
				end else begin
					next_state = STATE_FALL;
				end
			end

			default: begin
				next_state = STATE_WALK_LEFT;
				aaah = 0;
			end
		endcase
	end

	always @(*) begin
		walk_left = (current_state == STATE_WALK_LEFT);
		walk_right = (current_state == STATE_WALK_RIGHT);
	end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= STATE_WALK_LEFT;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;

        case (state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (ground == 0) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end
            end
            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (ground == 0) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end
            end
            STATE_FALL: begin
                if (ground == 1) begin
                    if (state == STATE_WALK_LEFT) begin
                        next_state = STATE_WALK_LEFT;
                    end else begin
                        next_state = STATE_WALK_RIGHT;
                    end
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {
        WALK_LEFT = 2'b00,
        WALK_RIGHT = 2'b01,
        FALL_LEFT = 2'b10,
        FALL_RIGHT = 2'b11
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @* begin
        aaah = 0;
        walk_left = 0;
        walk_right = 0;
        next_state = current_state;

        case (current_state)
            WALK_LEFT: begin
                if (!ground) begin
                    aaah = 1;
                    next_state = FALL_LEFT;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end
                walk_left = 1;
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    aaah = 1;
                    next_state = FALL_RIGHT;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end
                walk_right = 1;
            end

            FALL_LEFT: begin
                if (ground) begin
                    next_state = WALK_LEFT;
                end
                aaah = 1;
            end

            FALL_RIGHT: begin
                if (ground) begin
                    next_state = WALK_RIGHT;
                end
                aaah = 1;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

	typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
	state_t state, next_state;

	// State transition logic
	always @(*) begin
		next_state = state;
		aaah = 0;
		walk_left = 0;
		walk_right = 0;

		case(state)
			WALK_LEFT: begin
				if (ground == 0) begin
					next_state = FALL;
					aaah = 1;
				end else if (bump_right) begin
					next_state = WALK_RIGHT;
				end else begin
					walk_left = 1;
				end
			end
			WALK_RIGHT: begin
				if (ground == 0) begin
					next_state = FALL;
					aaah = 1;
				end else if (bump_left) begin
					next_state = WALK_LEFT;
				end else begin
					walk_right = 1;
				end
			end
			FALL: begin
				if (ground == 1) begin
					if (walk_left) begin
						next_state = WALK_LEFT;
					end else begin
						next_state = WALK_RIGHT;
					end
				end
			end
		endcase
	end

	// State update logic
	always @(posedge clk or posedge areset) begin
		if (areset) begin
			state <= WALK_LEFT;
		end else begin
			state <= next_state;
		end
	end
endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {
        WALK_LEFT,
        WALK_RIGHT,
        FALLING
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state;
        aaah = 0;
        walk_left = 0;
        walk_right = 0;

        case (current_state)
            WALK_LEFT: begin
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    walk_left = 1;
                end
            end

            WALK_RIGHT: begin
                if (!ground) begin
                    next_state = FALLING;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else begin
                    walk_right = 1;
                end
            end

            FALLING: begin
                if (ground) begin
                    if (current_state == WALK_LEFT) begin
                        next_state = WALK_LEFT;
                    end else begin
                        next_state = WALK_RIGHT;
                    end
                end
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

typedef enum logic [1:0] {
  WALK_LEFT = 2'b00,
  WALK_RIGHT = 2'b01,
  FALL = 2'b10
} state_t;

state_t current_state, next_state;

always_ff @(posedge clk or posedge areset) begin
	if (areset) begin
		current_state <= WALK_LEFT;
		walk_left <= 1;
		walk_right <= 0;
		aaah <= 0;
	end else begin
		current_state <= next_state;
	end
end

always_ff @(current_state or bump_left or bump_right or ground) begin
	next_state = current_state;
	aaah = 0;
	walk_left = 0;
	walk_right = 0;

	case (current_state)
		WALK_LEFT: begin
			if (!ground) begin
				next_state = FALL;
				aaah = 1;
			end else if (bump_right) begin
				next_state = WALK_RIGHT;
			end else begin
				walk_left = 1;
			end
		end

		WALK_RIGHT: begin
			if (!ground) begin
				next_state = FALL;
				aaah = 1;
			end else if (bump_left) begin
				next_state = WALK_LEFT;
			end else begin
				walk_right = 1;
			end
		end

		FALL: begin
			if (ground) begin
				if (current_state == WALK_LEFT) begin
					next_state = WALK_LEFT;
					walk_left = 1;
				end else begin
					next_state = WALK_RIGHT;
					walk_right = 1;
				end
			end
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum reg [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
    state_t current_state, next_state;

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        case (current_state)
            WALK_LEFT: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;
                if (!ground) begin
                    next_state = FALL;
                end else if (bump_right) begin
                    next_state = WALK_RIGHT;
                end else begin
                    next_state = WALK_LEFT;
                end
            end
            WALK_RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                aaah = 0;
                if (!ground) begin
                    next_state = FALL;
                end else if (bump_left) begin
                    next_state = WALK_LEFT;
                end else begin
                    next_state = WALK_RIGHT;
                end
            end
            FALL: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1;
                if (ground) begin
                    if (current_state == WALK_LEFT)
                        next_state = WALK_LEFT;
                    else
                        next_state = WALK_RIGHT;
                end else begin
                    next_state = FALL;
                end
            end
            default: begin
                next_state = WALK_LEFT;
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output reg walk_left,
	output reg walk_right,
	output reg aaah
);

typedef enum logic [1:0] {WALK_LEFT, WALK_RIGHT, FALL} state_t;
state_t state, next_state;

always_ff @(posedge clk or posedge areset) begin
	if (areset) begin
		state <= WALK_LEFT;
		walk_left <= 1;
		walk_right <= 0;
		aaah <= 0;
	end else begin
		state <= next_state;
	end
end

always_comb begin
	next_state = state;
	walk_left = 0;
	walk_right = 0;
	aaah = 0;

	case (state)
		WALK_LEFT: begin
			if (!ground) begin
				next_state = FALL;
				aaah = 1;
			end else if (bump_right) begin
				next_state = WALK_RIGHT;
			end else begin
				walk_left = 1;
			end
		end
		WALK_RIGHT: begin
			if (!ground) begin
				next_state = FALL;
				aaah = 1;
			end else if (bump_left) begin
				next_state = WALK_LEFT;
			end else begin
				walk_right = 1;
			end
		end
		FALL: begin
			if (ground) begin
				if (bump_left) begin
					next_state = WALK_RIGHT;
				end else if (bump_right) begin
					next_state = WALK_LEFT;
				end else begin
					next_state = (walk_left ? WALK_LEFT : WALK_RIGHT);
				end
			end
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_left,
    output reg walk_right,
    output reg aaah
);

    typedef enum logic [1:0] {
        STATE_WALK_LEFT,
        STATE_WALK_RIGHT,
        STATE_FALL
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            current_state <= STATE_WALK_LEFT;
        end else begin
            current_state <= next_state;
        end
    end

    always_comb begin
        next_state = current_state;
        walk_left = 0;
        walk_right = 0;
        aaah = 0;

        case (current_state)
            STATE_WALK_LEFT: begin
                walk_left = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_right) begin
                    next_state = STATE_WALK_RIGHT;
                end else if (bump_left) begin
                    next_state = STATE_WALK_RIGHT;
                end
            end

            STATE_WALK_RIGHT: begin
                walk_right = 1;
                if (!ground) begin
                    next_state = STATE_FALL;
                    aaah = 1;
                end else if (bump_left) begin
                    next_state = STATE_WALK_LEFT;
                end else if (bump_right) begin
                    next_state = STATE_WALK_LEFT;
                end
            end

            STATE_FALL: begin
                if (ground) begin
                    next_state = (walk_left) ? STATE_WALK_LEFT : STATE_WALK_RIGHT;
                end
            end
        endcase
    end

endmodule


module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);
    reg [3:0] ones, tens, hundreds, thousands;

    assign ena[1] = (ones == 4'd9) && (tens < 4'd9);
    assign ena[2] = (tens == 4'd9) && (hundreds < 4'd9);
    assign ena[3] = (hundreds == 4'd9) && (thousands < 4'd9);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'd0;
            tens <= 4'd0;
            hundreds <= 4'd0;
            thousands <= 4'd0;
        end else begin
            if (ones == 4'd9) begin
                ones <= 4'd0;
                if (tens == 4'd9) begin
                    tens <= 4'd0;
                    if (hundreds == 4'd9) begin
                        hundreds <= 4'd0;
                        thousands <= (thousands == 4'd9) ? 4'd0 : thousands + 4'd1;
                    end else begin
                        hundreds <= hundreds + 4'd1;
                    end
                end else begin
                    tens <= tens + 4'd1;
                end
            end else begin
                ones <= ones + 4'd1;
            end
        end
    end

    always @* begin
        q = {thousands, hundreds, tens, ones};
    end
endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 16'b0;
		end else begin
			if (q[3:0] == 4'd9) begin
				q[3:0] <= 4'b0;
				if (q[7:4] == 4'd9) begin
					q[7:4] <= 4'b0;
					if (q[11:8] == 4'd9) begin
						q[11:8] <= 4'b0;
						if (q[15:12] < 4'd9) begin
							q[15:12] <= q[15:12] + 1;
						end
					end else begin
						q[11:8] <= q[11:8] + 1;
					end
					ena[3] <= 1; // enable for hundreds
				end else begin
					q[7:4] <= q[7:4] + 1;
				end
				ena[2] <= 1; // enable for tens
			end else begin
				q[3:0] <= q[3:0] + 1;
			end
			ena[1] <= 1; // enable for ones
		end
	end
endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones, tens, hundreds, thousands;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'b0000;
            tens <= 4'b0000;
            hundreds <= 4'b0000;
            thousands <= 4'b0000;
        end else begin
            if (ones == 4'b1001) begin
                ones <= 4'b0000;
                if (tens == 4'b1001) begin
                    tens <= 4'b0000;
                    if (hundreds == 4'b1001) begin
                        hundreds <= 4'b0000;
                        if (thousands == 4'b1001) begin
                            thousands <= 4'b0000;
                        end else begin
                            thousands <= thousands + 1;
                        end
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end
        end
    end

    always @* begin
        q = {thousands, hundreds, tens, ones};
        ena[1] = (ones == 4'b1001);
        ena[2] = (tens == 4'b1001 && ones == 4'b1001);
        ena[3] = (hundreds == 4'b1001 && tens == 4'b1001 && ones == 4'b1001);
    end

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 0;
        end else begin
            if (q[3:0] == 9) begin
                q[3:0] <= 0;
                ena[1] <= 1;
                if (q[7:4] == 9) begin
                    q[7:4] <= 0;
                    ena[2] <= 1;
                    if (q[11:8] == 9) begin
                        q[11:8] <= 0;
                        ena[3] <= 1;
                        if (q[15:12] < 9) begin
                            q[15:12] <= q[15:12] + 1;
                            ena[3] <= 0;
                        end
                    end else begin
                        q[11:8] <= q[11:8] + 1;
                        ena[3] <= 0;
                    end
                end else begin
                    q[7:4] <= q[7:4] + 1;
                    ena[2] <= 0;
                end
            end else begin
                q[3:0] <= q[3:0] + 1;
                ena[1] <= 0;
            end
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 16'b0;
		end else begin
			if (q[3:0] == 9) begin
				q[3:0] <= 4'b0;
				if (q[7:4] == 9) begin
					q[7:4] <= 4'b0;
					if (q[11:8] == 9) begin
						q[11:8] <= 4'b0;
						if (q[15:12] == 9) begin
							q[15:12] <= 4'b0;
						end else begin
							q[15:12] <= q[15:12] + 1;
						end
						ena[3] <= 1;
					end else begin
						q[11:8] <= q[11:8] + 1;
						ena[2] <= 1;
						ena[3] <= 0;
					end
				end else begin
					q[7:4] <= q[7:4] + 1;
					ena[1] <= 1;
					ena[2] <= 0;
					ena[3] <= 0;
				end
			end else begin
				q[3:0] <= q[3:0] + 1;
				ena[1] <= 0;
				ena[2] <= 0;
				ena[3] <= 0;
			end
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (q[3:0] == 9) begin
                q[3:0] <= 4'b0; // reset ones digit
                if (q[7:4] == 9) begin
                    q[7:4] <= 4'b0; // reset tens digit
                    if (q[11:8] == 9) begin
                        q[11:8] <= 4'b0; // reset hundreds digit
                        if (q[15:12] < 9) begin
                            q[15:12] <= q[15:12] + 1; // increment thousands digit
                        end
                    end else begin
                        q[11:8] <= q[11:8] + 1; // increment hundreds digit
                    end
                end else begin
                    q[7:4] <= q[7:4] + 1; // increment tens digit
                end
            end else begin
                q[3:0] <= q[3:0] + 1; // increment ones digit
            end
        end
    end

    assign ena[1] = (q[3:0] == 9);
    assign ena[2] = (q[7:4] == 9) && ena[1];
    assign ena[3] = (q[11:8] == 9) && ena[2];

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q);

    reg [3:0] ones, tens, hundreds, thousands;

    assign ena[1] = (ones == 9);
    assign ena[2] = (tens == 9 && ones == 9);
    assign ena[3] = (hundreds == 9 && tens == 9 && ones == 9);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 0;
        end else begin
            if (ones == 9) begin
                ones <= 0;
                if (tens == 9) begin
                    tens <= 0;
                    if (hundreds == 9) begin
                        hundreds <= 0;
                        if (thousands == 9) begin
                            thousands <= 0;
                        end else begin
                            thousands <= thousands + 1;
                        end
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end

            q <= {thousands, hundreds, tens, ones};
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	reg [3:0] ones, tens, hundreds, thousands;

	assign ena[1] = (ones == 9);
	assign ena[2] = (tens == 9 && ones == 9);
	assign ena[3] = (hundreds == 9 && tens == 9 && ones == 9);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			ones <= 0;
			tens <= 0;
			hundreds <= 0;
			thousands <= 0;
		end else begin
			if (ones == 9) begin
				ones <= 0;
				if (tens == 9) begin
					tens <= 0;
					if (hundreds == 9) begin
						hundreds <= 0;
						if (thousands < 9) begin
							thousands <= thousands + 1;
						end
					end else begin
						hundreds <= hundreds + 1;
					end
				end else begin
					tens <= tens + 1;
				end
			end else begin
				ones <= ones + 1;
			end
		end
	end

	always @* begin
		q = {thousands, hundreds, tens, ones};
	end

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones, tens, hundreds, thousands;

    assign ena[1] = (ones == 9) && (tens < 9);
    assign ena[2] = (tens == 9) && (hundreds < 9);
    assign ena[3] = (hundreds == 9) && (thousands < 9);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
            ones <= 4'b0;
            tens <= 4'b0;
            hundreds <= 4'b0;
            thousands <= 4'b0;
        end else begin
            if (ones == 9) begin
                ones <= 4'b0;
                if (tens == 9) begin
                    tens <= 4'b0;
                    if (hundreds == 9) begin
                        hundreds <= 4'b0;
                        thousands <= thousands + 1;
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end
            q <= {thousands, hundreds, tens, ones};
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones, tens, hundreds, thousands;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'b0000;
            tens <= 4'b0000;
            hundreds <= 4'b0000;
            thousands <= 4'b0000;
            q <= 16'b0000000000000000;
        end else begin
            if (ones == 4'b1001) begin
                ones <= 4'b0000;
                if (tens == 4'b1001) begin
                    tens <= 4'b0000;
                    if (hundreds == 4'b1001) begin
                        hundreds <= 4'b0000;
                        if (thousands == 4'b1001) begin
                            thousands <= 4'b0000;
                        end else begin
                            thousands <= thousands + 1;
                        end
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end

            q <= {thousands, hundreds, tens, ones};
        end
    end

    assign ena = {hundreds != 4'b0000, tens != 4'b0000, ones != 4'b0000};

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones;
    reg [3:0] tens;
    reg [3:0] hundreds;
    reg [3:0] thousands;

    assign ena[1] = (ones == 9) && (tens < 9);
    assign ena[2] = (tens == 9) && (hundreds < 9);
    assign ena[3] = (hundreds == 9) && (thousands < 9);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'b0000;
            tens <= 4'b0000;
            hundreds <= 4'b0000;
            thousands <= 4'b0000;
            q <= 16'b0000000000000000;
        end else begin
            if (ones < 9) begin
                ones <= ones + 1;
            end else begin
                ones <= 4'b0000;
                if (tens < 9) begin
                    tens <= tens + 1;
                end else begin
                    tens <= 4'b0000;
                    if (hundreds < 9) begin
                        hundreds <= hundreds + 1;
                    end else begin
                        hundreds <= 4'b0000;
                        if (thousands < 9) begin
                            thousands <= thousands + 1;
                        end else begin
                            thousands <= 4'b0000;
                        end
                    end
                end
            end
            q <= {thousands, hundreds, tens, ones};
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	reg [3:0] ones, tens, hundreds, thousands;

	assign ena = {hundreds == 4'd9 && tens == 4'd9, thousands == 4'd9}; // Enable signals for tens and hundreds

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			ones <= 4'b0000;
			tens <= 4'b0000;
			hundreds <= 4'b0000;
			thousands <= 4'b0000;
			q <= 16'b0000000000000000;
		end else begin
			if (ones == 4'd9) begin
				ones <= 4'b0000;
				if (tens == 4'd9) begin
					tens <= 4'b0000;
					if (hundreds == 4'd9) begin
						hundreds <= 4'b0000;
						if (thousands == 4'd9) begin
							thousands <= 4'b0000;
						end else begin
							thousands <= thousands + 1;
						end
					end else begin
						hundreds <= hundreds + 1;
					end
				end else begin
					tens <= tens + 1;
				end
			end else begin
				ones <= ones + 1;
			end
			q <= {thousands, hundreds, tens, ones};
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	reg [3:0] ones, tens, hundreds, thousands;
	reg [3:1] enable;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			ones <= 0;
			tens <= 0;
			hundreds <= 0;
			thousands <= 0;
			q <= 0;
			enable <= 3'b000;
		end else begin
			if (ones == 9) begin
				ones <= 0;
				enable[1] <= 1;
				if (tens == 9) begin
					tens <= 0;
					enable[2] <= 1;
					if (hundreds == 9) begin
						hundreds <= 0;
						enable[3] <= 1;
						if (thousands == 9) begin
							thousands <= 0;
						end else begin
							thousands <= thousands + 1;
						end
					end else begin
						hundreds <= hundreds + 1;
					end
				end else begin
					tens <= tens + 1;
				end
			end else begin
				ones <= ones + 1;
				enable[1] <= 0;
			end
			q <= {thousands, hundreds, tens, ones};
		end
	end

	assign ena = enable;

endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones, tens, hundreds, thousands;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'b0000;
            tens <= 4'b0000;
            hundreds <= 4'b0000;
            thousands <= 4'b0000;
        end else begin
            if (ones == 4'd9) begin
                ones <= 4'b0000;
                if (tens == 4'd9) begin
                    tens <= 4'b0000;
                    if (hundreds == 4'd9) begin
                        hundreds <= 4'b0000;
                        if (thousands == 4'd9) begin
                            thousands <= 4'b0000; // Wrap around
                        end else begin
                            thousands <= thousands + 1'b1;
                        end
                    end else begin
                        hundreds <= hundreds + 1'b1;
                    end
                end else begin
                    tens <= tens + 1'b1;
                end
            end else begin
                ones <= ones + 1'b1;
            end
        end
    end

    assign ena[1] = (ones == 4'd9);
    assign ena[2] = (tens == 4'd9 && ones == 4'd9);
    assign ena[3] = (hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9);

    assign q = {thousands, hundreds, tens, ones};

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q
);

	reg [3:0] ones, tens, hundreds, thousands;

	assign ena[1] = (ones == 9);
	assign ena[2] = (tens == 9 && ones == 9);
	assign ena[3] = (hundreds == 9 && tens == 9 && ones == 9);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 16'b0;
			ones <= 4'b0;
			tens <= 4'b0;
			hundreds <= 4'b0;
			thousands <= 4'b0;
		end else begin
			if (ones == 9) begin
				ones <= 0;
				if (tens == 9) begin
					tens <= 0;
					if (hundreds == 9) begin
						hundreds <= 0;
						if (thousands == 9) begin
							thousands <= 0;
						end else begin
							thousands <= thousands + 1;
						end
					end else begin
						hundreds <= hundreds + 1;
					end
				end else begin
					tens <= tens + 1;
				end
			end else begin
				ones <= ones + 1;
			end
			q <= {thousands, hundreds, tens, ones};
		end
	end

endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	reg [3:0] ones, tens, hundreds, thousands;

	assign q = {thousands, hundreds, tens, ones};
	assign ena = {hundreds >= 4'd9, tens >= 4'd9, ones >= 4'd9};

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			q <= 16'b0;
			ones <= 4'b0;
			tens <= 4'b0;
			hundreds <= 4'b0;
			thousands <= 4'b0;
		end else begin
			if (ones < 4'd9) begin
				ones <= ones + 1;
			end else begin
				ones <= 4'b0;
				if (tens < 4'd9) begin
					tens <= tens + 1;
				end else begin
					tens <= 4'b0;
					if (hundreds < 4'd9) begin
						hundreds <= hundreds + 1;
					end else begin
						hundreds <= 4'b0;
						if (thousands < 4'd9) begin
							thousands <= thousands + 1;
						end else begin
							thousands <= 4'b0;
						end
					end
				end
			end
		end
	end
endmodule

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);

	reg [3:0] ones, tens, hundreds, thousands;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			ones <= 4'd0;
			tens <= 4'd0;
			hundreds <= 4'd0;
			thousands <= 4'd0;
		end else begin
			if (ones == 4'd9) begin
				ones <= 4'd0;
				if (tens == 4'd9) begin
					tens <= 4'd0;
					if (hundreds == 4'd9) begin
						hundreds <= 4'd0;
						if (thousands == 4'd9) begin
							thousands <= 4'd0;
						end else begin
							thousands <= thousands + 1;
						end
					end else begin
						hundreds <= hundreds + 1;
					end
				end else begin
					tens <= tens + 1;
				end
			end else begin
				ones <= ones + 1;
			end
		end
	end

	assign ena = {thousands > 0, hundreds > 0, tens > 0};
	always @* begin
		q = {thousands, hundreds, tens, ones};
	end
endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);

    reg [3:0] ones, tens, hundreds, thousands;

    assign q = {thousands, hundreds, tens, ones};
    assign ena = {hundreds >= 9, tens >= 9, ones >= 9};

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 4'b0000;
            tens <= 4'b0000;
            hundreds <= 4'b0000;
            thousands <= 4'b0000;
        end else begin
            if (ones == 9) begin
                ones <= 4'b0000;
                if (tens == 9) begin
                    tens <= 4'b0000;
                    if (hundreds == 9) begin
                        hundreds <= 4'b0000;
                        if (thousands < 9) begin
                            thousands <= thousands + 1;
                        end
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q
);
    reg [3:0] ones, tens, hundreds, thousands;

    assign q = {thousands, hundreds, tens, ones};
    assign ena = {hundreds == 9 && tens == 9 && ones == 9, hundreds == 9 && tens < 9, ones == 9};

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ones <= 0;
            tens <= 0;
            hundreds <= 0;
            thousands <= 0;
        end else begin
            if (ones == 9) begin
                ones <= 0;
                if (tens == 9) begin
                    tens <= 0;
                    if (hundreds == 9) begin
                        hundreds <= 0;
                        if (thousands < 9) begin
                            thousands <= thousands + 1;
                        end
                    end else begin
                        hundreds <= hundreds + 1;
                    end
                end else begin
                    tens <= tens + 1;
                end
            end else begin
                ones <= ones + 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    output [3:1] ena,
    output reg [15:0] q);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            q <= 16'b0;
        end else begin
            if (q[3:0] == 4'd9) begin
                q[3:0] <= 4'b0; // Reset ones digit
                if (q[7:4] == 4'd9) begin
                    q[7:4] <= 4'b0; // Reset tens digit
                    if (q[11:8] == 4'd9) begin
                        q[11:8] <= 4'b0; // Reset hundreds digit
                        if (q[15:12] < 4'd9) begin
                            q[15:12] <= q[15:12] + 1; // Increment thousands digit
                            ena[3] <= 1; // Enable thousands
                        end else begin
                            ena[3] <= 0; // No enable if overflow
                        end
                    end else begin
                        q[11:8] <= q[11:8] + 1; // Increment hundreds digit
                        ena[2] <= 1; // Enable hundreds
                    end
                end else begin
                    q[7:4] <= q[7:4] + 1; // Increment tens digit
                    ena[1] <= 1; // Enable tens
                end
            end else begin
                q[3:0] <= q[3:0] + 1; // Increment ones digit
                ena[1] <= 0; // Disable tens enable
            end
        end
    end

endmodule