module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    // State encoding
    typedef enum logic [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // Output logic
    always_ff @(current_state) begin
        case (current_state)
            A: out = 0;
            B: out = 0;
            C: out = 0;
            D: out = 1;
            default: out = 0;
        endcase
    end

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always_ff @(current_state, in) begin
        case (current_state)
            A: next_state = (in == 0) ? A : B;
            B: next_state = (in == 0) ? C : B;
            C: next_state = (in == 0) ? A : D;
            D: next_state = (in == 0) ? C : B;
            default: next_state = A;
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg out
);

typedef enum reg [1:0] {A, B, C, D} state_t;
state_t state, next_state;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= A;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	case (state)
		A: begin
			next_state = (in == 0) ? A : B;
			out = 0;
		end
		B: begin
			next_state = (in == 0) ? C : B;
			out = 0;
		end
		C: begin
			next_state = (in == 0) ? A : D;
			out = 0;
		end
		D: begin
			next_state = (in == 0) ? C : B;
			out = 1;
		end
		default: begin
			next_state = A;
			out = 0;
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);
    reg [1:0] state, next_state;

    parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= A;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            A: begin
                next_state = (in) ? B : A;
                out = 0;
            end
            B: begin
                next_state = (in) ? B : C;
                out = 0;
            end
            C: begin
                next_state = (in) ? D : A;
                out = 0;
            end
            D: begin
                next_state = (in) ? B : C;
                out = 1;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum logic [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state, in) begin
        case (current_state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= A;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            A: next_state = (in == 0) ? A : B;
            B: next_state = (in == 0) ? C : B;
            C: next_state = (in == 0) ? A : D;
            D: next_state = (in == 0) ? C : B;
            default: next_state = A; // default case to avoid latches
        endcase
    end

    // Output logic
    always @(*) begin
        case (current_state)
            A, B, C: out = 0;
            D: out = 1;
            default: out = 0; // default case for safety
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    // State encoding
    typedef enum reg [1:0] {A, B, C, D} state_t;
    state_t state, next_state;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= A;
        end else begin
            state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        case (state)
            A: next_state = (in == 0) ? A : B;
            B: next_state = (in == 0) ? C : B;
            C: next_state = (in == 0) ? A : D;
            D: next_state = (in == 0) ? C : B;
            default: next_state = A; // Should never happen
        endcase
    end

    // Output logic
    always @(state) begin
        case (state)
            A, B, C: out = 0;
            D: out = 1;
            default: out = 0; // Should never happen
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg out
);

	typedef enum reg [1:0] {A, B, C, D} state_t;
	state_t current_state, next_state;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= A;
		end else begin
			current_state <= next_state;
		end
	end

	always @(*) begin
		case (current_state)
			A: begin
				if (in) next_state = B; else next_state = A;
				out = 0;
			end
			B: begin
				if (in) next_state = B; else next_state = C;
				out = 0;
			end
			C: begin
				if (in) next_state = D; else next_state = A;
				out = 0;
			end
			D: begin
				if (in) next_state = B; else next_state = C;
				out = 1;
			end
			default: begin
				next_state = A;
				out = 0;
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum reg [1:0] {A, B, C, D} state_t;
    state_t current_state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= A;
        else
            current_state <= next_state;
    end

    always_comb begin
        case (current_state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum reg [1:0] {A, B, C, D} state_t;
    state_t current_state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        case (current_state)
            A: begin
                next_state = (in ? B : A);
                out = 0;
            end
            B: begin
                next_state = (in ? B : C);
                out = 0;
            end
            C: begin
                next_state = (in ? D : A);
                out = 0;
            end
            D: begin
                next_state = (in ? B : C);
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        case (current_state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum reg [1:0] {A, B, C, D} state_t;
    state_t state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            state <= A;
        else
            state <= next_state;
    end

    always_comb begin
        case (state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_type;

    state_type current_state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= A;
        else
            current_state <= next_state;
    end

    always @(*) begin
        case (current_state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum reg [1:0] {A, B, C, D} state_t;
    state_t state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= A;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        case (state)
            A: begin
                if (in) next_state = B; else next_state = A;
                out = 0;
            end
            B: begin
                if (in) next_state = B; else next_state = C;
                out = 0;
            end
            C: begin
                if (in) next_state = D; else next_state = A;
                out = 0;
            end
            D: begin
                if (in) next_state = B; else next_state = C;
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    typedef enum logic [1:0] {A, B, C, D} state_t;
    state_t current_state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= A;
        else
            current_state <= next_state;
    end

    always_comb begin
        case (current_state)
            A: begin
                if (in)
                    next_state = B;
                else
                    next_state = A;
                out = 0;
            end
            B: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 0;
            end
            C: begin
                if (in)
                    next_state = D;
                else
                    next_state = A;
                out = 0;
            end
            D: begin
                if (in)
                    next_state = B;
                else
                    next_state = C;
                out = 1;
            end
            default: begin
                next_state = A;
                out = 0;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg out
);

	typedef enum reg [1:0] {A, B, C, D} state_t;
	state_t current_state, next_state;

	always @(posedge clk or posedge reset) begin
		if (reset)
			current_state <= A;
		else
			current_state <= next_state;
	end

	always @(*) begin
		case (current_state)
			A: begin
				if (in) next_state = B; else next_state = A;
				out = 0;
			end
			B: begin
				if (in) next_state = B; else next_state = C;
				out = 0;
			end
			C: begin
				if (in) next_state = D; else next_state = A;
				out = 0;
			end
			D: begin
				if (in) next_state = B; else next_state = C;
				out = 1;
			end
			default: begin
				next_state = A;
				out = 0;
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);

    // State encoding
    typedef enum reg [1:0] {
        A = 2'b00,
        B = 2'b01,
        C = 2'b10,
        D = 2'b11
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always @(*) begin
        case (current_state)
            A: next_state = (in == 0) ? A : B;
            B: next_state = (in == 0) ? C : B;
            C: next_state = (in == 0) ? A : D;
            D: next_state = (in == 0) ? C : B;
            default: next_state = A; // default to reset state
        endcase
    end

    // Output logic
    always @(*) begin
        case (current_state)
            A, B, C: out = 0;
            D: out = 1;
            default: out = 0; // default output
        endcase
    end

    // State register with synchronous reset
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg out
);
    typedef enum logic[1:0] {
        A, B, C, D
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= A;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always_comb begin
        case (current_state)
            A: next_state = (in == 0) ? A : B;
            B: next_state = (in == 0) ? C : B;
            C: next_state = (in == 0) ? A : D;
            D: next_state = (in == 0) ? C : B;
            default: next_state = A;
        endcase
    end

    // Output logic
    always_ff @(current_state) begin
        case (current_state)
            A, B, C: out = 0;
            D: out = 1;
            default: out = 0;
        endcase
    end
endmodule


module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);
	always @(*) begin
		case (c)
			4'b0000: q = b;       // c = 0
			4'b0001: q = e;       // c = 1
			4'b0010: q = a;       // c = 2
			4'b0011: q = d;       // c = 3
			default: begin
				if (c >= 4'b0100 && c <= 4'b1001)
					q = 4'b1111;  // For c = 4 to 9
				else
					q = f;         // For c = A to F (not specified, assuming a fixed value)
			end
		endcase
	end
endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);
	always @(*) begin
		case (c)
			4'd0: q = b;
			4'd1: q = e;
			4'd2: q = a;
			4'd3: q = d;
			4'd4: q = 4'hf; // Assuming 'f' relates to the highest input of 'e'
			4'd5: q = 4'hf;
			4'd6: q = 4'hf;
			4'd7: q = 4'hf;
			4'd8: q = 4'hf;
			4'd9: q = 4'hf;
			4'd10: q = 4'hf; // a
			4'd11: q = 4'hf; // b
			4'd12: q = 4'hf; // c
			4'd13: q = 4'hf; // d
			4'd14: q = 4'hf; // e
			4'd15: q = 4'hf; // f
			default: q = 4'hx; // Undefined state
		endcase
	end
endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);

always @(*) begin
	case (c)
		4'd0: q = b;        // when c is 0
		4'd1: q = e;        // when c is 1
		4'd2: q = a;        // when c is 2
		4'd3: q = d;        // when c is 3
		4'd4: q = 4'd15;    // when c is 4
		4'd5: q = 4'd15;    // when c is 5
		4'd6: q = 4'd15;    // when c is 6
		4'd7: q = 4'd15;    // when c is 7
		4'd8: q = 4'd15;    // when c is 8
		4'd9: q = 4'd15;    // when c is 9
		4'd10: q = 4'd15;   // when c is a
		4'd11: q = 4'd15;   // when c is b
		4'd12: q = 4'd15;   // when c is c
		4'd13: q = 4'd15;   // when c is d
		4'd14: q = 4'd15;   // when c is e
		4'd15: q = 4'd15;   // when c is f
		default: q = 4'd0;  // default case
	endcase
end

endmodule

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output reg [3:0] q
);

    always @(*) begin
        case (c)
            4'd0: q = b;
            4'd1: q = e;
            4'd2: q = a;
            4'd3: q = d;
            4'd4: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd5: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd6: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd7: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd8: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd9: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd10: q = 4'b0111; // 'f' is assumed to be 4'd7
            4'd11: q = 4'b0111; // 'f' is assumed to be 4'd7
            default: q = 4'b0000; // fallback case
        endcase
    end

endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);
	always @(*) begin
		case (c)
			4'd0: q = b;
			4'd1: q = e;
			4'd2: q = a;
			4'd3: q = d;
			4'd4: q = 4'hf; // Assuming 'f' means 4'd15 (4'b1111)
			4'd5: q = 4'hf; // Same assumption
			4'd6: q = 4'hf; // Same assumption
			4'd7: q = 4'hf; // Same assumption
			4'd8: q = 4'hf; // Same assumption
			4'd9: q = 4'hf; // Same assumption
			4'd10: q = 4'hf; // Same assumption
			4'd11: q = 4'hf; // Same assumption
			4'd12: q = 4'hf; // Same assumption
			4'd13: q = 4'hf; // Same assumption
			4'd14: q = 4'hf; // Same assumption
			4'd15: q = 4'hf; // Same assumption
			default: q = 4'bx; // Don't care condition
		endcase
	end
endmodule

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output reg [3:0] q
);
    always @* begin
        case (c)
            4'd0: q = b;
            4'd1: q = e;
            4'd2: q = a;
            4'd3: q = d;
            4'd4: q = 4'b0110; // assuming 'f' is 6 as it is consistent from 4 to 9
            4'd5: q = 4'b0110; // same for 5
            4'd6: q = 4'b0110; // same for 6
            4'd7: q = 4'b0110; // same for 7
            4'd8: q = 4'b0110; // same for 8
            4'd9: q = 4'b0110; // same for 9
            4'd10: q = 4'b0110; // when c is 'a'
            4'd11: q = 4'b0110; // when c is 'b'
            4'd12: q = 4'b0110; // when c is 'c'
            4'd13: q = 4'b0110; // when c is 'd'
            4'd14: q = 4'b0110; // when c is 'e'
            4'd15: q = 4'b0110; // when c is 'f'
            default: q = 4'bxxxx; // Unknown case
        endcase
    end
endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);
	always @(*) begin
		case (c)
			4'b0000: q = b;
			4'b0001: q = e;
			4'b0010: q = a;
			4'b0011: q = d;
			4'b0100: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b0101: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b0110: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b0111: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1000: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1001: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1010: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1011: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1100: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1101: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			4'b1110: q = 4'b1111; // Assume 'f' corresponds to 4'b1111
			default: q = 4'b0000; // Default case
		endcase
	end
endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);

always @(*) begin
	case (c)
		4'd0: q = b;
		4'd1: q = e;
		4'd2: q = a;
		4'd3: q = d;
		4'd4: q = 4'hf;
		4'd5: q = 4'hf;
		4'd6: q = 4'hf;
		4'd7: q = 4'hf;
		4'd8: q = 4'hf;
		4'd9: q = 4'hf;
		4'ha: q = 4'hf;
		4'hb: q = 4'hf;
		4'hc: q = 4'hf;
		4'hd: q = 4'hf;
		4'he: q = 4'hf;
		4'hf: q = 4'hf;
		default: q = 4'hx;
	endcase
end

endmodule

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output reg [3:0] q
);

always @(*) begin
    case (c)
        4'd0: q = b;
        4'd1: q = e;
        4'd2: q = a;
        4'd3: q = d;
        4'd4: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd5: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd6: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd7: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd8: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd9: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd10: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd11: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd12: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd13: q = 4'd15; // 4'd15 corresponds to 'f'
        4'd14: q = 4'd15; // 4'd15 corresponds to 'f'
        default: q = 4'd0; // return to default case if c does not match
    endcase
end

endmodule

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);
	always @(*) begin
		case (c)
			4'd0: q = b; // when c is 0
			4'd1: q = e; // when c is 1
			4'd2: q = a; // when c is 2
			4'd3: q = d; // when c is 3
			4'd4: q = 4'd5; // constant 5 for c=4
			4'd5: q = 4'd5; // constant 5 for c=5
			4'd6: q = 4'd5; // constant 5 for c=6
			4'd7: q = 4'd5; // constant 5 for c=7
			4'd8: q = 4'd5; // constant 5 for c=8
			4'd9: q = 4'd5; // constant 5 for c=9
			4'd10: q = 4'd5; // constant 5 for c=10
			4'd11: q = 4'd5; // constant 5 for c=11
			4'd12: q = 4'd5; // constant 5 for c=12
			4'd13: q = 4'd5; // constant 5 for c=13
			4'd14: q = 4'd5; // constant 5 for c=14
			4'd15: q = 4'd5; // constant 5 for c=15
			default: q = 4'd0; // default case
		endcase
	end
endmodule


module top_module (
	input sel,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out
);

	always @(*) begin
		if (sel) begin
			out = b;
		end else begin
			out = a;
		end
	end

endmodule

module top_module (
	input sel,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out
);

	always @* begin
		if (sel)
			out = b;
		else
			out = a;
	end

endmodule

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out
);

    always @(*) begin
        out = (sel) ? b : a;
    end

endmodule

module top_module (
	input sel,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out
);

	always @(*) begin
		if (sel)
			out = b;
		else
			out = a;
	end

endmodule


module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] r;
    wire [2:0] q;

    // Flip-Flop
    always @(posedge clk) begin
        if (L) begin
            Q <= r_in;
        end else begin
            Q <= {Q[1] ^ Q[2], Q[0], Q[2]};
        end
    end

    // Instantiation of submodules
    full_module u1(.r(r), .L(L), .clk(clk), .q(q));
    full_module u2(.r(r), .L(L), .clk(clk), .q(q));
    full_module u3(.r(r), .L(L), .clk(clk), .q(q));

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            q <= {q_in, r_in, q[2]};
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0];
endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] q;
    wire [2:0] r = {r_in, q_in, q[2]};
    wire mux_out;

    // 2-to-1 Multiplexer
    assign mux_out = L ? r : {q[1] ^ q[2], q[0], q[2]};

    // Flip-Flop
    always @(posedge clk) begin
        Q <= mux_out;
        q <= mux_out;
    end
endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    wire [2:0] r;
    wire [2:0] q;

    assign r = {r_in, q_in, r_in};

    always @(posedge clk) begin
        if (L) begin
            Q <= r[0]; // Example connection
        end else begin
            Q <= q[0] ^ q[1]; // Example flip flop logic
        end
    end

    // Instantiate the full_module three times
    full_module u1 (
        .r(r[2:0]),
        .L(L),
        .clk(clk),
        .q(q)
    );

    full_module u2 (
        .r(r[2:0]),
        .L(L),
        .clk(clk),
        .q(q)
    );

    full_module u3 (
        .r(r[2:0]),
        .L(L),
        .clk(clk),
        .q(q)
    );

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] q;
    wire [2:0] r;

    assign r = {r_in, 1'b0, 1'b0}; // Extend r_in to 3 bits

    always @(posedge clk) begin
        if (L) begin
            q <= r;
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0]; // Output the least significant bit of q as Q
endmodule

module top_module(
	input clk,
	input L,
	input q_in,
	input r_in,
	output reg Q);

wire [2:0] r;
wire [2:0] q;

assign r = {r_in, q_in, q_in}; // Preparing inputs for the full_module

// Instantiation of full_module three times
full_module u1 (
    .r(r),
    .L(L),
    .clk(clk),
    .q(q)
);

always @(posedge clk) begin
    Q <= q[0]; // Taking output from the full_module
end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            q <= {q_in, r_in, q[2]};
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0]; // Output the first bit of q

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] r;
    wire [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            r <= {r_in, r[1:0]};
        end else begin
            r <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    generate
        genvar i;
        for (i = 0; i < 3; i = i + 1) begin: ff
            reg Q_temp;
            always @(posedge clk) begin
                if (L) begin
                    Q_temp <= r[i];
                end else begin
                    Q_temp <= q[i];
                end
            end
            assign q[i] = Q_temp;
        end
    endgenerate

    assign Q = q[0]; // Assign output Q to one of the q values

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

reg [2:0] q;
wire [2:0] mux_out;

always @(posedge clk) begin
    if (L) begin
        q <= {r_in, r_in, r_in};
    end else begin
        q <= {q[1] ^ q[2], q[0], q[2]};
    end
end

assign mux_out = L ? {r_in, r_in, r_in} : {q[1] ^ q[2], q[0], q[2]};
assign Q = mux_out[0];

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] r;
    wire [2:0] q;

    always @(*) begin
        r = {r_in, q_in, q}; // stack the inputs to create 'r'
    end

    full_module u1 (
        .r(r),
        .L(L),
        .clk(clk),
        .q(q)
    );

    always @(posedge clk) begin
        Q <= q[0]; // You can decide which output to assign to Q
    end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] q;
    wire [2:0] mux_out;

    // 2-1 multiplexer
    assign mux_out = (L) ? r_in : q;

    // Flip-flop
    always @(posedge clk) begin
        Q <= mux_out[0]; // Use the first bit of mux_out for Q
        q <= mux_out;    // Update q with mux_out
    end

endmodule

module top_module(
	input clk,
	input L,
	input q_in,
	input r_in,
	output reg Q
);

	reg [1:0] mux_out;
	wire d_ff_out;

	// 2-to-1 MUX
	always @(*) begin
		if (L) begin
			mux_out = r_in;
		end else begin
			mux_out = {Q ^ mux_out[1], Q};
		end
	end

	// D Flip-Flop
	always @(posedge clk) begin
		Q <= mux_out[0];
	end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            q <= {q_in, q[1:0]};
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0];

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q);

    reg [2:0] r;
    reg [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            q <= r;
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    always @(posedge clk) begin
        Q <= q[0]; // Assuming Q is assigned from the first bit of q
    end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] r;
    wire [2:0] q;

    // Instantiate the flip-flop
    always @(posedge clk) begin
        if (L) begin
            r <= {r[1:0], r_in};
        end
    end

    // Instantiate 2-to-1 MUX
    always @(posedge clk) begin
        if (L) begin
            Q <= r[0];
        end else begin
            Q <= (q_in) ? q[1] : q[0];
        end
    end

    // Full Module Instantiation (using r as input and Q as output)
    full_module u0 (
        .r(r),
        .L(L),
        .clk(clk),
        .q(q)
    );

    full_module u1 (
        .r(r),
        .L(L),
        .clk(clk),
        .q(q)
    );

    full_module u2 (
        .r(r),
        .L(L),
        .clk(clk),
        .q(q)
    );

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] q_temp;

    always @(posedge clk) begin
        if (L) begin
            q_temp <= {q_in, r_in, q_temp[0]};
        end else begin
            q_temp <= {q_temp[1] ^ q_temp[2], q_temp[0], q_temp[2]};
        end
    end

    assign Q = q_temp[0];

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] r;
    wire [2:0] q;

    always @(posedge clk) begin
        if (L) begin
            r <= {q_in, r[1:0]};
        end else begin
            r <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    always @(posedge clk) begin
        Q <= r[0];
    end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);
    reg [2:0] q;
    wire [2:0] r;

    assign r = {r_in, q_in, 1'b0}; // Assuming r_in is the MSB

    always @(posedge clk) begin
        if (L) begin
            q <= r;
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0];

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] r;
    wire [2:0] q;

    always @(posedge clk) begin
        r <= {r_in, r[2:1]}; // Shift input r_in into the array
        if (L) begin
            q <= r; // Load r into q when L is high
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]}; // Feedback logic
        end
        Q <= q[0]; // Output the least significant bit of q
    end

endmodule

module top_module(
    input clk,
    input L,
    input q_in,
    input r_in,
    output reg Q
);

    reg [2:0] q;
    wire [2:0] r;

    assign r = {r_in, q_in, q[2]}; // Concatenate r_in and q_in to form r

    always @(posedge clk) begin
        if (L) begin
            q <= r;
        end else begin
            q <= {q[1] ^ q[2], q[0], q[2]};
        end
    end

    assign Q = q[0];

endmodule


module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & (out | 32'b0));
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] prev_in;

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            prev_in <= in;
            out <= out | (~in & prev_in);
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & {32{1'b1}} & {in[31:1], 1'b0}); // Capture logic
        end
    end
endmodule

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out);

	always @(posedge clk) begin
		if (reset) begin
			out <= 32'b0;
		end else begin
			out <= out | (~in & (out >> 1)) | (~in & (out >> 0));
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] prev_in;

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (prev_in & ~in); // Capture the falling edge
        end
        prev_in <= in; // Store previous input state
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= (in == 32'b0) ? out : (in & ~out) | out; // Capture falling edge
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

always @(posedge clk) begin
    if (reset) begin
        out <= 32'b0;
    end else begin
        out <= (out | ({32{((in ^ {32{1'b1}}) & in)}} & ~in));
    end
end

endmodule

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out);

	always @(posedge clk) begin
		if (reset) begin
			out <= 32'b0;
		end else begin
			out <= out | (~in & {32{1'b1}}) & (out | (in & {32{1'b0}}));
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | ((in == 0) & (out == 1)); // Capture when input goes from 1 to 0
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | ((in | (out & ~in)) >> 1) & ~in;
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & (out | in)); // Capture the transition from 1 to 0
        end
    end

endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= (in == 32'b0) ? out : (in & ~out);
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out
);

reg [31:0] last_in;

always @(posedge clk) begin
	if (reset) begin
		out <= 32'b0;
	end else begin
		last_in <= in;
		out <= out | (~in & last_in);
	end
end

endmodule

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out);

	always @(posedge clk) begin
		if (reset) begin
			out <= 32'b0;
		end else begin
			out <= out | (~in & (in >> 1));
		end
	end

endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & (in ^ {in[30:0], 1'b0}));
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & (out | in));
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] prev_in;

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
            prev_in <= 32'b0;
        end else begin
            prev_in <= in;
            out <= out | (~in & prev_in);
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out);

    reg [31:0] captured;

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
            captured <= 32'b0;
        end else begin
            captured <= in;
            out <= (captured == 32'b1) ? 32'b1 : out;
            out <= out & ~in; // clear the corresponding bit when it goes from 1 to 0
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

    always @(posedge clk) begin
        if (reset) begin
            out <= 32'b0;
        end else begin
            out <= out | (~in & {32{1'b1}}); // Capture when input transitions from 1 to 0
        end
    end

endmodule

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out
);
	always @(posedge clk) begin
		if (reset) begin
			out <= 32'b0;
		end else begin
			out <= (out | ({32{1'b0}} & (in ^ {1'b0, in[31:1]}))) | (out & ~in);
		end
	end
endmodule


module top_module(
    input clk,
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

module top_module(
	input clk,
	input [7:0] d,
	output reg [7:0] q);

	always @(posedge clk) begin
		q <= d;
	end

endmodule


module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire [8:0] sum; // using an extra bit to capture overflow
    assign sum = {1'b0, a} + {1'b0, b}; // sign-extend for addition
    assign s = sum[7:0]; // take lower 8 bits as the result
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // overflow condition
endmodule

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire [8:0] sum; // 9 bits to accommodate overflow
    assign sum = {1'b0, a} + {1'b0, b}; // Extend to 9 bits and add
    assign s = sum[7:0]; // Lower 8 bits are the sum
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Check for overflow condition
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

	wire signed [8:0] sum; // 9-bit to accommodate overflow
	assign sum = $signed(a) + $signed(b);
	assign s = sum[7:0];
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]);

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
	wire signed [8:0] sum;
	assign sum = $signed(a) + $signed(b);
	assign s = sum[7:0];
	assign overflow = (sum[8] != sum[7]);
endmodule

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire signed [8:0] sum = {1'b0, a} + {1'b0, b};

    assign s = sum[7:0];
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]);
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

	wire [8:0] sum;
	assign sum = {1'b0, a} + {1'b0, b};
	assign s = sum[7:0];
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]);

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

    wire [8:0] sum;
    assign sum = {1'b0, a} + {1'b0, b}; // Extend to 9 bits to capture overflow
    assign s = sum[7:0];
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Check for overflow

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
	wire [8:0] sum;
	assign sum = {1'b0, a} + {1'b0, b}; // 9-bit to detect overflow
	assign s = sum[7:0];
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]);
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
    wire [8:0] sum;
    assign sum = {1'b0, a} + {1'b0, b}; // Extend to 9 bits to check for overflow
    assign s = sum[7:0];
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]);
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
    wire [8:0] sum; // 9 bits to capture overflow
    assign sum = {1'b0, a} + {1'b0, b}; // Extend to 9 bits for overflow checking
    assign s = sum[7:0]; // Result is the lower 8 bits
    assign overflow = (a[7] == b[7]) && (a[7] != s[7]); // Overflow detection
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
    wire signed [8:0] signed_a;
    wire signed [8:0] signed_b;
    wire signed [8:0] signed_s;

    assign signed_a = {a[7], a}; // sign extend a
    assign signed_b = {b[7], b}; // sign extend b
    assign signed_s = signed_a + signed_b;
    assign s = signed_s[7:0]; // lower 8 bits for the sum
    assign overflow = (signed_a[8] == signed_b[8]) && (signed_s[8] != signed_a[8]); // overflow condition

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

	wire [8:0] sum; // 9-bit to capture carry
	assign sum = {1'b0, a} + {1'b0, b}; // Extend to 9 bits for addition
	assign s = sum[7:0]; // 8-bit sum output
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Check for overflow

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

wire signed [8:0] sum;
assign sum = {1'b0, a} + {1'b0, b}; // extend to 9 bits to capture overflow
assign s = sum[7:0]; // lower 8 bits of the sum
assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // overflow condition

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

wire signed [8:0] sum;
assign sum = a + b;
assign s = sum[7:0];
assign overflow = (a[7] == b[7]) && (s[7] != a[7]);

endmodule

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);

    wire signed [8:0] result; // Use 9 bits to capture overflow
    assign result = $signed(a) + $signed(b); // Perform signed addition
    assign s = result[7:0]; // Assign lower 8 bits to s
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Check for overflow

endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
	wire [8:0] sum; // 9-bit to capture overflow
	assign sum = {1'b0, a} + {1'b0, b}; // sign-extend to 9 bits for addition
	assign s = sum[7:0]; // result is the lower 8 bits
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // overflow condition
endmodule

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire [8:0] sum;
    assign sum = {1'b0, a} + {1'b0, b}; // Extend a and b to 9 bits to capture overflow
    assign s = sum[7:0]; // Result is the lower 8 bits
    assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Overflow occurs if the signs of a and b are the same and differ from the sign of the sum
endmodule

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);

	reg [8:0] sum; // 9 bits to hold sum and detect overflow
	assign sum = {1'b0, a} + {1'b0, b}; // Zero extend to 9 bits

	assign s = sum[7:0]; // 8-bit sum
	assign overflow = (a[7] == b[7]) && (s[7] != a[7]); // Overflow condition

endmodule

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    wire signed [8:0] sum; // 9 bits to detect overflow
    assign sum = $signed(a) + $signed(b);
    assign s = sum[7:0];
    assign overflow = (sum[8] != sum[7]); // overflow occurs if sign bit changes
endmodule


module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

assign B3_next = state[9] & 1; // B3 (shift_ena=1) goes to Count
assign S_next = state[0] & d;  // S goes to S1 on d=1
assign S1_next = state[1] & d; // S1 goes to S11 on d=1
assign Count_next = state[8] & done_counting; // Count goes to Wait on done_counting=1
assign Wait_next = state[8] & done_counting & ack; // Wait goes to S on ack=1
assign done = state[8] & done_counting; // done is 1 when in Count and done_counting=1
assign counting = state[8]; // counting is 1 when in Count state
assign shift_ena = state[4] | state[5] | state[6] | state[7]; // B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    // State transitions
    assign S_next = state[0] & d;                  // S --d=1--> S1
    assign S1_next = state[1] & d;                 // S1 --d=1--> S11
    assign Count_next = state[8] & done_counting;  // Count --(done_counting)--> Wait
    assign Wait_next = state[9] & ack;              // Wait --ack=1--> S

    assign B3_next = state[7];                      // B3 --(shift_ena=1)--> Count

    // Output logic
    assign done = state[9];                         // Done output logic: Wait state done
    assign counting = state[8];                     // Counting output logic: Count state
    assign shift_ena = state[7] | state[8];        // Shift enable: B3 or Count state

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    assign B3_next = state[9] && 1'b1; // B3 always goes to Count
    assign S_next = state[0] && (d == 1'b1);
    assign S1_next = state[1] && (d == 1'b1);
    assign Count_next = state[8] && !done_counting;
    assign Wait_next = state[9] && done_counting && (ack == 1'b1);

    assign done = state[9] && done_counting; // done signal set when in Wait and done_counting is high
    assign counting = state[8]; // counting is asserted when in Count state
    assign shift_ena = state[4] || state[5] || state[6] || state[7]; // shift_ena asserted in B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    // State next logic
    wire S = state[0];
    wire S1 = state[1];
    wire S11 = state[2];
    wire S110 = state[3];
    wire B0 = state[4];
    wire B1 = state[5];
    wire B2 = state[6];
    wire B3 = state[7];
    wire Count = state[8];
    wire Wait = state[9];

    assign B3_next = B3 && shift_ena;   // B3 -> Count
    assign S_next = S && ~d;             // S -> S
    assign S1_next = S1 && d;            // S1 -> S1
    assign Count_next = Count && ~done_counting;  // Count -> Count
    assign Wait_next = Wait && (done && ack); // Wait -> S

    // Output logic
    assign done = Wait && ack;          // done logic
    assign counting = Count;            // counting logic
    assign shift_ena = B0 || B1 || B2 || B3; // shift_ena logic

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    assign B3_next = state[8] & 1'b1; // From B3 to Count
    assign S_next = state[0] & (d == 1'b0) | state[1] & (d == 1'b0) | state[2] & (d == 1'b1) | state[3] & (d == 1'b0); // From S or S1 to S
    assign S1_next = state[1] & (d == 1'b1); // From S1 to S11
    assign Count_next = state[8] & ~done_counting; // From Count to Count
    assign Wait_next = state[9] & (done == 1'b1 & ack == 1'b1) | state[9] & (done == 1'b1 & ack == 1'b0); // From Wait to S

    assign done = state[9]; // Output done is high when in Wait state
    assign counting = state[8]; // Output counting is high when in Count state
    assign shift_ena = state[4] | state[5] | state[6] | state[7]; // Shift enabled in B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // Next-state logic
    wire S = state[0];
    wire S1 = state[1];
    wire S11 = state[2];
    wire S110 = state[3];
    wire B0 = state[4];
    wire B1 = state[5];
    wire B2 = state[6];
    wire B3 = state[7];
    wire Count = state[8];
    wire Wait = state[9];

    assign B3_next = B3 & shift_ena;
    assign S_next = S & ~d | S1 & d;
    assign S1_next = S1 & ~d | S11 & d;
    assign Count_next = Count & ~done_counting | done_counting;
    assign Wait_next = Wait & (ack ? 0 : 1);

    // Output logic
    assign done = Wait & ack;
    assign counting = Count;
    assign shift_ena = B0 | B1 | B2 | B3;

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    // Next-state logic
    assign B3_next = (state[3] && shift_ena);
    assign S_next = (state[0] && d);
    assign S1_next = (state[1] && d) || (state[0] && !d);
    assign Count_next = (state[4] && shift_ena) || (state[8] && !done_counting);
    assign Wait_next = (state[8] && done_counting && ack) || (state[9] && ack);

    // Output logic
    assign done = state[9];
    assign counting = state[8];
    assign shift_ena = (state[4] || state[5] || state[6] || state[7]);

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

  // One-hot state encoding
  wire S = state[0];
  wire S1 = state[1];
  wire S11 = state[2];
  wire S110 = state[3];
  wire B0 = state[4];
  wire B1 = state[5];
  wire B2 = state[6];
  wire B3 = state[7];
  wire Count = state[8];
  wire Wait = state[9];

  // Next state logic
  assign S_next = S && d;                   // S -> S1 (d=1)
  assign S1_next = S1 && ~d;                // S1 -> S (d=0)
  assign Count_next = Count && ~done_counting; // Count -> Count (done_counting=0)

  assign B3_next = B3;                     // B3 always go to next cycle
  assign Wait_next = Wait && done;         // Wait remains until ack=1

  // Output logic
  assign done = Wait && ack;              // done=1 when in Wait state and ack=1
  assign counting = Count;                 // counting=1 when in Count state
  assign shift_ena = B0 || B1 || B2 || B3; // shift_ena=1 when in any of B0, B1, B2, B3 states

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

wire S = state[0];
wire S1 = state[1];
wire S11 = state[2];
wire S110 = state[3];
wire B0 = state[4];
wire B1 = state[5];
wire B2 = state[6];
wire B3 = state[7];
wire Count = state[8];
wire Wait = state[9];

// Next State Logic
assign S_next = (S && d) || (S1 && ~d);
assign S1_next = (S && d) || (S11 && ~d);
assign Count_next = (Count && ~done_counting) || (Count && done_counting);
assign Wait_next = (Wait && done && ack) || (Wait && done && ~ack);
assign B3_next = B3; // B3 always transitions to Count when shift_ena is high

// Output Logic
assign done = Wait && done;
assign counting = Count;
assign shift_ena = B0 || B1 || B2 || B3;

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // Next-state logic
    wire S = state[0];
    wire S1 = state[1];
    wire S11 = state[2];
    wire S110 = state[3];
    wire B0 = state[4];
    wire B1 = state[5];
    wire B2 = state[6];
    wire B3 = state[7];
    wire Count = state[8];
    wire Wait = state[9];

    assign B3_next = B3 & (1'b1); // Always go to next cycle
    assign S_next = S & (d == 1'b1 ? S1 : S);
    assign S1_next = S1 & (d == 1'b0 ? S : (d == 1'b1 ? S11 : S1));
    assign Count_next = Count & (!done_counting ? Count : Wait);
    assign Wait_next = Wait & (done ? (ack == 1'b0 ? Wait : S) : Wait);

    // Output logic
    assign done = Wait & ack;
    assign counting = Count;
    assign shift_ena = (B0 | B1 | B2 | B3);

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // State output logic
    assign done = (state[9] == 1'b1); // Wait state
    assign counting = (state[8] == 1'b1); // Count state
    assign shift_ena = (state[4] == 1'b1 || state[5] == 1'b1 || state[6] == 1'b1 || state[7] == 1'b1); // B0 to B3 states

    // Next state logic
    assign S_next = (state[0] == 1'b1 && d == 1'b1) ? 1'b1 : 1'b0;
    assign S1_next = (state[1] == 1'b1 && d == 1'b1) ? 1'b1 : 1'b0;
    assign Count_next = (state[8] == 1'b1 && done_counting == 1'b1) ? 1'b1 : 1'b0;
    assign Wait_next = (state[8] == 1'b1 && done_counting == 1'b1 && ack == 1'b1) ? 1'b1 : 1'b0;
    assign B3_next = (state[7] == 1'b1 && shift_ena == 1'b1) ? 1'b1 : 1'b0;

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    assign B3_next = state[4] & 1'b1;   // From state B3 to Count
    assign S_next = state[0] & ~d;      // From state S to S or S1
    assign S1_next = state[1] & d;      // From state S1 to S11 or S
    assign Count_next = state[8] & ~done_counting;  // From Count to Count or Wait
    assign Wait_next = state[9] & done & ack; // From Wait to S

    assign done = state[9];              // Output done in Wait state
    assign counting = state[8];          // Output counting in Count state
    assign shift_ena = state[4] | state[5] | state[6] | state[7]; // B0 to B3 to Count

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    assign B3_next = state[9] & 1'b1; // B3 always goes to next state
    assign S_next = state[0] & ~d;      // From S to S
    assign S1_next = state[1] & d;      // From S1 to S11
    assign Count_next = state[8] & ~done_counting; // Count remains in Count
    assign Wait_next = state[8] & done_counting & ack; // Goes to S

    assign done = state[8] & done_counting; // done output when in Count and done_counting is high
    assign counting = state[8]; // counting output when in Count state
    assign shift_ena = (state[4] | state[5] | state[6] | state[7]); // shift_ena active in B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

assign B3_next = state[9] & 1; // B3 to Count
assign S_next = state[0] & ~d; // S to S or S to S1
assign S1_next = state[1] & d; // S1 to S11 or S1 to S
assign Count_next = state[8] & ~done_counting; // Count to Count or Count to Wait
assign Wait_next = state[8] & done_counting & (ack ? 1 : 0); // Wait to S

assign done = state[8] & done_counting; // done when in Count and done_counting is high
assign counting = state[8]; // counting is high when in Count state
assign shift_ena = state[4] | state[5] | state[6] | state[7]; // shift_ena high for B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // Next-state logic
    assign S_next = state[0] & d;                     // S -> S1
    assign S1_next = state[1] & ~d;                   // S1 -> S
    assign Count_next = state[8] & (done_counting);   // Count -> Wait
    assign Wait_next = state[9] & ack;                 // Wait -> S
    assign B3_next = state[7];                         // B3 -> Count

    // Output logic
    assign done = state[9];                            // Wait state indicates done
    assign counting = state[8];                        // Count state indicates counting
    assign shift_ena = state[4] | state[5] | state[6] | state[7]; // B0, B1, B2, B3 enable shifting

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // Next-state logic
    wire S = state[0];
    wire S1 = state[1];
    wire S11 = state[2];
    wire S110 = state[3];
    wire B0 = state[4];
    wire B1 = state[5];
    wire B2 = state[6];
    wire B3 = state[7];
    wire Count = state[8];
    wire Wait = state[9];

    assign B3_next = B3 & 1'b1; // Always go to the next cycle
    assign Count_next = Count & ~done_counting; // Stay in Count while not done
    assign S_next = (S & ~d) | (S1 & d) | (S110 & ~d) | (B0 & ack);
    assign S1_next = (S & d) | (S1 & ~d);
    assign Wait_next = (Wait & (done & ack)) | (Count & done_counting);

    // Output logic
    assign done = Wait & 1'b1; // Done when in Wait state
    assign counting = Count & 1'b1; // Counting when in Count state
    assign shift_ena = (B0 | B1 | B2 | B3); // Shift enable when in B0 to B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    assign B3_next = state[9]; // B3 state active

    assign S_next = (state[0] && d) ? 1 : 0; // S to S1 on d=1
    assign S1_next = (state[1] && d) ? 1 : (state[1] && ~d) ? 0 : 0; // S1 to S11 on d=1, back to S on d=0
    assign Count_next = (state[8] && ~done_counting) ? 1 : (state[8] && done_counting) ? 0 : 0; // Count to Count on done_counting=0, to Wait on done_counting=1
    assign Wait_next = (state[9] && ack) ? 1 : (state[9] && ~ack) ? 0 : 0; // Wait to S on ack=1

    assign done = (state[9] && ack); // done output
    assign counting = state[8];      // counting output
    assign shift_ena = state[4] || state[5] || state[6] || state[7]; // B0, B1, B2, B3 active

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );

    // Next state logic
    assign S_next = state[0] & ~d;                 // From S to S
    assign S1_next = state[1] & d;                 // From S to S1
    assign B3_next = state[7] & 1'b1;               // From B3 to next state
    assign Count_next = state[8] & ~done_counting; // From Count to Count
    assign Wait_next = state[9] & done & ack;      // From Wait to S

    // Output logic
    assign done = state[9];                        // Done output active in Wait state
    assign counting = state[8];                    // Counting active in Count state
    assign shift_ena = state[4] | state[5] | state[6] | state[7]; // B0, B1, B2, B3

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

wire S = state[0];
wire S1 = state[1];
wire S11 = state[2];
wire S110 = state[3];
wire B0 = state[4];
wire B1 = state[5];
wire B2 = state[6];
wire B3 = state[7];
wire Count = state[8];
wire Wait = state[9];

// Next-state logic
assign B3_next = B3 & shift_ena;
assign Count_next = Count & ~done_counting;
assign S_next = (S & d) | (S1 & ~d) | (S110 & ~d);
assign S1_next = (S & d) | (S11 & d);
assign Wait_next = Wait & (done & ~ack);

// Output logic
assign done = Wait & done_counting;
assign counting = Count;
assign shift_ena = B0 | B1 | B2 | B3;

endmodule

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
);

    // State assignments
    wire S = state[0];       // 10'b0000000001
    wire S1 = state[1];      // 10'b0000000010
    wire S11 = state[2];     // 10'b0000000100
    wire S110 = state[3];    // 10'b0000001000
    wire B0 = state[4];      // 10'b0000010000
    wire B1 = state[5];      // 10'b0000100000
    wire B2 = state[6];      // 10'b0001000000
    wire B3 = state[7];      // 10'b0010000000
    wire Count = state[8];   // 10'b0100000000
    wire Wait = state[9];    // 10'b1000000000

    // Next-state logic
    assign S_next = (S & ~d) | (S1 & ~d) | (S110 & ~d) | (Wait & ack);
    assign S1_next = (S & d) | (S11 & ~d);
    assign Count_next = (Count & ~done_counting) | (Wait & ack);
    assign Wait_next = (Count & done_counting);
    assign B3_next = (B3); // B3 always goes to the next when shift_ena is asserted

    // Output logic
    assign done = Wait & (ack);
    assign counting = Count;
    assign shift_ena = (B3 || B2 || B1 || B0); // Shift enable when in B0 to B3

endmodule


module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01;
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11)
                    state <= state + 1;
            end else begin
                if (state > 2'b00)
                    state <= state - 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01;
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11) begin
                    state <= state + 1;
                end
            end else begin
                if (state > 2'b00) begin
                    state <= state - 1;
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // Reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11) begin
                    state <= state + 1; // Increment (max 3)
                end
            end else begin
                if (state > 2'b00) begin
                    state <= state - 1; // Decrement (min 0)
                end
            end
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01;
        end else if (train_valid) begin
            if (train_taken && state < 2'b11) begin
                state <= state + 1;
            end else if (!train_taken && state > 2'b00) begin
                state <= state - 1;
            end
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // Reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken && state < 2'b11) begin
                state <= state + 1; // Increment if train_taken is 1 and not max
            end else if (!train_taken && state > 2'b00) begin
                state <= state - 1; // Decrement if train_taken is 0 and not min
            end
        end
    end

endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // Reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11) // Increment if less than 3
                    state <= state + 1;
            end else begin
                if (state > 2'b00) // Decrement if greater than 0
                    state <= state - 1;
            end
        end
    end

endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // reset to weakly not-taken
        end else begin
            if (train_valid) begin
                if (train_taken) begin
                    if (state < 2'b11)
                        state <= state + 1; // increment
                end else begin
                    if (state > 2'b00)
                        state <= state - 1; // decrement
                end
            end
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset)
            state <= 2'b01;
        else if (train_valid) begin
            if (train_taken && state < 2'b11)
                state <= state + 1;
            else if (!train_taken && state > 2'b00)
                state <= state - 1;
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // Asynchronously reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken && state < 2'b11) begin
                state <= state + 1; // Increment, max 3
            end else if (!train_taken && state > 2'b00) begin
                state <= state - 1; // Decrement, min 0
            end
        end
    end
endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);

    always_ff @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // Reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11) begin
                    state <= state + 1; // Increment
                end
            end else begin
                if (state > 2'b00) begin
                    state <= state - 1; // Decrement
                end
            end
        end
    end

endmodule

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            state <= 2'b01; // reset to weakly not-taken
        end else if (train_valid) begin
            if (train_taken) begin
                if (state < 2'b11) begin
                    state <= state + 1; // increment
                end
            end else begin
                if (state > 2'b00) begin
                    state <= state - 1; // decrement
                end
            end
        end
    end

endmodule


module top_module (
	input [7:0] in,
	output reg [2:0] pos
);

always @* begin
	pos = 3'b000; // Default output when no bits are high
	case (in)
		8'b00000000: pos = 3'b000; // No bits high
		8'b00000001: pos = 3'b000; // Bit 0 high
		8'b00000010: pos = 3'b001; // Bit 1 high
		8'b00000100: pos = 3'b010; // Bit 2 high
		8'b00001000: pos = 3'b011; // Bit 3 high
		8'b00010000: pos = 3'b100; // Bit 4 high
		8'b00100000: pos = 3'b101; // Bit 5 high
		8'b01000000: pos = 3'b110; // Bit 6 high
		8'b10000000: pos = 3'b111; // Bit 7 high
		default: begin
			if (in[0]) pos = 3'b000;
			else if (in[1]) pos = 3'b001;
			else if (in[2]) pos = 3'b010;
			else if (in[3]) pos = 3'b011;
			else if (in[4]) pos = 3'b100;
			else if (in[5]) pos = 3'b101;
			else if (in[6]) pos = 3'b110;
			else if (in[7]) pos = 3'b111;
		end
	endcase
end

endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    integer i;

    always @(*) begin
        pos = 3'b0; // Default value if no bits are high
        for (i = 0; i < 8; i = i + 1) begin
            if (in[i] == 1) begin
                pos = i[2:0]; // Report the position of the first high bit
                break;
            end
        end
    end
endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    integer i;

    always @(*) begin
        pos = 3'b000; // Default to zero
        for (i = 0; i < 8; i = i + 1) begin
            if (in[i]) begin
                pos = i[2:0]; // Store the position of the first 1
                break;
            end
        end
    end
endmodule

module top_module (
	input [7:0] in,
	output reg [2:0] pos
);

	always @(*) begin
		pos = 3'b000; // Default to 0 (no bits are high)
		if (in[0]) pos = 3'd0;
		else if (in[1]) pos = 3'd1;
		else if (in[2]) pos = 3'd2;
		else if (in[3]) pos = 3'd3;
		else if (in[4]) pos = 3'd4;
		else if (in[5]) pos = 3'd5;
		else if (in[6]) pos = 3'd6;
		else if (in[7]) pos = 3'd7;
	end

endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    integer i;
    always @* begin
        pos = 3'd0; // Default output is 0
        for (i = 0; i < 8; i = i + 1) begin
            if (in[i]) begin
                pos = i;
                break;
            end
        end
    end
endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    integer i;

    always @(*) begin
        pos = 3'd0; // Default to zero if no bits are high
        for (i = 0; i < 8; i = i + 1) begin
            if (in[i] == 1) begin
                pos = i; // Capture the first (least significant) bit that is high
                break;
            end
        end
    end
endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    always @(*) begin
        pos = 3'd0; // Default to zero if no bits are high
        case (in)
            8'b00000001: pos = 3'd0;
            8'b00000011: pos = 3'd0; // If multiple bits are high, return the least significant
            8'b00000100: pos = 3'd2;
            8'b00000101: pos = 3'd0;
            8'b00001000: pos = 3'd3;
            8'b00001001: pos = 3'd0;
            8'b00010000: pos = 3'd4;
            8'b00010001: pos = 3'd0;
            8'b00100000: pos = 3'd5;
            8'b01000000: pos = 3'd6;
            8'b10000000: pos = 3'd7;
            default: pos = 3'd0; // For any other case
        endcase
    end
endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    integer i;
    always @(*) begin
        pos = 3'b0; // Default output is 0
        for (i = 0; i < 8; i = i + 1) begin
            if (in[i]) begin
                pos = i[2:0]; // Report the position of the first 1
                break;
            end
        end
    end
endmodule

module top_module (
	input [7:0] in,
	output reg [2:0] pos
);
	always @(*) begin
		pos = 3'b000; // Default to zero if no bits are high
		case(in)
			8'b00000001: pos = 3'd0;
			8'b00000010: pos = 3'd1;
			8'b00000100: pos = 3'd2;
			8'b00001000: pos = 3'd3;
			8'b00010000: pos = 3'd4;
			8'b00100000: pos = 3'd5;
			8'b01000000: pos = 3'd6;
			8'b10000000: pos = 3'd7;
			default: pos = pos; // Remain zero if no high bits
		endcase
	end
endmodule

module top_module (
	input [7:0] in,
	output reg [2:0] pos
);

always @(*) begin
	pos = 3'd0; // Default to zero if no bits are high
	for (integer i = 0; i < 8; i = i + 1) begin
		if (in[i]) begin
			pos = i; // Set position to the first high bit
			break; // Exit the loop after finding the first high bit
		end
	end
end

endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    always @(*) begin
        pos = 3'd0; // Default to zero
        for (integer i = 0; i < 8; i = i + 1) begin
            if (in[i]) begin
                pos = i; // Assign position of the first 1
                break; // Exit loop on first match
            end
        end
    end
endmodule

module top_module (
    input [7:0] in,
    output reg [2:0] pos
);
    always @(*) begin
        pos = 3'b000; // Default to zero if no bits are high
        for (integer i = 0; i < 8; i = i + 1) begin
            if (in[i]) begin
                pos = i; // Output the position of the first high bit
                break; // Exit loop once the first high bit is found
            end
        end
    end
endmodule


module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

	always @(*) begin
		// Initialize outputs to 0
		left = 0;
		down = 0;
		right = 0;
		up = 0;

		// Check the scancode for arrow keys
		case (scancode)
			16'hE06B: left = 1;   // Left arrow
			16'hE072: down = 1;   // Down arrow
			16'hE074: right = 1;  // Right arrow
			16'hE075: up = 1;     // Up arrow
			default: ;            // None, outputs remain 0
		endcase
	end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'hE06B: left = 1;
            16'hE072: down = 1;
            16'hE074: right = 1;
            16'hE075: up = 1;
            default: ; // do nothing
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

	always @* begin
		left = 0;
		down = 0;
		right = 0;
		up = 0;

		case (scancode)
			16'hE06B: left = 1;
			16'hE072: down = 1;
			16'hE074: right = 1;
			16'hE075: up = 1;
			default: ;
		endcase
	end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

always @* begin
	left = 0;
	down = 0;
	right = 0;
	up = 0;

	case (scancode)
		16'hE06B: left = 1;
		16'hE072: down = 1;
		16'hE074: right = 1;
		16'hE075: up = 1;
		default: begin
			left = 0;
			down = 0;
			right = 0;
			up = 0;
		end
	endcase
end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Initialize outputs
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        case (scancode)
            16'hE06B: left = 1;  // left arrow
            16'hE072: down = 1;  // down arrow
            16'hE074: right = 1; // right arrow
            16'hE075: up = 1;    // up arrow
            default: ;           // none
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

always @(*) begin
	left = 0;
	down = 0;
	right = 0;
	up = 0;

	case(scancode)
		16'hE06B: left = 1;
		16'hE072: down = 1;
		16'hE074: right = 1;
		16'hE075: up = 1;
		default: begin
			left = 0;
			down = 0;
			right = 0;
			up = 0;
		end
	endcase
end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @* begin
        // Initialize outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check the scancode for arrow key presses
        case (scancode)
            16'hE06B: left = 1;    // Left arrow
            16'hE072: down = 1;    // Down arrow
            16'hE074: right = 1;   // Right arrow
            16'hE075: up = 1;      // Up arrow
            default: ;              // None
        endcase
    end
endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @* begin
        // Initialize outputs to 0
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check for specific scancodes
        case (scancode)
            16'hE06B: left = 1;    // left arrow
            16'hE072: down = 1;    // down arrow
            16'hE074: right = 1;   // right arrow
            16'hE075: up = 1;      // up arrow
            default: ;              // no action for anything else
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

	always @(*) begin
		left = 0;
		down = 0;
		right = 0;
		up = 0;

		case (scancode)
			16'hE06B: left = 1;
			16'hE072: down = 1;
			16'hE074: right = 1;
			16'hE075: up = 1;
			default: ;
		endcase
	end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

always @(*) begin
    // Default output states
    left = 0;
    down = 0;
    right = 0;
    up = 0;

    case (scancode)
        16'hE06B: left = 1;   // Left arrow
        16'hE072: down = 1;   // Down arrow
        16'hE074: right = 1;  // Right arrow
        16'hE075: up = 1;     // Up arrow
        default: ;             // No action for anything else
    endcase
end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

always @(*) begin
    left = 0;
    down = 0;
    right = 0;
    up = 0;

    case (scancode)
        16'hE06B: left = 1;
        16'hE072: down = 1;
        16'hE074: right = 1;
        16'hE075: up = 1;
        default:;
    endcase
end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

always @(*) begin
    left = 0;
    down = 0;
    right = 0;
    up = 0;

    case (scancode)
        16'hE06B: left = 1;  // left arrow
        16'hE072: down = 1;  // down arrow
        16'hE074: right = 1; // right arrow
        16'hE075: up = 1;    // up arrow
        default: ;            // none
    endcase
end

endmodule

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up
);

    always @(*) begin
        // Default outputs to zero
        left = 0;
        down = 0;
        right = 0;
        up = 0;

        // Check the scancode for arrow keys
        case (scancode)
            16'hE06B: left = 1;   // left arrow
            16'hE072: down = 1;   // down arrow
            16'hE074: right = 1;  // right arrow
            16'hE075: up = 1;     // up arrow
            default: ;            // none
        endcase
    end

endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

	always @(*) begin
		left = 0;
		down = 0;
		right = 0;
		up = 0;

		case (scancode)
			16'hE06B: left = 1;
			16'hE072: down = 1;
			16'hE074: right = 1;
			16'hE075: up = 1;
			default: begin
				left = 0;
				down = 0;
				right = 0;
				up = 0;
			end
		endcase
	end
endmodule

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);

always @* begin
	left = 0;
	down = 0;
	right = 0;
	up = 0;

	case (scancode)
		16'hE06B: left = 1;    // left arrow
		16'hE072: down = 1;    // down arrow
		16'hE074: right = 1;   // right arrow
		16'hE075: up = 1;      // up arrow
		default: ;             // none
	endcase
end

endmodule


module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
	wire c1, c2, c3; // carry wires

	// Full adder for bit 0
	assign sum[0] = x[0] ^ y[0];
	assign c1 = x[0] & y[0];

	// Full adder for bit 1
	assign sum[1] = x[1] ^ y[1] ^ c1;
	assign c2 = (x[1] & y[1]) | (c1 & (x[1] ^ y[1]));

	// Full adder for bit 2
	assign sum[2] = x[2] ^ y[2] ^ c2;
	assign c3 = (x[2] & y[2]) | (c2 & (x[2] ^ y[2]));

	// Full adder for bit 3
	assign sum[3] = x[3] ^ y[3] ^ c3;
	assign sum[4] = (x[3] & y[3]) | (c3 & (x[3] ^ y[3]));

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire [3:0] carry;

    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(carry[0])
    );

    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(carry[0]),
        .sum(sum[1]),
        .cout(carry[1])
    );

    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(carry[1]),
        .sum(sum[2]),
        .cout(carry[2])
    );

    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(carry[2]),
        .sum(sum[3]),
        .cout(sum[4])
    );

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	wire c1, c2, c3;
    wire s0, s1, s2, s3;

    // Full adder for the least significant bit
    assign s0 = x[0] ^ y[0];
    assign sum[0] = s0 ^ 0; // No carry in for the LSB
    assign c1 = (x[0] & y[0]) | (s0 & 0);

    // Full adder for the second bit
    assign s1 = x[1] ^ y[1];
    assign sum[1] = s1 ^ c1;
    assign c2 = (x[1] & y[1]) | (s1 & c1);

    // Full adder for the third bit
    assign s2 = x[2] ^ y[2];
    assign sum[2] = s2 ^ c2;
    assign c3 = (x[2] & y[2]) | (s2 & c2);

    // Full adder for the most significant bit
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign sum[4] = (x[3] & y[3]) | (c3 & (x[3] ^ y[3]));

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire [3:0] carry;

    // Full Adder for the Least Significant Bit (LSB)
    assign sum[0] = x[0] ^ y[0];
    assign carry[0] = x[0] & y[0];

    // Full Adder for the second bit
    assign sum[1] = x[1] ^ y[1] ^ carry[0];
    assign carry[1] = (x[1] & y[1]) | (carry[0] & (x[1] ^ y[1]));

    // Full Adder for the third bit
    assign sum[2] = x[2] ^ y[2] ^ carry[1];
    assign carry[2] = (x[2] & y[2]) | (carry[1] & (x[2] ^ y[2]));

    // Full Adder for the Most Significant Bit (MSB)
    assign sum[3] = x[3] ^ y[3] ^ carry[2];
    assign sum[4] = (x[3] & y[3]) | (carry[2] & (x[3] ^ y[3]));

endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
	wire c1, c2, c3; // Carry wires

	full_adder fa0 (.a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum[0]), .cout(c1));
	full_adder fa1 (.a(x[1]), .b(y[1]), .cin(c1), .sum(sum[1]), .cout(c2));
	full_adder fa2 (.a(x[2]), .b(y[2]), .cin(c2), .sum(sum[2]), .cout(c3));
	full_adder fa3 (.a(x[3]), .b(y[3]), .cin(c3), .sum(sum[3]), .cout(sum[4]));

endmodule

module full_adder (
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
	assign sum = a ^ b ^ cin;
	assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	wire c1, c2, c3; // carry wires

	full_adder fa0 (.a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum[0]), .cout(c1));
	full_adder fa1 (.a(x[1]), .b(y[1]), .cin(c1), .sum(sum[1]), .cout(c2));
	full_adder fa2 (.a(x[2]), .b(y[2]), .cin(c2), .sum(sum[2]), .cout(c3));
	full_adder fa3 (.a(x[3]), .b(y[3]), .cin(c3), .sum(sum[3]), .cout(sum[4])); // overflow bit as carry out

endmodule

module full_adder (
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
	assign sum = a ^ b ^ cin;
	assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire [3:0] carry;

    full_adder FA0 (.a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum[0]), .cout(carry[0]));
    full_adder FA1 (.a(x[1]), .b(y[1]), .cin(carry[0]), .sum(sum[1]), .cout(carry[1]));
    full_adder FA2 (.a(x[2]), .b(y[2]), .cin(carry[1]), .sum(sum[2]), .cout(carry[2]));
    full_adder FA3 (.a(x[3]), .b(y[3]), .cin(carry[2]), .sum(sum[3]), .cout(sum[4]));

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire [2:0] carry;

    // Full adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign carry[0] = x[0] & y[0];

    // Full adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ carry[0];
    assign carry[1] = (x[1] & y[1]) | (carry[0] & (x[1] ^ y[1]));

    // Full adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ carry[1];
    assign carry[2] = (x[2] & y[2]) | (carry[1] & (x[2] ^ y[2]));

    // Full adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ carry[2];
    assign sum[4] = (x[3] & y[3]) | (carry[2] & (x[3] ^ y[3]));

endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	wire [3:0] c; // carry bits

	full_adder fa0 (
		.a(x[0]),
		.b(y[0]),
		.c_in(1'b0),
		.sum(sum[0]),
		.c_out(c[0])
	);

	full_adder fa1 (
		.a(x[1]),
		.b(y[1]),
		.c_in(c[0]),
		.sum(sum[1]),
		.c_out(c[1])
	);

	full_adder fa2 (
		.a(x[2]),
		.b(y[2]),
		.c_in(c[1]),
		.sum(sum[2]),
		.c_out(c[2])
	);

	full_adder fa3 (
		.a(x[3]),
		.b(y[3]),
		.c_in(c[2]),
		.sum(sum[3]),
		.c_out(sum[4]) // overflow bit
	);

endmodule

module full_adder (
	input a,
	input b,
	input c_in,
	output sum,
	output c_out
);
	assign sum = a ^ b ^ c_in;
	assign c_out = (a & b) | (c_in & (a ^ b));
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	wire c1, c2, c3;

	full_adder fa0 (
		.a(x[0]),
		.b(y[0]),
		.cin(1'b0),
		.sum(sum[0]),
		.cout(c1)
	);

	full_adder fa1 (
		.a(x[1]),
		.b(y[1]),
		.cin(c1),
		.sum(sum[1]),
		.cout(c2)
	);

	full_adder fa2 (
		.a(x[2]),
		.b(y[2]),
		.cin(c2),
		.sum(sum[2]),
		.cout(c3)
	);

	full_adder fa3 (
		.a(x[3]),
		.b(y[3]),
		.cin(c3),
		.sum(sum[3]),
		.cout(sum[4])
	);

endmodule

module full_adder (
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
	assign sum = a ^ b ^ cin;
	assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);

    wire [3:0] carry;

    // Full Adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign carry[0] = x[0] & y[0];

    // Full Adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ carry[0];
    assign carry[1] = (x[1] & y[1]) | (carry[0] & (x[1] ^ y[1]));

    // Full Adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ carry[1];
    assign carry[2] = (x[2] & y[2]) | (carry[1] & (x[2] ^ y[2]));

    // Full Adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ carry[2];
    assign sum[4] = (x[3] & y[3]) | (carry[2] & (x[3] ^ y[3]));

endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
	wire [3:0] c; // carry bits

	full_adder fa0 (.a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum[0]), .cout(c[0]));
	full_adder fa1 (.a(x[1]), .b(y[1]), .cin(c[0]), .sum(sum[1]), .cout(c[1]));
	full_adder fa2 (.a(x[2]), .b(y[2]), .cin(c[1]), .sum(sum[2]), .cout(c[2]));
	full_adder fa3 (.a(x[3]), .b(y[3]), .cin(c[2]), .sum(sum[3]), .cout(sum[4]));

endmodule

module full_adder(
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
	assign sum = a ^ b ^ cin;
	assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c1, c2, c3; // Carry wires

    // Full adder for bit 0
    assign sum[0] = x[0] ^ y[0];
    assign c1 = x[0] & y[0];

    // Full adder for bit 1
    assign sum[1] = x[1] ^ y[1] ^ c1;
    assign c2 = (x[1] & y[1]) | (c1 & (x[1] ^ y[1]));

    // Full adder for bit 2
    assign sum[2] = x[2] ^ y[2] ^ c2;
    assign c3 = (x[2] & y[2]) | (c2 & (x[2] ^ y[2]));

    // Full adder for bit 3
    assign sum[3] = x[3] ^ y[3] ^ c3;
    assign sum[4] = (x[3] & y[3]) | (c3 & (x[3] ^ y[3]));
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
	wire c1, c2, c3;

	full_adder fa0 (.a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum[0]), .cout(c1));
	full_adder fa1 (.a(x[1]), .b(y[1]), .cin(c1), .sum(sum[1]), .cout(c2));
	full_adder fa2 (.a(x[2]), .b(y[2]), .cin(c2), .sum(sum[2]), .cout(c3));
	full_adder fa3 (.a(x[3]), .b(y[3]), .cin(c3), .sum(sum[3]), .cout(sum[4]));

endmodule

module full_adder (
	input a,
	input b,
	input cin,
	output sum,
	output cout
);
	assign sum = a ^ b ^ cin;
	assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire [3:0] carry;

    // Full adder for the least significant bit
    assign sum[0] = x[0] ^ y[0];
    assign carry[0] = x[0] & y[0];

    // Full adder for the second bit
    assign sum[1] = x[1] ^ y[1] ^ carry[0];
    assign carry[1] = (x[1] & y[1]) | (carry[0] & (x[1] ^ y[1]));

    // Full adder for the third bit
    assign sum[2] = x[2] ^ y[2] ^ carry[1];
    assign carry[2] = (x[2] & y[2]) | (carry[1] & (x[2] ^ y[2]));

    // Full adder for the most significant bit
    assign sum[3] = x[3] ^ y[3] ^ carry[2];
    assign sum[4] = (x[3] & y[3]) | (carry[2] & (x[3] ^ y[3]));

endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire [3:0] carry; // Carry outputs from each full adder

    full_adder fa0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(carry[0])
    );

    full_adder fa1 (
        .a(x[1]),
        .b(y[1]),
        .cin(carry[0]),
        .sum(sum[1]),
        .cout(carry[1])
    );

    full_adder fa2 (
        .a(x[2]),
        .b(y[2]),
        .cin(carry[1]),
        .sum(sum[2]),
        .cout(carry[2])
    );

    full_adder fa3 (
        .a(x[3]),
        .b(y[3]),
        .cin(carry[2]),
        .sum(sum[3]),
        .cout(sum[4]) // Overflow bit
    );

endmodule

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
    assign sum = a ^ b ^ cin;      // Sum equation
    assign cout = (a & b) | (cin & (a ^ b)); // Carry equation
endmodule