module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] current_count;
    reg [2:0] state, next_state;
    reg [19:0] clk_counter;

    localparam IDLE = 3'b000,
               SEARCH = 3'b001,
               LOAD_DELAY = 3'b010,
               COUNTING = 3'b011,
               DONE = 3'b100;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            clk_counter <= 0;
            current_count <= 0;
            delay <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(state or data or current_count or ack) begin
        case (state)
            IDLE: begin
                counting = 0;
                done = 0;
                clk_counter = 0;
                current_count = 0;
                next_state = SEARCH;
            end

            SEARCH: begin
                if (data == 1) begin
                    next_state = LOAD_DELAY;
                end else begin
                    next_state = SEARCH;
                end
            end

            LOAD_DELAY: begin
                next_state = (data == 1) ? COUNTING : LOAD_DELAY;
                if (data == 1) begin
                    delay <= {data, delay[3:1]};
                end
            end

            COUNTING: begin
                counting = 1;
                if (clk_counter < (delay + 1) * 1000) begin
                    if (clk_counter % 1000 == 0) begin
                        current_count = (delay == 0) ? 0 : delay;
                        delay = (delay > 0) ? delay - 1 : 0;
                    end
                    clk_counter <= clk_counter + 1;
                    next_state = COUNTING;
                end else begin
                    done = 1;
                    counting = 0;
                    next_state = DONE;
                end
            end

            DONE: begin
                if (ack) begin
                    next_state = SEARCH;
                end else begin
                    next_state = DONE;
                end
            end

            default: next_state = IDLE;
        endcase
    end

    assign count = (counting) ? current_count : 4'bx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] state;
    reg [9:0] cycle_counter;
    reg [3:0] time_remaining;

    parameter IDLE = 4'b0000, SEARCH = 4'b0001, SHIFT = 4'b0010, COUNT = 4'b0011, DONE = 4'b0100;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'bxxxx; // don't care
            cycle_counter <= 10'd0;
            time_remaining <= 4'd0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    count <= 4'bxxxx; // don't care
                    if (data == 1'b1) state <= SEARCH;
                end
                SEARCH: begin
                    if (data == 1'b1) state <= SHIFT;
                    else if (data == 1'b0) state <= SEARCH;
                end
                SHIFT: begin
                    if (delay === 4'bxxxx) begin // if we haven't loaded shift bits yet
                        delay <= 0; // clear delay for shifting
                    end else if (time_remaining < 4'd4) begin
                        delay <= {delay[2:0], data}; // shift in data
                        time_remaining <= time_remaining + 1'b1;
                        if (time_remaining == 4'd3) begin
                            delay <= delay; // for the last bit, complete it
                            state <= COUNT; // go to count state
                        end
                    end
                end
                COUNT: begin
                    counting <= 1;
                    if (cycle_counter < (delay + 1) * 1000) begin
                        count <= time_remaining;
                        cycle_counter <= cycle_counter + 1'b1;
                        if (cycle_counter % 1000 == 0 && time_remaining > 0)
                            time_remaining <= time_remaining - 1'b1;
                    end else begin
                        state <= DONE; // go to done state
                    end
                end
                DONE: begin
                    counting <= 0;
                    done <= 1;
                    count <= 4'bxxxx; // don't care
                    if (ack) begin
                        state <= IDLE; // reset and look for next sequence
                        cycle_counter <= 10'd0; // reset counter
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] current_delay;
    reg [11:0] counter; // for counting up to (delay + 1) * 1000
    reg [2:0] state;

    localparam IDLE = 3'b000,
               DETECT = 3'b001,
               SHIFT = 3'b010,
               COUNT = 3'b011,
               DONE = 3'b100;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            count <= 4'b0000;
            counting <= 0;
            done <= 0;
            current_delay <= 4'b0000;
            counter <= 12'b000000000000;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    if ({data, state[1:0]} == 3'b101) begin
                        state <= DETECT;
                    end
                end

                DETECT: begin
                    if (data) begin
                        if (state == 1) begin
                            state <= SHIFT;
                        end
                    end else begin
                        state <= IDLE;
                    end
                end

                SHIFT: begin
                    if (current_delay < 4'd4) begin
                        delay[current_delay] <= data;
                        current_delay <= current_delay + 1;
                    end else begin
                        state <= COUNT;
                        current_delay <= 0;
                        counter <= (delay + 1) * 1000 - 1;
                    end
                end

                COUNT: begin
                    counting <= 1;
                    if (counter == 0) begin
                        state <= DONE;
                        done <= 1;
                    end else begin
                        if (counter == 1000) begin
                            count <= delay;
                            delay <= delay - 1;
                            counter <= 999; // Reset counter for 1000 cycles
                        end
                        counter <= counter - 1;
                    end
                end

                DONE: begin
                    counting <= 0;
                    if (ack) begin
                        state <= IDLE;
                        done <= 0;
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

    reg [3:0] delay;
    reg [3:0] cycle_count;
    reg [2:0] state;
    reg [2:0] next_state;

    localparam IDLE = 3'd0, PATTERN = 3'd1, SHIFT_DELAY = 3'd2, COUNTING = 3'd3, DONE = 3'd4;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'bxxxx;
        end else begin
            state <= next_state;
            if (next_state == COUNTING) begin
                if (cycle_count > 0) begin
                    cycle_count <= cycle_count - 1;
                end else begin
                    if (delay > 0) begin
                        delay <= delay - 1;
                        cycle_count <= 1000;
                    end else begin
                        done <= 1;
                        counting <= 0;
                    end
                end
            end else if (next_state == DONE && ack) begin
                done <= 0;
                count <= 4'bxxxx;
            end
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            pattern_recognized <= 0;
            delay <= 0;
            cycle_count <= 1000; // Initial delay for the first countdown
        end else begin
            case (state)
                IDLE: begin
                    done <= 0;
                    counting <= 0;
                    if (data == 1 && state < 3) // first bit
                        state <= PATTERN;
                end
                PATTERN: begin
                    // Detect 1101 pattern
                    if (data == 1 && state == 1)
                        state <= 2;
                    else if (data == 1 && state == 2)
                        state <= 3;
                    else if (data == 0 && state == 3)
                        state <= 4;
                    else if (data == 1 && state == 4) begin
                        pattern_recognized <= 1;
                        state <= SHIFT_DELAY;
                    end
                end
                SHIFT_DELAY: begin
                    delay <= {delay[2:0], data};
                    if (count == 3) begin
                        cycle_count <= (delay + 1) * 1000;
                        next_state <= COUNTING;
                    end
                end
                COUNTING: begin
                    counting <= 1;
                    count <= delay;
                end
                DONE: begin
                    if (ack) begin
                        next_state <= IDLE;
                    end
                end
            endcase
        end
    end

    always @(*) begin
        case (state)
            IDLE: next_state = (data == 1) ? PATTERN : IDLE;
            PATTERN: next_state = (pattern_recognized) ? SHIFT_DELAY : PATTERN;
            SHIFT_DELAY: next_state = (count == 3) ? COUNTING : SHIFT_DELAY;
            COUNTING: next_state = (done) ? DONE : COUNTING;
            DONE: next_state = (ack) ? IDLE : DONE;
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module(
	input wire clk,
	input wire reset,
	input wire data,
	output reg [3:0] count,
	output reg counting,
	output reg done,
	input wire ack );

	reg [3:0] delay;
	reg [3:0] state;
	reg [12:0] cycle_count;
	localparam IDLE = 4'b0000,
	           SEARCH = 4'b0001,
	           DELAY_LOAD = 4'b0010,
	           COUNTING = 4'b0011,
	           NOTIFY = 4'b0100;

	always @(posedge clk) begin
		if (reset) begin
			state <= IDLE;
			count <= 4'b0000;
			counting <= 1'b0;
			done <= 1'b0;
			cycle_count <= 13'b0;
		end else begin
			case (state)
				IDLE: begin
					if (data == 1'b1) begin
						state <= SEARCH;
						cycle_count <= 13'b0;
					end
				end

				SEARCH: begin
					if (cycle_count < 13'd3) begin
						if (data == 1'b1) begin
							cycle_count <= cycle_count + 1;
						end else begin
							state <= IDLE;
							cycle_count <= 13'b0;
						end
					end else if (data == 1'b0) begin
						state <= DELAY_LOAD;
						cycle_count <= 13'b0;
					end
				end

				DELAY_LOAD: begin
					delay[3] <= data;
					cycle_count <= cycle_count + 1;
					if (cycle_count == 4) begin
						state <= COUNTING;
						counting <= 1'b1;
						count <= delay;
						cycle_count <= 0;
					end
				end

				COUNTING: begin
					cycle_count <= cycle_count + 1;
					if (cycle_count == 1000) begin
						if (count > 0) begin
							count <= count - 1;
							cycle_count <= 0;
						end else begin
							state <= NOTIFY;
							done <= 1'b1;
							counting <= 1'b0;
						end
					end
				end

				NOTIFY: begin
					if (ack) begin
						state <= IDLE;
						done <= 1'b0;
					end
				end
			endcase
		end
	end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] state;
    reg [9:0] counter;
    reg [2:0] bit_count;
    reg [1:0] current_delay;

    localparam IDLE = 2'b00,
               WAIT_PATTERN = 2'b01,
               SHIFT_DELAY = 2'b10,
               COUNTING = 2'b11;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 0;
            counter <= 0;
            bit_count <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    bit_count <= 0;
                    if (data == 1'b1) state <= WAIT_PATTERN;
                end

                WAIT_PATTERN: begin
                    if (bit_count < 3) begin
                        if (data == (3 - bit_count)) // Check for 1101
                            bit_count <= bit_count + 1;
                        else
                            state <= IDLE; // Reset if pattern is wrong
                    end else begin
                        bit_count <= 0;
                        state <= SHIFT_DELAY;
                    end
                end

                SHIFT_DELAY: begin
                    if (bit_count < 4) begin
                        delay[3 - bit_count] <= data;
                        bit_count <= bit_count + 1;
                    end else begin
                        current_delay <= delay;
                        counting <= 1;
                        counter <= 0;
                        state <= COUNTING;
                    end
                end

                COUNTING: begin
                    if (counter < (current_delay + 1) * 1000) begin
                        counter <= counter + 1;
                        if (counter % 1000 == 0) begin
                            if (current_delay > 0) begin
                                count <= current_delay;
                                current_delay <= current_delay - 1;
                            end else begin
                                count <= 0;
                            end
                        end
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= IDLE;
                    end
                end

                default: state <= IDLE;
            endcase

            if (done && ack) begin
                done <= 0;
                state <= IDLE;
            end
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] state;
    reg [3:0] remaining_time;
    reg [9:0] cycle_count;

    localparam IDLE = 0, SEARCH = 1, LOAD_DELAY = 2, COUNTING = 3, DONE = 4;

    always @(posedge clk) begin
        if (reset) begin
            state <= SEARCH;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            cycle_count <= 10'd0;
            remaining_time <= 4'b0000;
        end else begin
            case (state)
                SEARCH: begin
                    if (data == 1'b1) begin
                        state <= SEARCH_1;
                    end
                end
                SEARCH_1: begin
                    if (data == 1'b1) begin
                        state <= SEARCH_11;
                    end else begin
                        state <= SEARCH; // reset to SEARCH if pattern breaks
                    end
                end
                SEARCH_11: begin
                    if (data == 1'b0) begin
                        state <= SEARCH_110;
                    end else begin
                        state <= SEARCH; // reset to SEARCH if pattern breaks
                    end
                end
                SEARCH_110: begin
                    if (data == 1'b1) begin
                        state <= LOAD_DELAY; // valid pattern detected
                    end else begin
                        state <= SEARCH; // reset to SEARCH if pattern breaks
                    end
                end
                LOAD_DELAY: begin
                    delay <= {data, delay[3:1]}; // shift in the next bit
                    if (delay == 4'b1111) begin
                        state <= COUNTING;
                        remaining_time <= delay;
                        cycle_count <= 10'd0;
                    end
                end
                COUNTING: begin
                    if (cycle_count < (delay + 1) * 10'd1000) begin
                        if (cycle_count % 10'd1000 == 0) begin
                            if (remaining_time > 0) begin
                                remaining_time <= remaining_time - 4'b0001;
                            end
                        end
                        cycle_count <= cycle_count + 10'd1;
                    end else begin
                        done <= 1;
                        counting <= 0;
                        state <= DONE;
                    end
                end
                DONE: begin
                    count <= 4'b0000; // don't care output
                    if (ack) begin
                        done <= 0;
                        state <= SEARCH;
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

    reg [3:0] delay;
    reg [3:0] state;
    reg [3:0] timer_count;
    reg [3:0] remaining_time;
    reg [3:0] seq_detected;

    localparam IDLE = 4'b0000;
    localparam PATTERN = 4'b0001;
    localparam SHIFT = 4'b0010;
    localparam COUNTING = 4'b0011;
    localparam DONE = 4'b0100;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            count <= 4'd0;
            counting <= 0;
            done <= 0;
            timer_count <= 4'd0;
            seq_detected <= 4'd0;
            remaining_time <= 4'd0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    seq_detected <= {seq_detected[2:0], data};
                    if (seq_detected == 4'b1101) begin
                        state <= SHIFT;
                        seq_detected <= 4'd0; // reset seq_detected once detected
                    end
                end

                SHIFT: begin
                    if (timer_count < 4) begin
                        delay <= {delay[2:0], data}; // shift in the next bit
                        timer_count <= timer_count + 1;
                    end else begin
                        remaining_time <= delay;
                        state <= COUNTING;
                        counting <= 1;
                        timer_count <= 4'd0;
                    end
                end

                COUNTING: begin
                    if (remaining_time > 0) begin
                        count <= remaining_time;
                        timer_count <= timer_count + 1;
                        if (timer_count == 1000 - 1) begin
                            remaining_time <= remaining_time - 1;
                            timer_count <= 0;
                        end
                    end else if (timer_count < 1000) begin
                        count <= 4'd0;
                        timer_count <= timer_count + 1;
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= DONE;
                        count <= 4'd0; // Reset count when done
                    end
                end

                DONE: begin
                    if (ack) begin
                        state <= IDLE;
                        delay <= 4'd0; // Reset delay
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [1:0] state, next_state;
    reg [3:0] delay;
    reg [9:0] cycle_counter;
    reg [3:0] remaining_time;

    localparam SEARCH = 2'b00;
    localparam SHIFT = 2'b01;
    localparam COUNT = 2'b10;
    localparam DONE = 2'b11;

    always @(posedge clk) begin
        if (reset) begin
            state <= SEARCH;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            cycle_counter <= 0;
            remaining_time <= 0;
        end else begin
            state <= next_state;
            if (counting) begin
                if (cycle_counter < 999) begin
                    cycle_counter <= cycle_counter + 1;
                end else begin
                    cycle_counter <= 0;
                    if (remaining_time > 0) begin
                        remaining_time <= remaining_time - 1;
                    end else begin
                        counting <= 0;
                        done <= 1;
                    end
                end
            end
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            SEARCH: begin
                counting = 0;
                done = 0;
                if ({data, 1'b0} == 4'b1101) begin
                    next_state = SHIFT;
                end
            end
            SHIFT: begin
                if (cycle_counter < 3) begin
                    next_state = SHIFT;
                end else begin
                    next_state = COUNT;
                    delay = {data, 3'b000}; // shifting in next 4 bits
                    remaining_time = delay;
                    counting = 1;
                end
            end
            COUNT: begin
                counting = 1;
                remaining_time = (remaining_time == 0) ? delay : remaining_time;
                if (remaining_time == 0) begin
                    next_state = DONE;
                end
            end
            DONE: begin
                counting = 0;
                if (ack) begin
                    next_state = SEARCH;
                end
            end
        endcase
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] count_reg;
    reg [2:0] state, next_state;
    reg [3:0] cycle_counter;
    parameter IDLE = 3'b000, SEARCH = 3'b001, LOAD_DELAY = 3'b010, COUNT = 3'b011, DONE_STATE = 3'b100;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count_reg <= 4'bxxxx; // Don't-care
            cycle_counter <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            IDLE: begin
                counting = 0;
                done = 0;
                count_reg = 4'bxxxx; // Don't-care
                if (data == 1'b1)
                    next_state = SEARCH;
            end
            SEARCH: begin
                if (data == 1'b1) // Detect first 1
                    next_state = LOAD_DELAY;
                else
                    next_state = SEARCH;
            end
            LOAD_DELAY: begin
                counting = 0;
                if (cycle_counter < 4) begin
                    count_reg[3-cycle_counter] = data; // Shift in delay
                    cycle_counter = cycle_counter + 1;
                    next_state = LOAD_DELAY;
                end else begin
                    delay = count_reg;
                    cycle_counter = 0;
                    if (delay > 0)
                        next_state = COUNT;
                    else
                        next_state = DONE_STATE;
                end
            end
            COUNT: begin
                counting = 1;
                done = 0;
                count_reg = delay;
                if (cycle_counter < (delay + 1) * 1000) begin
                    // Counting logic
                    if (cycle_counter % 1000 == 0) begin
                        if (count_reg > 0)
                            count_reg = count_reg - 1;
                    end
                    cycle_counter = cycle_counter + 1;
                    next_state = COUNT;
                end else begin
                    counting = 0;
                    done = 1;
                    next_state = DONE_STATE;
                end
            end
            DONE_STATE: begin
                counting = 0;
                count_reg = 4'bxxxx; // Don't-care
                if (ack) begin
                    next_state = IDLE; // Return to IDLE to search again
                end else begin
                    next_state = DONE_STATE;
                end
            end
            default: next_state = IDLE;
        endcase
    end

    assign count = counting ? count_reg : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [2:0] state, next_state;
    reg [3:0] delay;
    reg [9:0] cycle_counter;
    reg [3:0] remaining_time;
    parameter IDLE = 3'b000, WAIT_PATTERN = 3'b001, SHIFT_DELAY = 3'b010, COUNTING = 3'b011, DONE = 3'b100;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            cycle_counter <= 0;
            remaining_time <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(state or data or cycle_counter or ack) begin
        next_state = state;
        case (state)
            IDLE: begin
                counting = 0;
                done = 0;
                if (data) begin
                    next_state = WAIT_PATTERN;
                end
            end
            WAIT_PATTERN: begin
                if (cycle_counter < 3) begin
                    if (data == 1'b1) cycle_counter = cycle_counter + 1;
                    if (cycle_counter == 3 && data == 1'b0) begin
                        next_state = SHIFT_DELAY;
                        cycle_counter = 0;
                    end
                end
            end
            SHIFT_DELAY: begin
                if (cycle_counter < 4) begin
                    delay[3-cycle_counter] = data;
                    cycle_counter = cycle_counter + 1;
                end else begin
                    next_state = COUNTING;
                    cycle_counter = 0;
                    remaining_time = delay; // Initialize remaining time
                end
            end
            COUNTING: begin
                counting = 1;
                if (cycle_counter < (remaining_time + 1) * 1000) begin
                    cycle_counter = cycle_counter + 1;
                    if (cycle_counter % 1000 == 0) begin
                        if (remaining_time > 0) remaining_time = remaining_time - 1;
                    end
                end else begin
                    done = 1;
                    counting = 0;
                    next_state = DONE;
                end
            end
            DONE: begin
                if (ack) begin
                    next_state = IDLE;
                    cycle_counter = 0;
                    delay = 0;
                    remaining_time = 0;
                end
            end
        endcase
    end

    assign count = (state == COUNTING) ? remaining_time : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] state;

    localparam IDLE = 4'd0;
    localparam DETECT = 4'd1;
    localparam SHIFT_DELAY = 4'd2;
    localparam COUNTING = 4'd3;
    localparam DONE = 4'd4;

    reg [9:0] cycle_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'bxxxx;
            cycle_count <= 0;
            delay <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    count <= 4'bxxxx;
                    if (data == 1 && cycle_count == 0) begin
                        if (shift_pattern()) begin
                            state <= SHIFT_DELAY;
                            cycle_count <= 0;
                        end
                    end
                end
                SHIFT_DELAY: begin
                    if (cycle_count < 4) begin
                        if (shift_in_delay()) begin
                            cycle_count <= cycle_count + 1;
                        end
                    end else begin
                        state <= COUNTING;
                        counting <= 1;
                        count <= delay;
                        cycle_count <= 0;
                    end
                end
                COUNTING: begin
                    if (cycle_count < (delay + 1) * 1000) begin
                        if (cycle_count < 1000) begin
                            count <= delay;
                        end else if (cycle_count < 2000) begin
                            count <= delay - 1;
                        end else if (cycle_count < 3000) begin
                            count <= delay - 2;
                        end else begin
                            count <= delay - 3;
                        end
                        cycle_count <= cycle_count + 1;
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= DONE;
                        count <= 4'bxxxx;
                    end
                end
                DONE: begin
                    if (ack) begin
                        state <= IDLE;
                        done <= 0;
                    end
                end
            endcase
        end
    end

    function shift_pattern;
        input;
        // Shift logic to detect pattern 1101
        // (Implement the actual logic required for detection)
    endfunction

    function shift_in_delay;
        input;
        // Logic to shift in the next 4 bits to determine delay
        // (Implement the actual logic required for shifting)
    endfunction

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] state;
    reg [3:0] remaining_time;
    reg [3:0] cycle_counter;
    reg [9:0] timer_count;

    parameter IDLE = 0, DETECT = 1, SHIFT = 2, COUNT = 3, COMPLETE = 4;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            remaining_time <= 4'b0000;
            timer_count <= 0;
            cycle_counter <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    if (data == 1'b1)
                        state <= DETECT;
                end

                DETECT: begin
                    // Check for the pattern 1101
                    if (data == 1 && state[2] == 0)
                        state[2] <= 1; // first
                    else if (data == 1 && state[1] == 0)
                        state[1] <= 1; // second
                    else if (data == 0 && state[0] == 1)
                        state[0] <= 0; // third
                    else if (data == 1 && state[0] == 0) begin
                        state <= SHIFT;
                        state[2:0] <= 3'b000; // Reset counter after detection
                    end
                end

                SHIFT: begin
                    if (remaining_time < 4) begin // Shift in 4 bits
                        delay <= {delay[2:0], data};
                        remaining_time <= remaining_time + 1;
                    end else begin
                        count <= delay;
                        remaining_time <= delay;
                        counting <= 1;
                        state <= COUNT;
                        timer_count <= 0;
                    end
                end

                COUNT: begin
                    if (timer_count < (remaining_time + 1) * 1000) begin
                        if (cycle_counter < 1000) begin
                            cycle_counter <= cycle_counter + 1;
                        end else begin
                            cycle_counter <= 0;
                            remaining_time <= remaining_time - 1;
                            if (remaining_time == 0)
                                done <= 1;
                        end
                        timer_count <= timer_count + 1;
                    end else begin
                        counting <= 0;
                        cycle_counter <= 0;
                        state <= COMPLETE;
                    end
                end

                COMPLETE: begin
                    if (ack) begin
                        done <= 0;
                        remaining_time <= 0;
                        delay <= 0;
                        state <= IDLE;
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] current_count;
    reg [3:0] state;
    reg [3:0] bit_counter;
    reg [3:0] count_out;
    reg [3:0] next_count;

    localparam IDLE = 4'b0000;
    localparam READING_PATTERN = 4'b0001;
    localparam SHIFT_DELAY = 4'b0010;
    localparam COUNTING = 4'b0011;
    localparam DONE = 4'b0100;

    // State Machine
    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            current_count <= 0;
            bit_counter <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    if (data == 1'b1) begin
                        state <= READING_PATTERN;
                    end
                end

                READING_PATTERN: begin
                    if (bit_counter < 4) begin
                        if (bit_counter == 0 && data == 1'b1) begin
                            bit_counter <= 1;
                        end else if (bit_counter == 1 && data == 1'b1) begin
                            bit_counter <= 2;
                        end else if (bit_counter == 2 && data == 1'b0) begin
                            bit_counter <= 3;
                        end else if (bit_counter == 3 && data == 1'b1) begin
                            bit_counter <= 4;
                            state <= SHIFT_DELAY;
                        end else begin
                            bit_counter <= 0; // reset if pattern not matched
                        end
                    end
                end

                SHIFT_DELAY: begin
                    if (bit_counter < 8) begin
                        delay[3 - (bit_counter - 4)] <= data;
                        bit_counter <= bit_counter + 1;
                    end else begin
                        counting <= 1;
                        current_count <= (delay + 1) * 1000; // Calculate counts
                        count_out <= delay; // Start with the delay value
                        state <= COUNTING;
                        bit_counter <= 0; // Reset after reading delay
                    end
                end

                COUNTING: begin
                    if (current_count > 0) begin
                        current_count <= current_count - 1;
                        if (current_count % 1000 == 0) begin
                            if (count_out > 0)
                                count_out <= count_out - 1;
                        end
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= DONE;
                    end
                end

                DONE: begin
                    if (ack) begin
                        done <= 0;
                        state <= IDLE; // Reset state machine to start searching again
                        bit_counter <= 0; // Reset bit counter
                    end
                end
            endcase
        end
    end

    assign count = counting ? count_out : 4'bx; // Output count during counting only

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

    reg [3:0] delay;
    reg [3:0] count_reg;
    reg [3:0] state;
    reg [3:0] next_state;

    parameter IDLE = 4'b0000;
    parameter WAIT_PATTERN = 4'b0001;
    parameter SHIFT_DELAY = 4'b0010;
    parameter COUNTING = 4'b0011;
    parameter DONE = 4'b0100;

    reg [2:0] bit_index;
    reg [9:0] cycle_count;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count_reg <= 4'b0000;
            cycle_count <= 0;
            bit_index <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    if (data == 1 && bit_index == 0) begin
                        state <= WAIT_PATTERN;
                    end
                end
                WAIT_PATTERN: begin
                    if (data == 1 && bit_index == 0) begin
                        bit_index <= 1;
                    end else if (data == 1 && bit_index == 1) begin
                        bit_index <= 2;
                    end else if (data == 0 && bit_index == 2) begin
                        bit_index <= 3;
                    end else if (data == 1 && bit_index == 3) begin
                        bit_index <= 0;
                        state <= SHIFT_DELAY;
                    end else if (data != 1) begin
                        bit_index <= 0;
                    end
                end
                SHIFT_DELAY: begin
                    if (cycle_count < 4) begin
                        delay[3-bit_index] <= data;
                        bit_index <= bit_index + 1;
                        cycle_count <= cycle_count + 1;
                    end else begin
                        cycle_count <= 0;
                        count_reg <= delay;
                        counting <= 1;
                        state <= COUNTING;
                    end
                end
                COUNTING: begin
                    if (cycle_count < 1000) begin
                        cycle_count <= cycle_count + 1;
                    end else begin
                        if (count_reg > 0) begin
                            count_reg <= count_reg - 1;
                        end else begin
                            counting <= 0;
                            done <= 1;
                            state <= DONE;
                        end
                        cycle_count <= 0;
                    end
                end
                DONE: begin
                    if (ack) begin
                        state <= IDLE;
                        counting <= 0;
                        done <= 0;
                        count_reg <= 4'b0000;
                    end
                end
            endcase
        end
    end

    assign count = counting ? count_reg : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] current_count;
    reg [2:0] state;

    localparam IDLE = 3'b000;
    localparam READING = 3'b001;
    localparam COUNTING = 3'b010;
    localparam DONE = 3'b011;

    reg [3:0] sequence;
    reg [9:0] cycle_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            current_count <= 4'b0000;
            cycle_count <= 10'b0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    count <= 4'b0000;
                    sequence = {sequence[2:0], data};

                    if (sequence == 4'b1101) begin
                        state <= READING;
                    end
                end

                READING: begin
                    if (cycle_count < 4) begin
                        delay[3 - cycle_count] <= data;
                        cycle_count <= cycle_count + 1;
                    end else begin
                        counting <= 1;
                        current_count <= delay;
                        cycle_count <= 0;
                        state <= COUNTING;
                    end
                end

                COUNTING: begin
                    if (cycle_count < 1000) begin
                        count <= current_count;
                        cycle_count <= cycle_count + 1;
                    end else begin
                        if (current_count > 0) begin
                            current_count <= current_count - 1;
                        end else begin
                            done <= 1;
                            counting <= 0;
                            state <= DONE;
                        end
                        cycle_count <= 0;
                    end
                end

                DONE: begin
                    count <= 4'bxxxx; // Don't care value when done
                    if (ack) begin
                        state <= IDLE;
                        sequence <= 4'b0;
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [3:0] delay;
    reg [3:0] bit_count;
    reg [3:0] current_count;
    reg [3:0] remaining_time;
    reg [1:0] state;

    localparam IDLE = 2'b00, GET_DELAY = 2'b01, COUNTING = 2'b10, DONE = 2'b11;

    always @(posedge clk) begin
        if (reset) begin
            state <= IDLE;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            current_count <= 0;
            bit_count <= 0;
        end else begin
            case (state)
                IDLE: begin
                    counting <= 0;
                    done <= 0;
                    count <= 4'b0000;
                    if (bit_count == 3) begin
                        if (data == 1) bit_count <= bit_count + 1;
                    end else if (bit_count == 2) begin
                        if (data == 1) bit_count <= bit_count + 1;
                        else bit_count <= 0;
                    end else if (bit_count == 1) begin
                        if (data == 0) bit_count <= bit_count + 1;
                        else bit_count <= 0;
                    end else if (bit_count == 0) begin
                        if (data == 1) bit_count <= bit_count + 1;
                    end

                    if (bit_count == 4) begin
                        state <= GET_DELAY;
                        bit_count <= 0;
                    end
                end

                GET_DELAY: begin
                    if (bit_count < 4) begin
                        delay[3-bit_count] <= data;
                        bit_count <= bit_count + 1;
                    end else begin
                        state <= COUNTING;
                        remaining_time <= delay + 1; // Set to delay + 1 for counting
                        current_count <= 0;
                        counting <= 1;
                    end
                end

                COUNTING: begin
                    if (current_count < (delay + 1) * 1000) begin
                        count <= remaining_time;
                        if (current_count % 1000 == 0) begin
                            if (remaining_time > 0) remaining_time <= remaining_time - 1; // Decrement remaining time
                        end
                        current_count <= current_count + 1;
                    end else begin
                        state <= DONE;
                        done <= 1;
                        counting <= 0;
                    end
                end

                DONE: begin
                    count <= 4'bxxxx; // Don't care
                    if (ack) begin
                        state <= IDLE; // Wait for ack to reset
                    end
                end
            endcase
        end
    end

endmodule

module top_module(
	input wire clk,
	input wire reset,
	input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );

	reg [3:0] delay;
	reg [3:0] current_count;
	reg [2:0] state, next_state;
	reg [3:0] remaining_time;

	parameter IDLE = 3'b000, SEARCH = 3'b001, SHIFT_DELAY = 3'b010, COUNTING = 3'b011, DONE = 3'b100;

	always @(posedge clk) begin
		if (reset) begin
			state <= IDLE;
			counting <= 0;
			done <= 0;
			current_count <= 0;
		end else begin
			state <= next_state;
			if (state == COUNTING) begin
				if (current_count < 999) begin
					current_count <= current_count + 1;
				end else begin
					remaining_time <= (remaining_time == 0) ? delay : remaining_time - 1;
					if (remaining_time == 0) begin
						done <= 1;
					end
					current_count <= 0;
				end
			end else begin
				current_count <= 0;
			end
		end
	end

	always @(*) begin
		case (state)
			IDLE: begin
				counting = 0;
				done = 0;
				if (data == 1) next_state = SEARCH; else next_state = IDLE;
			end
			SEARCH: begin
				counting = 0;
				if (data == 0) next_state = (data) ? SHIFT_DELAY : SEARCH;
				else next_state = SEARCH; // Continue searching
			end
			SHIFT_DELAY: begin
				counting = 0;
				if (current_count < 3) begin // Shift in 4 bits
					delay[3 - current_count] = data;
					current_count = current_count + 1;
					next_state = SHIFT_DELAY;
				end else begin
					remaining_time = delay;
					counting = 1;
					next_state = COUNTING;
				end
			end
			COUNTING: begin
				counting = 1;
				if (remaining_time == 0) begin
					next_state = DONE;
				end else begin
					next_state = COUNTING;
				end
			end
			DONE: begin
				counting = 0;
				if (ack) begin
					done = 0;
					next_state = IDLE;
				end else begin
					next_state = DONE;
				end
			end
			default: next_state = IDLE;
		endcase
	end

	assign count = (counting) ? remaining_time : 4'bxxxx;

endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);
    reg [3:0] delay;
    reg [3:0] state;
    reg [9:0] cycle_count;
    reg [3:0] remaining_time;
    reg [3:0] next_state;

    parameter WAIT_FOR_PATTERN = 0,
              SHIFT_IN_DELAY = 1,
              COUNTING = 2,
              DONE = 3;

    initial begin
        state = WAIT_FOR_PATTERN;
        counting = 0;
        done = 0;
        count = 4'b0000;
        cycle_count = 0;
        remaining_time = 0;
    end

    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT_FOR_PATTERN;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            cycle_count <= 0;
            remaining_time <= 0;
        end else begin
            case (state)
                WAIT_FOR_PATTERN: begin
                    counting <= 0;
                    done <= 0;
                    count <= 4'b0000;
                    if ({data, last_data} == 2'b11 && last_data == 1'b0 && data == 1'b1) begin
                        state <= SHIFT_IN_DELAY;
                    end
                    last_data <= data;
                end

                SHIFT_IN_DELAY: begin
                    if (delay < 4'b1111) begin
                        delay <= {delay[2:0], data};
                    end else begin
                        state <= COUNTING;
                        remaining_time <= delay;
                        cycle_count <= (delay + 1) * 1000 - 1;
                        counting <= 1;
                    end
                end

                COUNTING: begin
                    if (cycle_count > 0) begin
                        cycle_count <= cycle_count - 1;
                        if (cycle_count % 1000 == 0) begin
                            remaining_time <= remaining_time - 1;
                            count <= remaining_time;
                        end
                    end else begin
                        counting <= 0;
                        done <= 1;
                        state <= DONE;
                    end
                end

                DONE: begin
                    if (ack) begin
                        state <= WAIT_FOR_PATTERN;
                        done <= 0;
                        count <= 4'bxxxx;
                    end
                end
            endcase
        end
    end
endmodule

module top_module(
    input wire clk,
    input wire reset,
    input wire data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input wire ack
);

    reg [1:0] state, next_state;
    reg [3:0] delay;
    reg [9:0] cycle_count;
    reg [3:0] remaining_time;

    parameter WAIT = 2'b00, PATTERN = 2'b01, SHIFT = 2'b10, COUNT = 2'b11;
    parameter PATTERN_BITS = 4'b1101;

    always @(posedge clk) begin
        if (reset) begin
            state <= WAIT;
            counting <= 0;
            done <= 0;
            count <= 4'b0000;
            cycle_count <= 0;
            remaining_time <= 0;
        end else begin
            state <= next_state;
            if (state == COUNT) begin
                cycle_count <= cycle_count + 1;
                if (cycle_count == 1000) begin
                    cycle_count <= 0;
                    if (remaining_time > 0) begin
                        remaining_time <= remaining_time - 1;
                    end
                end
                if (remaining_time == 0) begin
                    counting <= 0;
                    done <= 1;
                end
            end
        end
    end

    always @(*) begin
        next_state = state;
        case (state)
            WAIT: begin
                counting = 0;
                done = 0;
                if (data == PATTERN[3]) begin
                    next_state = PATTERN;
                end
            end
            PATTERN: begin
                if (data == PATTERN[2]) begin
                    next_state = SHIFT;
                end else begin
                    next_state = WAIT;
                end
            end
            SHIFT: begin
                if (counting == 0) begin
                    delay = {data, delay[3:1]};
                    if (delay == 4'b1111) begin
                        remaining_time = delay;
                        counting = 1;
                        next_state = COUNT;
                    end else begin
                        next_state = WAIT;
                    end
                end
            end
            COUNT: begin
                counting = 1;
                if (done && ack) begin
                    next_state = WAIT;
                end
            end
        endcase
    end

    always @(posedge clk) begin
        if (state == COUNT) begin
            count <= remaining_time;
        end else begin
            count <= 4'bxxxx; // Don't care value when not counting
        end
    end

endmodule


module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

    typedef enum reg [1:0] {
        LOW,       // Below s[1]
        BETWEEN_12, // Between s[2] and s[1]
        BETWEEN_23, // Between s[3] and s[2]
        HIGH       // Above s[3]
    } state_t;

    state_t state, next_state;
    reg [3:1] last_s;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW;
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
            last_s <= 3'b000;
        end else begin
            state <= next_state;
            last_s <= s;
        end
    end

    always @(*) begin
        case (state)
            LOW: begin
                if (s[1]) next_state = BETWEEN_12;
                else if (s[2]) next_state = BETWEEN_23;
                else if (s[3]) next_state = HIGH;
                else next_state = LOW;
            end

            BETWEEN_12: begin
                if (s[1]) next_state = BETWEEN_12;
                else if (s[2]) next_state = BETWEEN_23;
                else if (s[3]) next_state = HIGH;
                else next_state = LOW;
            end

            BETWEEN_23: begin
                if (s[3]) next_state = HIGH;
                else if (s[2]) next_state = BETWEEN_23;
                else if (s[1]) next_state = BETWEEN_12;
                else next_state = LOW;
            end

            HIGH: begin
                next_state = HIGH;
            end

            default: next_state = LOW;
        endcase
    end

    always @(posedge clk) begin
        case (state)
            LOW: begin
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= 0;
            end

            BETWEEN_12: begin
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= (last_s < s) ? 1 : 0; // Increase flow if the level has risen
            end

            BETWEEN_23: begin
                fr3 <= 0;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= (last_s < s) ? 1 : 0; // Increase flow if the level has risen
            end

            HIGH: begin
                fr3 <= 0;
                fr2 <= 0;
                fr1 <= 0;
                dfr <= 0; // No flow allowed above highest sensor
            end

            default: begin
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    reg [1:0] prev_state; // 0: lower, 1: middle, 2: upper
    reg [1:0] current_state; // 0: None, 1: s[1], 2: s[2], 3: s[3]

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
            current_state <= 0; // reset state to below s[1]
            prev_state <= 0;
        end else begin
            prev_state <= current_state;

            if (s[3]) begin
                // Above s[3]
                fr3 <= 0;
                fr2 <= 0;
                fr1 <= 0;
                dfr <= 0;
                current_state <= 3;
            end else if (s[2]) begin
                // Between s[3] and s[2]
                fr3 <= 0;
                fr2 <= 0;
                fr1 <= 1;
                dfr <= (prev_state < 3) ? 1 : 0; // If previous level was lower
                current_state <= 2;
            end else if (s[1]) begin
                // Between s[2] and s[1]
                fr3 <= 0;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= (prev_state < 2) ? 1 : 0; // If previous level was lower
                current_state <= 1;
            end else begin
                // Below s[1]
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= 1; // Maximum flow
                current_state <= 0;
            end
        end
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);
    reg [1:0] state, next_state;
    reg [3:1] prev_s;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= 2'b00; // Reset state
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
            prev_s <= 3'b000;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        case (state)
            2'b00: begin // Below s[1]
                if (s[1] == 0) begin // No sensors
                    fr3 = 1;
                    fr2 = 1;
                    fr1 = 1;
                    dfr = 0;
                end else begin
                    next_state = 2'b01; // Go to between s[2] and s[1]
                end
            end
            2'b01: begin // Between s[2] and s[1]
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1; // Assuming we're increasing flow rate
                next_state = 2'b10; // Go to between s[3] and s[2]
            end
            2'b10: begin // Between s[3] and s[2]
                fr3 = 1;
                fr2 = 1;
                fr1 = 0;
                dfr = (prev_s < s) ? 1 : 0; // Check if we need to increase flow rate
                next_state = 2'b11; // Go to above s[3]
            end
            2'b11: begin // Above s[3]
                fr3 = 0;
                fr2 = 0;
                fr1 = 0;
                dfr = 0;
                next_state = (s[1] == 0) ? 2'b00 : 2'b11; // Check if we need to go back down
            end
        endcase
    end

    always @(s) begin
        prev_s = s; // Store previous sensor state
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

reg [1:0] state; // State to keep track of the last sensor change
reg last_state; // To keep track of the previous sensor state

always @(posedge clk or posedge reset) begin
    if (reset) begin
        fr3 <= 1;
        fr2 <= 1;
        fr1 <= 1;
        dfr <= 0;
        state <= 2'b00;
        last_state <= 1'b0;
    end else begin
        case (s)
            3'b111: begin // Above s[3]
                fr3 <= 0;
                fr2 <= 0;
                fr1 <= 0;
                dfr <= 0;
                state <= 2'b00; // No sensors
            end
            3'b110: begin // Between s[3] and s[2]
                fr3 <= 0;
                fr2 <= 0;
                fr1 <= 1;
                dfr <= (last_state < s[3]) ? 1 : 0;
                state <= 2'b01; // Current state indicates change
            end
            3'b100: begin // Between s[2] and s[1]
                fr3 <= 0;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= (last_state < s[2]) ? 1 : 0;
                state <= 2'b10; // Current state indicates change
            end
            3'b000: begin // Below s[1]
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= 1;
                state <= 2'b11; // All valves open
            end
            default: begin
                fr3 <= 1;
                fr2 <= 1;
                fr1 <= 1;
                dfr <= 0;
                state <= 2'b00; // Default to no sensors
            end
        endcase
        last_state <= s; // Update last_state
    end
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] current_level, previous_level;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
		current_level <= 2'b00; // Below s[1]
		previous_level <= 2'b00;
	end else begin
		previous_level <= current_level;

		// Determine the current water level based on sensors
		if (s[3]) begin
			current_level <= 2'b11; // Above s[3]
			fr3 <= 0;
			fr2 <= 0;
			fr1 <= 0;
			dfr <= 0;
		end else if (s[2]) begin
			current_level <= 2'b10; // Between s[3] and s[2]
			fr3 <= 0;
			fr2 <= 0;
			fr1 <= 1;
			dfr <= (previous_level < 2'b10) ? 1 : 0;
		end else if (s[1]) begin
			current_level <= 2'b01; // Between s[2] and s[1]
			fr3 <= 0;
			fr2 <= 1;
			fr1 <= 1;
			dfr <= (previous_level < 2'b01) ? 1 : 0;
		end else begin
			current_level <= 2'b00; // Below s[1]
			fr3 <= 1;
			fr2 <= 1;
			fr1 <= 1;
			dfr <= 1;
		end
	end
end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    reg [1:0] state, next_state;
    parameter STATE_LOW = 2'b00;
    parameter STATE_MEDIUM1 = 2'b01;
    parameter STATE_MEDIUM2 = 2'b10;
    parameter STATE_HIGH = 2'b11;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= STATE_LOW;
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;

        case (state)
            STATE_LOW: begin
                if (s[1] == 1) begin
                    next_state = STATE_MEDIUM2;
                    fr1 = 1;
                    fr2 = 1;
                    fr3 = 1;
                    dfr = 1;
                end
            end

            STATE_MEDIUM2: begin
                if (s[2] == 1) begin
                    next_state = STATE_MEDIUM1;
                    fr1 = 1;
                    fr2 = 1;
                    dfr = 1;
                end else if (s[3] == 1) begin
                    next_state = STATE_HIGH;
                end
            end

            STATE_MEDIUM1: begin
                if (s[3] == 1) begin
                    next_state = STATE_HIGH;
                end else begin
                    fr1 = 1;
                    fr2 = 1;
                end
            end

            STATE_HIGH: begin
                fr3 = 0;
                fr2 = 0;
                fr1 = 0;
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    typedef enum reg [1:0] {
        LOW_LEVEL,       // Below s[1]
        INTERMEDIATE,    // Between s[2] and s[3]
        HIGH_LEVEL,      // Between s[3] and s[2]
        ABOVE_MAX        // Above s[3]
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW_LEVEL;
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 1;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;
        case (state)
            LOW_LEVEL: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                dfr = 1;
                if (s[1]) begin
                    next_state = INTERMEDIATE;
                end else if (s[2]) begin
                    next_state = INTERMEDIATE;
                end else if (s[3]) begin
                    next_state = HIGH_LEVEL;
                end else begin
                    next_state = LOW_LEVEL;
                end
            end

            INTERMEDIATE: begin
                if (s[1]) begin
                    fr1 = 1;
                end
                if (s[2]) begin
                    fr2 = 1;
                end
                next_state = (s[1]) ? HIGH_LEVEL : LOW_LEVEL;
            end

            HIGH_LEVEL: begin
                fr1 = 1;
                if (s[3]) begin
                    next_state = ABOVE_MAX;
                end else if (s[2]) begin
                    next_state = INTERMEDIATE;
                end else begin
                    next_state = LOW_LEVEL;
                end
            end

            ABOVE_MAX: begin
                fr3 = 0;
                fr2 = 0;
                fr1 = 0;
                dfr = 0;
                next_state = (s[3]) ? ABOVE_MAX : INTERMEDIATE;
            end

            default: begin
                next_state = LOW_LEVEL;
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] state, next_state;
parameter IDLE = 2'b00, HIGH = 2'b01, MID = 2'b10, LOW = 2'b11;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= LOW;
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	next_state = state;

	case (state)
		LOW: begin
			if (s[1] && !s[2] && !s[3]) begin
				next_state = MID;
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end else if (s[2] && !s[3]) begin
				next_state = HIGH;
				fr3 = 1;
				fr2 = 0;
				fr1 = 1;
				dfr = 0;
			end else if (s[3]) begin
				next_state = HIGH;
				fr3 = 0;
				fr2 = 0;
				fr1 = 1;
				dfr = 0;
			end else begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end
		end
		HIGH: begin
			if (s[3]) begin
				fr3 = 0;
				fr2 = 0;
				fr1 = 0;
				dfr = 0;
			end else if (s[2]) begin
				fr3 = 1;
				fr2 = 0;
				fr1 = 1;
				dfr = 0;
			end else if (s[1]) begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end else begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end
		end
		MID: begin
			if (s[1]) begin
				next_state = LOW;
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end else if (s[2]) begin
				next_state = HIGH;
				fr3 = 1;
				fr2 = 0;
				fr1 = 1;
				dfr = 0;
			end else if (s[3]) begin
				fr3 = 0;
				fr2 = 0;
				fr1 = 1;
				dfr = 1;
			end else begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end
		end
	endcase
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] state, next_state;

	// State encoding
	parameter LOW = 2'b00;    // Below s[1]
	parameter MID_LOW = 2'b01; // Between s[2] and s[1]
	parameter MID_HIGH = 2'b10; // Between s[3] and s[2]
	parameter HIGH = 2'b11;    // Above s[3]

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= LOW; // Reset to LOW state
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		case (state)
			LOW: begin
				if (s[1] == 1'b0) begin
					next_state = LOW;
					{fr3, fr2, fr1, dfr} = 4'b1111; // All flow opened
				end else begin
					next_state = MID_LOW;
				end
			end
			MID_LOW: begin
				if (s[2]) begin
					next_state = MID_HIGH;
					{fr3, fr2, fr1, dfr} = 4'b1101; // fr1, fr2 opened
				end else if (s[1] == 1'b0) begin
					next_state = LOW;
					{fr3, fr2, fr1, dfr} = 4'b1111; // All flow opened
				end else begin
					next_state = MID_LOW;
					{fr3, fr2, fr1, dfr} = 4'b1100; // fr1 opened
				end
			end
			MID_HIGH: begin
				if (s[3]) begin
					next_state = HIGH;
					{fr3, fr2, fr1, dfr} = 4'b1000; // No flow
				end else if (s[2] == 1'b0) begin
					next_state = MID_LOW;
					{fr3, fr2, fr1, dfr} = 4'b1101; // fr1, fr2 opened
				end else begin
					next_state = MID_HIGH;
					{fr3, fr2, fr1, dfr} = 4'b1100; // fr1 opened
				end
			end
			HIGH: begin
				next_state = HIGH; // Remain in HIGH
				{fr3, fr2, fr1, dfr} = 4'b1000; // No flow
			end
			default: begin
				next_state = LOW;
				{fr3, fr2, fr1, dfr} = 4'b1111; // All flow opened
			end
		endcase
	end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] state, next_state;
parameter LOW = 2'b00, MID1 = 2'b01, MID2 = 2'b10, HIGH = 2'b11;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= LOW;
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	case (state)
		LOW: begin
			if (s[1]) next_state = MID2;
			else if (s[2]) next_state = MID1;
			else if (s[3]) next_state = HIGH;
			else next_state = LOW;
			fr3 = 1; fr2 = 1; fr1 = 1; dfr = 0;
		end
		MID2: begin
			if (s[1]) next_state = MID2;
			else if (s[2]) next_state = MID1;
			else if (s[3]) next_state = HIGH;
			else next_state = LOW;
			fr3 = 0; fr2 = 1; fr1 = 1; dfr = 0;
		end
		MID1: begin
			if (s[1]) next_state = MID2;
			else if (s[2]) next_state = MID1;
			else if (s[3]) next_state = HIGH;
			else next_state = LOW;
			fr3 = 0; fr2 = 0; fr1 = 1; dfr = 1; // Supplemental flow added
		end
		HIGH: begin
			if (s[1]) next_state = MID2;
			else if (s[2]) next_state = MID1;
			else if (s[3]) next_state = HIGH;
			else next_state = LOW;
			fr3 = 0; fr2 = 0; fr1 = 0; dfr = 0;
		end
		default: begin
			next_state = LOW;
			fr3 = 1; fr2 = 1; fr1 = 1; dfr = 0;
		end
	endcase
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] state, next_state;
reg previous_sensor_state;

parameter STATE_LOW = 2'b00;
parameter STATE_MEDIUM = 2'b01;
parameter STATE_HIGH = 2'b10;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= STATE_LOW;
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
		previous_sensor_state <= 0;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	dfr = 0;
	fr3 = 0;
	fr2 = 0;
	fr1 = 0;

	case(state)
		STATE_LOW: begin
			if (s[1] == 0 && s[2] == 0 && s[3] == 0) begin
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
			end
			next_state = (s[1] ? STATE_MEDIUM : STATE_LOW);
		end
		STATE_MEDIUM: begin
			if (s[2]) begin
				fr2 = 1;
				fr1 = 1;
				next_state = STATE_HIGH;
			end else if (s[1]) begin
				fr1 = 1;
				next_state = STATE_LOW;
			end else begin
				next_state = STATE_LOW;
			end
			if (previous_sensor_state < s) dfr = 1;
			previous_sensor_state = s;
		end
		STATE_HIGH: begin
			if (s[3]) begin
				next_state = STATE_LOW;
			end else begin
				fr1 = 1;
				fr2 = 1;
				next_state = STATE_MEDIUM;
			end
			if (previous_sensor_state < s) dfr = 1;
			previous_sensor_state = s;
		end
	endcase
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] current_state, next_state;
reg [1:0] last_sensor;

localparam STATE_LOW = 2'b00, STATE_MID1 = 2'b01, STATE_MID2 = 2'b10, STATE_HIGH = 2'b11;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		current_state <= STATE_LOW;
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
	end else begin
		current_state <= next_state;
	end
end

always @(*) begin
	next_state = current_state;
	fr3 = 0;
	fr2 = 0;
	fr1 = 0;
	dfr = 0;

	case (current_state)
		STATE_LOW: begin
			if (s[1] == 1'b0 && s[2] == 1'b0 && s[3] == 1'b0) begin
				next_state = STATE_LOW;
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end else begin
				if (s[1]) begin
					next_state = STATE_MID2;
				end else if (s[2]) begin
					next_state = STATE_MID1;
				end else if (s[3]) begin
					next_state = STATE_HIGH;
				end
			end
		end

		STATE_MID1: begin
			next_state = STATE_MID1;
			fr1 = 1;
			fr2 = 1;
			dfr = (last_sensor < 2'b01) ? 1 : 0; // Allow supplemental flow if last was low.
			if (s[2] == 0) next_state = STATE_LOW;
			if (s[3] == 1) next_state = STATE_HIGH;
		end

		STATE_MID2: begin
			next_state = STATE_MID2;
			fr1 = 1;
			fr2 = 0;
			dfr = (last_sensor < 2'b10) ? 1 : 0; // Allow supplemental flow if last was mid1.
			if (s[1] == 0) next_state = STATE_LOW;
			if (s[2] == 1) next_state = STATE_MID1;
			if (s[3] == 1) next_state = STATE_HIGH;
		end

		STATE_HIGH: begin
			next_state = STATE_HIGH;
			fr1 = 0;
			fr2 = 0;
			dfr = 0; // No supplemental flow above high level.
			if (s[3] == 0) next_state = STATE_MID2;
		end
	endcase

	last_sensor = s[1:2]; // Update the last sensor state.
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] state, next_state;

	parameter LOW = 2'b00, MEDIUM = 2'b01, HIGH = 2'b10, RESET = 2'b11;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= RESET;
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		case (state)
			LOW: begin
				if (s[1] == 1'b1) next_state = MEDIUM;
				else next_state = LOW;
				fr3 = 1'b1;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b0;
			end

			MEDIUM: begin
				if (s[2] == 1'b1) next_state = HIGH;
				else next_state = LOW;
				fr3 = 1'b0;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b1;
			end

			HIGH: begin
				if (s[3] == 1'b1) next_state = LOW;
				else next_state = MEDIUM;
				fr3 = 1'b0;
				fr2 = 1'b0;
				fr1 = 1'b1;
				dfr = 1'b1;
			end

			RESET: begin
				next_state = LOW;
				fr3 = 1'b1;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b0;
			end

			default: begin
				next_state = LOW;
				fr3 = 1'b0;
				fr2 = 1'b0;
				fr1 = 1'b0;
				dfr = 1'b0;
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    reg [1:0] state, prev_state;
    parameter LOW = 2'b00, MID1 = 2'b01, MID2 = 2'b10, HIGH = 2'b11;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
            state <= LOW;
        end else begin
            prev_state <= state;
            case (state)
                LOW: begin
                    if (s[1] == 1) begin
                        state <= MID2;
                    end
                end
                MID2: begin
                    if (s[2] == 1) begin
                        state <= HIGH;
                    end else if (s[1] == 0) begin
                        state <= LOW;
                    end
                end
                HIGH: begin
                    if (s[3] == 1) begin
                        state <= HIGH;
                    end else if (s[2] == 1) begin
                        state <= MID2;
                    end
                end
            endcase

            case (state)
                LOW: begin
                    fr3 <= 1;
                    fr2 <= 1;
                    fr1 <= 1;
                    dfr <= 1;
                end
                MID2: begin
                    fr3 <= 1;
                    fr2 <= 1;
                    fr1 <= 0;
                    dfr <= (prev_state == LOW) ? 0 : 1;
                end
                HIGH: begin
                    fr3 <= 0;
                    fr2 <= 0;
                    fr1 <= 1;
                    dfr <= (prev_state == MID2) ? 1 : 0;
                end
            endcase
        end
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);

    // State encoding
    typedef enum reg [1:0] {
        LOW = 2'b00,
        LOW_TO_MED = 2'b01,
        MEDIUM = 2'b10,
        MED_TO_HIGH = 2'b11,
        HIGH = 2'b100
    } state_t;

    state_t state, next_state;
    reg [3:1] prev_s;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= LOW;
            fr3 <= 1;
            fr2 <= 1;
            fr1 <= 1;
            dfr <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        // Default output assignments
        fr3 = 0;
        fr2 = 0;
        fr1 = 0;
        dfr = 0;

        case (state)
            LOW: begin
                if (s[1] == 0 && s[2] == 0 && s[3] == 0) begin
                    fr3 = 1;
                    fr2 = 1;
                    fr1 = 1;
                end
                next_state = LOW;
            end

            LOW_TO_MED: begin
                fr3 = 1;
                fr2 = 1;
                fr1 = 1;
                next_state = (s[1] == 1) ? MEDIUM : LOW_TO_MED;
            end

            MEDIUM: begin
                fr1 = 1;
                fr2 = 1;
                next_state = (s[2] == 1) ? MED_TO_HIGH : LOW_TO_MED;
            end

            MED_TO_HIGH: begin
                fr1 = 1;
                fr2 = 1;
                dfr = 1;
                next_state = (s[3] == 1) ? HIGH : MED_TO_HIGH;
            end

            HIGH: begin
                next_state = HIGH;
            end

            default: next_state = LOW;
        endcase
    end

    always @(s or prev_s) begin
        if (prev_s < s) dfr = 1;
        prev_s = s;
    end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] state, next_state;
	parameter S0 = 2'b00; // Below s[1]
	parameter S1 = 2'b01; // Between s[2] and s[1]
	parameter S2 = 2'b10; // Between s[3] and s[2]
	parameter S3 = 2'b11; // Above s[3]

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= S0;
			fr3 <= 1'b1;
			fr2 <= 1'b1;
			fr1 <= 1'b1;
			dfr <= 1'b0;
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		case (state)
			S0: begin
				if (s[1] == 1'b1) begin
					next_state = S1;
				end else begin
					next_state = S0;
				end
			end

			S1: begin
				if (s[2] == 1'b1) begin
					next_state = S2;
				end else if (s[1] == 1'b0) begin
					next_state = S0;
				end else begin
					next_state = S1;
				end
			end

			S2: begin
				if (s[3] == 1'b1) begin
					next_state = S3;
				end else if (s[2] == 1'b0) begin
					next_state = S1;
				end else begin
					next_state = S2;
				end
			end

			S3: begin
				if (s[3] == 1'b0) begin
					next_state = S2;
				end else begin
					next_state = S3;
				end
			end

			default: next_state = S0;
		endcase
	end

	always @(*) begin
		{fr3, fr2, fr1, dfr} = 4'b0000; // Default output
		case (state)
			S0: begin
				fr3 = 1'b1;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b1; // Supplemental flow valve opened
			end
			S1: begin
				fr3 = 1'b0;
				fr2 = 1'b0;
				fr1 = 1'b1;
				dfr = 1'b0; // No increase
			end
			S2: begin
				fr3 = 1'b0;
				fr2 = 1'b1;
				fr1 = 1'b1;
				dfr = 1'b0; // No increase
			end
			S3: begin
				fr3 = 1'b0;
				fr2 = 1'b0;
				fr1 = 1'b0;
				dfr = 1'b0; // No increase
			end
		endcase
	end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] state, next_state;
localparam BELOW_S1 = 2'b00, BETWEEN_S2_S1 = 2'b01, BETWEEN_S3_S2 = 2'b10, ABOVE_S3 = 2'b11;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= BELOW_S1;
		fr3 <= 1;
		fr2 <= 1;
		fr1 <= 1;
		dfr <= 0;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	case(state)
		BELOW_S1: begin
			fr3 = 1;
			fr2 = 1;
			fr1 = 1;
			dfr = 0;
			if (s[1] || s[2] || s[3]) next_state = BETWEEN_S2_S1;
			else next_state = BELOW_S1;
		end

		BETWEEN_S2_S1: begin
			fr3 = 0;
			fr2 = 1;
			fr1 = 1;
			dfr = 0;
			if (s[2] && !s[3]) next_state = BETWEEN_S3_S2;
			else if (s[3]) next_state = ABOVE_S3;
			else if (!s[1]) next_state = BELOW_S1;
			else next_state = BETWEEN_S2_S1;
		end

		BETWEEN_S3_S2: begin
			fr3 = 0;
			fr2 = 0;
			fr1 = 1;
			dfr = 0;
			if (s[3]) next_state = ABOVE_S3;
			else if (!s[2]) next_state = BETWEEN_S2_S1;
			else next_state = BETWEEN_S3_S2;
		end

		ABOVE_S3: begin
			fr3 = 0;
			fr2 = 0;
			fr1 = 0;
			dfr = 0;
			if (!s[3]) next_state = BETWEEN_S3_S2;
			else next_state = ABOVE_S3;
		end

		default: begin
			fr3 = 1;
			fr2 = 1;
			fr1 = 1;
			dfr = 0;
			next_state = BELOW_S1;
		end
	endcase

	if (state < next_state) dfr = 1;
	else dfr = 0;
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] state, next_state;
	parameter LOW = 2'b00, INTERMEDIATE = 2'b01, HIGH = 2'b10;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= LOW;
			fr3 <= 1;
			fr2 <= 1;
			fr1 <= 1;
			dfr <= 0;
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		case (state)
			LOW: begin
				if (s[1]) begin
					next_state = INTERMEDIATE;
				end else begin
					next_state = LOW;
				end
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end

			INTERMEDIATE: begin
				if (s[2]) begin
					next_state = HIGH;
				end else if (!s[1]) begin
					next_state = LOW;
				end else begin
					next_state = INTERMEDIATE;
				end
				fr3 = 0;
				fr2 = 0;
				fr1 = 1;
				dfr = 1;
			end

			HIGH: begin
				if (s[3]) begin
					next_state = HIGH;
				end else if (s[2]) begin
					next_state = INTERMEDIATE;
				end else begin
					next_state = LOW;
				end
				fr3 = 0;
				fr2 = 1;
				fr1 = 1;
				dfr = 1;
			end

			default: begin
				next_state = LOW;
				fr3 = 1;
				fr2 = 1;
				fr1 = 1;
				dfr = 0;
			end
		endcase
	end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

reg [1:0] state, next_state;
reg [1:0] prev_level; // 0: below s[1], 1: at s[1], 2: at s[2], 3: at s[3]

// State encoding
parameter LOW = 2'b00;  // Below s[1]
parameter MID1 = 2'b01; // Between s[1] and s[2]
parameter MID2 = 2'b10; // Between s[2] and s[3]
parameter HIGH = 2'b11; // Above s[3]

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= LOW;
		fr1 <= 1;
		fr2 <= 1;
		fr3 <= 1;
		dfr <= 0;
		prev_level <= LOW;
	end else begin
		state <= next_state;
		// Update flow rate outputs based on the current state
		case (next_state)
			LOW: begin
				fr1 <= 1;
				fr2 <= 1;
				fr3 <= 1;
				dfr <= 0;
			end
			MID1: begin
				fr1 <= 1;
				fr2 <= 1;
				fr3 <= 0;
				dfr <= (prev_level < MID1) ? 1 : 0;
			end
			MID2: begin
				fr1 <= 1;
				fr2 <= 0;
				fr3 <= 0;
				dfr <= (prev_level < MID2) ? 1 : 0;
			end
			HIGH: begin
				fr1 <= 0;
				fr2 <= 0;
				fr3 <= 0;
				dfr <= 0;
			end
		endcase
	end
end

always @(*) begin
	case (state)
		LOW: begin
			if (s[1]) next_state = MID1;
			else next_state = LOW;
		end
		MID1: begin
			if (s[2]) next_state = MID2;
			else if (s[1]) next_state = LOW;
			else next_state = MID1;
		end
		MID2: begin
			if (s[3]) next_state = HIGH;
			else if (s[1]) next_state = LOW;
			else if (s[2]) next_state = MID1;
			else next_state = MID2;
		end
		HIGH: begin
			if (s[3]) next_state = HIGH;
			else if (s[2]) next_state = MID2;
			else if (s[1]) next_state = MID1;
			else next_state = LOW;
		end
		default: next_state = LOW;
	endcase
	prev_level <= state;
end

endmodule

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);

	reg [1:0] state, next_state;

	localparam [1:0]
		STATE_LOW = 2'b00,   // Below s[1]
		STATE_MEDIUM = 2'b01, // Between s[2] and s[1]
		STATE_HIGH = 2'b10;   // Between s[3] and s[2]

	always @(posedge clk or posedge reset) begin
		if (reset)
			state <= STATE_LOW;
		else
			state <= next_state;
	end

	always @(*) begin
		case (state)
			STATE_LOW: begin
				if (s[1])
					next_state = STATE_MEDIUM;
				else
					next_state = STATE_LOW;
			end
			STATE_MEDIUM: begin
				if (s[2])
					next_state = STATE_HIGH;
				else if (s[1] == 0)
					next_state = STATE_LOW;
				else
					next_state = STATE_MEDIUM;
			end
			STATE_HIGH: begin
				if (s[3])
					next_state = STATE_MEDIUM;
				else if (s[2] == 0)
					next_state = STATE_LOW;
				else
					next_state = STATE_HIGH;
			end
			default: next_state = STATE_LOW;
		endcase
	end

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			fr3 <= 1;
			fr2 <= 1;
			fr1 <= 1;
			dfr <= 0;
		end else begin
			case (next_state)
				STATE_LOW: begin
					fr3 <= 1;
					fr2 <= 1;
					fr1 <= 1;
					dfr <= 0;
				end
				STATE_MEDIUM: begin
					fr3 <= 1;
					fr2 <= 0;
					fr1 <= 1;
					dfr <= 0;
				end
				STATE_HIGH: begin
					fr3 <= 1;
					fr2 <= 0;
					fr1 <= 0;
					dfr <= 1; // Increase flow rate when transitioning upwards
				end
				default: begin
					fr3 <= 1;
					fr2 <= 1;
					fr1 <= 1;
					dfr <= 0;
				end
			endcase
		end
	end
endmodule