module top_module (
    input clk,
    input in,
    input reset,
    output done
);
    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START_BIT = 3'b001,
        DATA_BITS = 3'b010,
        CHECK_STOP = 3'b011,
        DONE = 3'b100
    } state_t;

    state_t state, next_state;
    logic [3:0] bit_count; // Count of received bits (0 for start bit, 1-8 for data bits)

    assign done = (state == DONE);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 4'b0000;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        next_state = state;
        case (state)
            IDLE: begin
                if (in == 1'b0) // Detect start bit
                    next_state = START_BIT;
            end

            START_BIT: begin
                if (in == 1'b1) // Transition to data bits on next clock
                    next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_count < 4'd8) begin
                    if (clk) // Sample data bit on clk edge
                        bit_count = bit_count + 1;
                end else begin
                    next_state = CHECK_STOP;
                end
            end

            CHECK_STOP: begin
                if (in == 1'b1) // Check stop bit
                    next_state = DONE;
                else begin
                    bit_count = 4'b0000; // Reset bit count if stop bit not received
                    next_state = IDLE; // Wait for a new start bit
                end
            end

            DONE: begin
                bit_count = 4'b0000; // Reset bit count
                next_state = IDLE; // Go back to idle after done
            end

        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg done
);

	// State encoding
	typedef enum reg [1:0] {
		IDLE       = 2'b00,
		START_BIT  = 2'b01,
		DATA_BITS  = 2'b10,
		STOP_BIT   = 2'b11
	} state_t;

	state_t current_state, next_state;
	reg [3:0] bit_count; // Count of bits received (0 to 8)

	// State transition
	always @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= IDLE;
			bit_count <= 0;
			done <= 0;
		end else begin
			current_state <= next_state;
		end
	end

	// Next state logic
	always @* begin
		next_state = current_state;
		done = 0;

		case (current_state)
			IDLE: begin
				if (in == 0) begin // Start bit detected
					next_state = START_BIT;
					bit_count = 0;
				end
			end

			START_BIT: begin
				if (in == 1) begin
					next_state = DATA_BITS; // Transition to data bits
				end
			end

			DATA_BITS: begin
				if (bit_count < 8) begin
					bit_count = bit_count + 1;
				end else begin
					next_state = STOP_BIT; // All data bits received
				end
			end

			STOP_BIT: begin
				if (in == 1) begin // Stop bit detected
					done = 1; // Byte received
					next_state = IDLE; // Go back to idle
				end else begin
					// Stay in STOP_BIT state until correct stop bit is received
					next_state = STOP_BIT;
				end
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t state, next_state;
    integer bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            done <= 0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (state == DATA) begin
            bit_count <= bit_count + 1;
        end else begin
            bit_count <= 0;
        end
    end

    always_comb begin
        case (state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START;
                    done = 0;
                end else begin
                    next_state = IDLE;
                    done = 0;
                end
            end

            START: begin
                if (in == 0) begin
                    next_state = DATA;
                    done = 0;
                end else begin
                    next_state = IDLE;
                    done = 0;
                end
            end

            DATA: begin
                if (bit_count == 7) begin
                    next_state = STOP;
                    done = 0;
                end else begin
                    next_state = DATA;
                    done = 0;
                end
            end

            STOP: begin
                if (in == 1) begin
                    next_state = IDLE;
                    done = 1;
                end else begin
                    next_state = STOP;
                    done = 0;
                end
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum logic [2:0] {
        IDLE,
        START_BIT,
        DATA_RECEIVE,
        STOP_BIT,
        VERIFY_STOP
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count; // count for data bits
    assign done = (current_state == VERIFY_STOP && in == 1'b1);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 4'b0;
        end else begin
            current_state <= next_state;
        end
    end

    always_comb begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (in == 1'b0) // Detect start bit
                    next_state = START_BIT;
            end
            START_BIT: begin
                next_state = DATA_RECEIVE; // Move to receive data bits
            end
            DATA_RECEIVE: begin
                if (bit_count < 4'd8)
                    bit_count = bit_count + 1;
                else
                    next_state = STOP_BIT; // Once 8 bits are received
            end
            STOP_BIT: begin
                next_state = VERIFY_STOP; // Move to verify stop bit
            end
            VERIFY_STOP: begin
                if (in == 1'b1)
                    next_state = IDLE; // Return to idle after verifying stop bit
                else
                    next_state = STOP_BIT; // Wait for correct stop bit
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);
    typedef enum logic [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t current_state, next_state;
    integer bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            done <= 0;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (current_state == DATA) begin
            bit_count <= bit_count + 1;
        end else if (current_state == IDLE || current_state == START || current_state == STOP) begin
            bit_count <= 0;
        end
    end

    always_comb begin
        done = 0;
        case (current_state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START;
                end else begin
                    next_state = IDLE;
                end
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_count < 7) begin
                    next_state = DATA;
                end else begin
                    next_state = STOP;
                end
            end
            STOP: begin
                if (in == 1) begin
                    done = 1;
                    next_state = IDLE;
                end else begin
                    next_state = STOP;
                end
            end
            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

    typedef enum logic [2:0] {
        IDLE,
        START_BIT,
        DATA_BITS,
        STOP_BIT,
        DONE
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count; // 8 data bits + 1 start bit + 1 stop bit

    assign done = (current_state == DONE);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(current_state or in) begin
        case (current_state)
            IDLE: begin
                if (in == 1'b0) // Start bit detected
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end
            START_BIT: begin
                next_state = DATA_BITS; // Move to data bits after start bit
                bit_count = 0; // Reset bit count
            end
            DATA_BITS: begin
                bit_count = bit_count + 1;
                if (bit_count == 8)
                    next_state = STOP_BIT; // Move to stop bit after 8 data bits
                else
                    next_state = DATA_BITS; // Continue receiving data bits
            end
            STOP_BIT: begin
                if (in == 1'b1) // Stop bit detected
                    next_state = DONE;
                else
                    next_state = STOP_BIT; // Wait for stop bit
            end
            DONE: begin
                if (in == 1'b0) // Wait for new start bit
                    next_state = START_BIT;
                else
                    next_state = DONE;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

	typedef enum logic [2:0] {
		IDLE,
		CHECK_START,
		RECEIVE_DATA,
		CHECK_STOP
	} state_t;

	state_t state, next_state;
	integer bit_count;

	assign done = (state == CHECK_STOP) && (bit_count == 8);

	always_ff @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= IDLE;
			bit_count <= 0;
		end else begin
			state <= next_state;
		end
	end

	always_ff @(state or in) begin
		next_state = state;

		case (state)
			IDLE: begin
				if (in == 0) begin
					next_state = CHECK_START;
				end
			end

			CHECK_START: begin
				if (in == 1) begin
					next_state = IDLE;
				end else begin
					next_state = RECEIVE_DATA;
					bit_count = 0;
				end
			end

			RECEIVE_DATA: begin
				if (bit_count < 7) begin
					bit_count = bit_count + 1;
				end else begin
					next_state = CHECK_STOP;
				end
			end

			CHECK_STOP: begin
				if (in == 1) begin
					next_state = IDLE;
				end else begin
					next_state = IDLE; // wait for start bit
				end
			end
		endcase
	end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

	typedef enum logic [2:0] {
		IDLE,
		START,
		DATA0,
		DATA1,
		DATA2,
		DATA3,
		DATA4,
		DATA5,
		DATA6,
		DATA7,
		STOP
	} state_t;

	state_t state, next_state;
	reg [3:0] bit_count;

	assign done = (state == STOP);

	always_ff @(posedge clk or posedge reset) begin
		if (reset)
			state <= IDLE;
		else
			state <= next_state;
	end

	always_ff @(posedge clk or posedge reset) begin
		if (reset)
			bit_count <= 0;
		else if (state == START)
			bit_count <= 0;
		else if (state >= DATA0 && state <= DATA7)
			bit_count <= bit_count + 1;
	end

	always_comb begin
		next_state = state;
		case (state)
			IDLE: begin
				if (in == 0) // Detect start bit
					next_state = START;
			end
			START: begin
				if (bit_count == 0) // Wait for the first data bit
					next_state = DATA0;
			end
			DATA0: next_state = (bit_count == 7) ? STOP : DATA1;
			DATA1: next_state = (bit_count == 7) ? STOP : DATA2;
			DATA2: next_state = (bit_count == 7) ? STOP : DATA3;
			DATA3: next_state = (bit_count == 7) ? STOP : DATA4;
			DATA4: next_state = (bit_count == 7) ? STOP : DATA5;
			DATA5: next_state = (bit_count == 7) ? STOP : DATA6;
			DATA6: next_state = (bit_count == 7) ? STOP : DATA7;
			DATA7: next_state = STOP;
			STOP: begin
				if (in == 1) // Check for the stop bit
					next_state = IDLE;
			end
			default: next_state = IDLE;
		endcase
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);
    typedef enum logic [1:0] {
        IDLE = 2'b00,
        START_BIT = 2'b01,
        DATA = 2'b10,
        STOP_BIT = 2'b11
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count;

    assign done = (current_state == STOP_BIT && in == 1'b1);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 4'd0;
        end else begin
            current_state <= next_state;
            if (current_state == DATA) begin
                bit_count <= bit_count + 1;
            end else if (current_state == START_BIT || current_state == IDLE) begin
                bit_count <= 0;
            end
        end
    end

    always_comb begin
        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START_BIT;
                end else begin
                    next_state = IDLE;
                end
            end
            START_BIT: begin
                if (bit_count == 0) begin
                    next_state = DATA;
                end else begin
                    next_state = START_BIT;
                end
            end
            DATA: begin
                if (bit_count == 8) begin
                    next_state = STOP_BIT;
                end else begin
                    next_state = DATA;
                end
            end
            STOP_BIT: begin
                if (in == 1'b1) begin
                    next_state = IDLE;
                end else begin
                    next_state = STOP_BIT;
                end
            end
            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg done
);

	typedef enum reg [2:0] {
		IDLE = 3'b000,
		START_BIT = 3'b001,
		RECEIVING = 3'b010,
		CHECK_STOP = 3'b011
	} state_t;

	state_t current_state, next_state;
	reg [3:0] bit_count;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= IDLE;
			bit_count <= 0;
			done <= 0;
		end else begin
			current_state <= next_state;
		end
	end

	always @(*) begin
		next_state = current_state;
		done = 0;
		case (current_state)
			IDLE: begin
				if (in == 1'b0) begin
					next_state = START_BIT;
				end
			end
			START_BIT: begin
				next_state = RECEIVING;
				bit_count = 0;
			end
			RECEIVING: begin
				bit_count = bit_count + 1;
				if (bit_count == 8) begin
					next_state = CHECK_STOP;
				end
			end
			CHECK_STOP: begin
				if (in == 1'b1) begin
					done = 1;
					next_state = IDLE;
				end else begin
					next_state = CHECK_STOP;
				end
			end
		endcase
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE       = 3'b000,
        START_BIT  = 3'b001,
        DATA_BITS  = 3'b010,
        STOP_BIT   = 3'b011,
        ERROR      = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            done <= 0;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state;
        done = 0;
        case (current_state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START_BIT;
                end
            end
            START_BIT: begin
                if (in == 1) begin
                    next_state = IDLE; // invalid start bit
                end else begin
                    next_state = DATA_BITS;
                    bit_count = 0; // reset bit count
                end
            end
            DATA_BITS: begin
                if (bit_count < 8) begin
                    if (bit_count == 7) begin
                        bit_count = bit_count + 1; // increment after last data bit
                        next_state = STOP_BIT;
                    end else begin
                        bit_count = bit_count + 1; // increment within data bits
                    end
                end else begin
                    next_state = ERROR; // shouldn't get here
                end
            end
            STOP_BIT: begin
                if (in == 1) begin
                    done = 1; // valid byte received
                    next_state = IDLE; // go back to idle
                end else begin
                    next_state = IDLE; // invalid stop bit
                end
            end
            ERROR: begin
                if (in == 1) begin
                    next_state = IDLE; // reset to IDLE on idle line
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START_BIT = 3'b001,
        DATA_BITS = 3'b010,
        STOP_BIT = 3'b011,
        DONE = 3'b100
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count; // counts received data bits

    assign done = (current_state == DONE);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (in == 0) // Start bit detected
                    next_state = START_BIT;
            end
            START_BIT: begin
                if (bit_count == 8) // Wait to receive 8 bits
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end
            DATA_BITS: begin
                if (bit_count < 7)
                    next_state = DATA_BITS; // Continue receiving data bits
                else
                    next_state = STOP_BIT; // Data bits complete
            end
            STOP_BIT: begin
                if (in == 1) // Stop bit detected
                    next_state = DONE;
                else
                    next_state = IDLE; // If no stop bit, return to IDLE
            end
            DONE: begin
                next_state = IDLE; // Return to IDLE after done
            end
        endcase
    end

    always @(posedge clk) begin
        if (current_state == START_BIT) begin
            bit_count <= 0; // Reset bit count on start bit
        end else if (current_state == DATA_BITS) begin
            bit_count <= bit_count + 1; // Count received data bits
        end
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);
    typedef enum logic [2:0] {
        IDLE,       // Waiting for start bit
        START_BIT,  // Detected start bit
        DATA_BIT,   // Receiving data bits
        STOP_BIT,   // Waiting for stop bit
        DONE        // Byte received successfully
    } state_t;

    state_t state, next_state;
    logic [3:0] bit_count; // Counts data bits received (0 to 8)
    assign done = (state == DONE);

    // State Transition
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 0;
        end else begin
            state <= next_state;
            if (state == START_BIT) begin
                bit_count <= 0; // Reset bit count after detecting start bit
            end else if (state == DATA_BIT) begin
                bit_count <= bit_count + 1; // Increment bit count
            end
        end
    end

    // Next State Logic
    always_comb begin
        next_state = state; // Default to hold current state
        case (state)
            IDLE: begin
                if (in == 0) begin // Start bit detected
                    next_state = START_BIT;
                end
            end
            START_BIT: begin
                next_state = DATA_BIT; // Move to data bits after start bit
            end
            DATA_BIT: begin
                if (bit_count == 7) begin // After receiving 8 data bits
                    next_state = STOP_BIT;
                end
            end
            STOP_BIT: begin
                if (in == 1) begin // Stop bit detected
                    next_state = DONE; // Transition to DONE
                end
                // Stay in STOP_BIT until stop bit received
            end
            DONE: begin
                // After DONE, can go back to IDLE or remain same
                next_state = IDLE; // Assume next byte reception starts after one is done
            end
            default: next_state = IDLE; // Default case
        endcase
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

	reg [3:0] state;
	reg [3:0] bit_count;
	reg receiving;
	reg done_reg;

	localparam IDLE      = 4'b0000;
	localparam START     = 4'b0001;
	localparam DATA      = 4'b0010;
	localparam STOP      = 4'b0011;

	assign done = done_reg;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= IDLE;
			bit_count <= 4'b0;
			receiving <= 1'b0;
			done_reg <= 1'b0;
		end else begin
			case (state)
				IDLE: begin
					done_reg <= 1'b0;
					if (in == 1'b0) begin
						state <= START;
					end
				end

				START: begin
					if (in == 1'b0) begin
						bit_count <= 4'b0;
						state <= DATA;
					end else begin
						state <= IDLE;
					end
				end

				DATA: begin
					if (bit_count < 8) begin
						bit_count <= bit_count + 1;
					end else begin
						state <= STOP;
					end
				end

				STOP: begin
					if (in == 1'b1) begin
						done_reg <= 1'b1;
						state <= IDLE;
					end else begin
						state <= IDLE; // If stop bit is not high, go back to IDLE
					end
				end

			endcase
		end
	end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

	parameter IDLE = 2'b00, START = 2'b01, DATA = 2'b10, STOP = 2'b11;
	reg [1:0] state, next_state;
	reg [2:0] bit_count; // to count data bits

	assign done = (state == STOP && in == 1'b1);

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= IDLE;
			bit_count <= 3'b000;
		end else begin
			state <= next_state;
		end
	end

	always @(*) begin
		next_state = state;
		case (state)
			IDLE: begin
				if (in == 1'b0) // start bit detected
					next_state = START;
			end
			START: begin
				next_state = DATA; // move to data bit state
				bit_count = 3'b000; // reset bit count
			end
			DATA: begin
				if (bit_count < 3'b111) begin // 8 bits to receive
					bit_count = bit_count + 1'b1;
					next_state = DATA; // stay in data state
				end else begin
					next_state = STOP; // move to stop bit check
				end
			end
			STOP: begin
				if (in == 1'b1) // stop bit detected
					next_state = IDLE; // back to idle
				else begin
					next_state = STOP; // stay in stop state
				end
			end
		endcase
	end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

    typedef enum reg [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count; // Counts the number of data bits received
    reg done_reg;

    assign done = done_reg;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
            done_reg <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        case (current_state)
            IDLE: begin
                done_reg = 0;
                if (in == 1'b0) // start bit detected
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                if (bit_count == 0) begin
                    next_state = DATA;
                    bit_count = 0; // reset data bit counter
                end else begin
                    next_state = START;
                end
            end
            DATA: begin
                if (bit_count < 8) begin
                    // read the data bit
                    bit_count = bit_count + 1;
                    next_state = DATA;
                end else begin
                    next_state = STOP; // if we have received 8 bits
                end
            end
            STOP: begin
                if (in == 1'b1) begin
                    done_reg = 1; // valid byte received
                    next_state = IDLE; // go back to idle
                end else begin
                    next_state = STOP; // wait for correct stop bit
                end
            end
            default: next_state = IDLE;
        endcase
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

    typedef enum logic [1:0] {
        IDLE = 2'b00,
        START_BIT = 2'b01,
        DATA_BITS = 2'b10,
        STOP_BIT = 2'b11
    } state_t;

    state_t state, next_state;
    logic [3:0] bit_count;
    assign done = (state == STOP_BIT);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin
        next_state = state;
        case(state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START_BIT;
                    bit_count = 0;
                end
            end
            START_BIT: begin
                if (bit_count == 3) begin  // Wait 1 clock for start bit to stabilize
                    next_state = DATA_BITS;
                end
            end
            DATA_BITS: begin
                if (bit_count < 8) begin
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP_BIT;
                end
            end
            STOP_BIT: begin
                if (in == 1) begin
                    next_state = IDLE;
                end else begin
                    // Remain in STOP_BIT until the stop bit is valid
                    next_state = STOP_BIT;
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output done
);

    typedef enum logic [2:0] {
        IDLE,
        START_BIT,
        DATA_BITS,
        STOP_BIT,
        DONE
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count; // Counts the bits received

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            bit_count <= 0;
        end else if (current_state == DATA_BITS) begin
            bit_count <= bit_count + 1;
        end else if (current_state == DONE) begin
            bit_count <= 0;
        end
    end

    always_comb begin
        case (current_state)
            IDLE: begin
                if (in == 0) // Start bit detected
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end
            START_BIT: begin
                next_state = DATA_BITS; // Proceed to data bits after start bit
            end
            DATA_BITS: begin
                if (bit_count == 7) // All 8 data bits received
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end
            STOP_BIT: begin
                if (in == 1) // Stop bit detected
                    next_state = DONE;
                else
                    next_state = STOP_BIT; // Wait for the correct stop bit
            end
            DONE: begin
                next_state = IDLE; // Go back to IDLE after done
            end
            default: next_state = IDLE; // Default state
        endcase
    end

    assign done = (current_state == DONE);

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

    typedef enum logic [2:0] {
        IDLE,       // Idle state
        START_BIT,  // Start bit detected
        DATA_BITS,  // Receiving data bits
        STOP_BIT,   // Stop bit checking
        DONE        // Byte received
    } state_t;

    state_t state, next_state;
    logic [2:0] bit_count; // To count the number of received data bits

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            bit_count <= 3'b0;
        end else begin
            state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (state == DATA_BITS)
            bit_count <= bit_count + 3'b1;
        else if (state == IDLE || state == STOP_BIT)
            bit_count <= 3'b0;
    end

    always_comb begin
        case (state)
            IDLE: begin
                if (~in) // Start bit detected
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end

            START_BIT: begin
                next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_count == 3'd7)
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end

            STOP_BIT: begin
                if (in) // Stop bit detected
                    next_state = DONE;
                else
                    next_state = STOP_BIT;
            end

            DONE: begin
                next_state = IDLE; // After done, return to idle
            end

            default: next_state = IDLE;
        endcase
    end

    assign done = (state == DONE);

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output done
);

    typedef enum logic [2:0] {
        IDLE = 3'b000,
        START = 3'b001,
        DATA = 3'b010,
        STOP = 3'b011
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count; // 8 data bits + 1 stop bit

    assign done = (current_state == STOP);

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 4'd0;
        end else begin
            current_state <= next_state;
            if (next_state == DATA) begin
                bit_count <= bit_count + 1;
            end else if (next_state == IDLE) begin
                bit_count <= 4'd0;
            end
        end
    end

    always_comb begin
        case (current_state)
            IDLE: begin
                if (in == 0)
                    next_state = START;
                else
                    next_state = IDLE;
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_count == 4'd8)
                    next_state = STOP;
                else
                    next_state = DATA;
            end
            STOP: begin
                if (in == 1)
                    next_state = IDLE;
                else
                    next_state = STOP;
            end
            default: next_state = IDLE;
        endcase
    end

endmodule


module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            out_byte <= 8'b0;
            done <= 1'b0;
            bit_count <= 4'b0;
        end else begin
            current_state <= next_state;
        end
    end

    always @(*) begin
        next_state = current_state;
        done = 1'b0;

        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START;
                end
            end

            START: begin
                if (in == 1'b1) begin
                    next_state = IDLE; // Invalid start
                end else begin
                    next_state = DATA;
                    bit_count = 4'b0;
                end
            end

            DATA: begin
                if (bit_count < 4'd8) begin
                    out_byte[bit_count] = in; // Capture data bits
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP;
                end
            end

            STOP: begin
                done = 1'b1;
                if (in == 1'b1) begin
                    next_state = IDLE;
                end else begin
                    next_state = IDLE; // Invalid stop
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE,
        START_BIT,
        DATA_BITS,
        STOP_BIT,
        ERROR
    } state_t;

    state_t current_state, next_state;
    logic [3:0] bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (current_state == DATA_BITS) begin
            out_byte[bit_count] <= in; // capture data bits
        end
    end

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            bit_count <= 0;
        end else if (current_state == DATA_BITS) begin
            bit_count <= bit_count + 1;
        end else if (current_state == IDLE) begin
            bit_count <= 0;
        end
    end

    always_comb begin
        case (current_state)
            IDLE: begin
                done = 0;
                if (in == 0) // Start bit detected
                    next_state = START_BIT;
                else
                    next_state = IDLE;
            end

            START_BIT: begin
                if (in == 0) // Still receiving start bit
                    next_state = START_BIT;
                else // Start bit completed
                    next_state = DATA_BITS;
            end

            DATA_BITS: begin
                if (bit_count == 7) // Received all 8 bits
                    next_state = STOP_BIT;
                else
                    next_state = DATA_BITS;
            end

            STOP_BIT: begin
                if (in == 1) begin // Stop bit received
                    done = 1;
                    next_state = IDLE; // Return to IDLE
                end else begin
                    next_state = ERROR; // Stop bit not received
                end
            end

            ERROR: begin
                if (in == 1) // Find a stop bit before trying again
                    next_state = IDLE;
                else
                    next_state = ERROR;
            end

            default: next_state = IDLE; // Default state
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);
    parameter IDLE = 2'b00, START = 2'b01, DATA = 2'b10, STOP = 2'b11;
    reg [1:0] state, next_state;
    reg [2:0] bit_count; // to count the 8 data bits

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        done = 0;
        case (state)
            IDLE: begin
                if (in == 0) // start bit detected
                    next_state = START;
            end

            START: begin
                next_state = DATA;
                bit_count = 0; // reset bit counter
            end

            DATA: begin
                if (bit_count < 8) begin
                    out_byte[bit_count] = in; // capture data bit
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP;
                end
            end

            STOP: begin
                if (in == 1) begin // stop bit detected
                    done = 1;
                    next_state = IDLE; // return to idle
                end
                // If stop bit is not detected, stay in STOP state
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE,
        START,
        RECEIVING,
        STOP
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            current_state <= next_state;
            if (current_state == RECEIVING) begin
                out_byte <= {in, out_byte[7:1]};
            end
            done <= (current_state == STOP);
        end
    end

    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START;
                end
            end
            START: begin
                next_state = RECEIVING;
                bit_count = 0;
            end
            RECEIVING: begin
                if (bit_count < 8) begin
                    next_state = RECEIVING;
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP;
                end
            end
            STOP: begin
                if (in == 1'b1) begin
                    next_state = IDLE;
                end else begin
                    next_state = STOP;
                end
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

    typedef enum reg [2:0] {
        IDLE,
        START_BIT,
        DATA_BITS,
        STOP_BIT
    } state_t;

    state_t current_state, next_state;
    reg [3:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            bit_count <= 0;
            out_byte <= 8'b0;
            done <= 0;
        end else begin
            current_state <= next_state;
        end
    end

    always @* begin
        next_state = current_state;
        done = 0;
        case (current_state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START_BIT;
                end
            end

            START_BIT: begin
                if (bit_count == 0) begin
                    bit_count = 0;
                    next_state = DATA_BITS;
                end
            end

            DATA_BITS: begin
                if (bit_count < 8) begin
                    out_byte[bit_count] = in;  // Receive data bit
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP_BIT;
                end
            end

            STOP_BIT: begin
                if (in == 1) begin
                    done = 1;  // Stop bit received
                    next_state = IDLE;
                end else begin
                    next_state = IDLE;  // Wait for stop bit
                end
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 3'b0;
        end else begin
            current_state <= next_state;
            if (current_state == DATA) begin
                out_byte[bit_count] <= in; // Capture the data bit
                bit_count <= bit_count + 1;
            end else if (current_state == STOP) begin
                done <= 1;
            end else begin
                done <= 0;
                if (current_state == IDLE) bit_count <= 0; // Reset bit count in IDLE
            end
        end
    end

    always_comb begin
        case (current_state)
            IDLE: begin
                if (in == 0) // Detect start bit
                    next_state = START;
                else
                    next_state = IDLE;
            end

            START: begin
                next_state = DATA;
            end

            DATA: begin
                if (bit_count == 7)
                    next_state = STOP;
                else
                    next_state = DATA;
            end

            STOP: begin
                if (in == 1) // Check for stop bit
                    next_state = IDLE;
                else
                    next_state = STOP; // Wait for valid stop bit
            end

            default: next_state = IDLE; // Default to IDLE
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum reg [2:0] {IDLE, START, DATA, STOP} state_t;
    state_t state, next_state;
    reg [3:0] bit_count; // Count of received data bits

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 1'b0;
            bit_count <= 4'b0;
        end else begin
            state <= next_state;
            if (state == DATA) begin
                out_byte[bit_count] <= in; // Shift data bits
            end
            if (next_state == STOP) begin
                done <= 1'b1; // Assert done when in STOP state
            end else begin
                done <= 1'b0;
            end
        end
    end

    always @(*) begin
        next_state = state; // Default to stay in the current state
        case (state)
            IDLE: begin
                if (in == 1'b0) // Detect start bit
                    next_state = START;
            end
            START: begin
                next_state = DATA;
                bit_count = 0; // Reset bit counter
            end
            DATA: begin
                if (bit_count < 8) begin
                    bit_count = bit_count + 1; // Increment bit counter
                    next_state = DATA; // Stay in DATA state
                end else begin
                    next_state = STOP; // Move to STOP state after 8 bits
                end
            end
            STOP: begin
                if (in == 1'b1) begin // Check stop bit
                    next_state = IDLE; // Go back to IDLE after stop bit
                end else begin
                    next_state = STOP; // Stay in STOP state until stop bit is correct
                end
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

	typedef enum reg [2:0] {IDLE, START, DATA, STOP} state_t;
	state_t current_state, next_state;
	reg [2:0] bit_count;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= IDLE;
			out_byte <= 8'b0;
			done <= 1'b0;
			bit_count <= 3'b0;
		end else begin
			current_state <= next_state;
		end
	end

	always @(*) begin
		next_state = current_state;
		done = 1'b0;

		case (current_state)
			IDLE: begin
				if (in == 1'b0) begin // Detect start bit
					next_state = START;
					bit_count = 3'b0;
				end
			end

			START: begin
				if (bit_count == 3'b0) begin
					next_state = DATA; // Expect data bits after start
				end
			end

			DATA: begin
				if (bit_count < 3'b111) begin
					out_byte[bit_count] = in; // Shift in data bit
					bit_count = bit_count + 1;
				end else begin
					next_state = STOP; // Move to stop after 8 bits
				end
			end

			STOP: begin
				done = 1'b1; // Assert done when stop bit is detected
				if (in == 1'b1) begin // Check for stop bit
					next_state = IDLE; // Go back to idle if stop is correct
				end else begin
					next_state = IDLE; // Restart search if stop is not correct
				end
			end

			default: next_state = IDLE;
		endcase
	end

	always @(posedge clk) begin
		if (current_state == DATA) begin
			bit_count <= bit_count + 1;
		end else if (current_state == STOP) begin
			if (in == 1'b1) begin
				done <= 1'b1;
			end
		end
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        done = 0;

        case (state)
            IDLE: begin
                if (in == 0) begin // Detect start bit
                    next_state = START;
                    bit_count = 0;
                end
            end
            START: begin
                if (in == 1) begin
                    // Wait for start bit to stabilize
                    next_state = START;
                end else begin
                    next_state = DATA;
                end
            end
            DATA: begin
                if (bit_count < 8) begin
                    out_byte[bit_count] = in; // Read data bits
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP; // Switch to stop bit state after 8 bits
                end
            end
            STOP: begin
                if (in == 1) begin
                    done = 1; // Stop bit valid
                    next_state = IDLE; // Back to idle
                end else begin
                    // Wait for a valid stop bit
                    next_state = STOP;
                end
            end
        endcase
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

typedef enum reg [2:0] {
	IDLE,
	START,
	DATA,
	STOP
} state_t;

state_t current_state, next_state;
reg [2:0] bit_count;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		current_state <= IDLE;
		bit_count <= 3'b000;
		out_byte <= 8'b00000000;
		done <= 0;
	end else begin
		current_state <= next_state;
	end
end

always @(*) begin
	next_state = current_state;
	done = 0;
	case (current_state)
		IDLE: begin
			if (in == 0) begin
				next_state = START;
			end
		end
		START: begin
			if (bit_count == 3'b000) begin
				bit_count = bit_count + 1;
				next_state = DATA;
			end
		end
		DATA: begin
			if (bit_count < 3'b111) begin
				out_byte[bit_count] = in;
				bit_count = bit_count + 1;
			end else begin
				next_state = STOP;
			end
		end
		STOP: begin
			if (in == 1) begin
				done = 1;
				next_state = IDLE;
			end else begin
				next_state = IDLE;
			end
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);
    reg [3:0] state; // State register
    reg [3:0] bit_count; // Bit counter
    reg [7:0] data; // Shift register for data

    // State encoding
    localparam IDLE = 4'b0000,
               START = 4'b0001,
               DATA = 4'b0010,
               STOP = 4'b0011;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            done <= 0;
            out_byte <= 8'b0;
            bit_count <= 0;
            data <= 8'b0;
        end else begin
            case (state)
                IDLE: begin
                    done <= 0;
                    if (in == 0) // Start bit detected
                        state <= START;
                end

                START: begin
                    // Wait for a stable start bit
                    if (in == 0) begin
                        state <= DATA;
                        bit_count <= 0;
                    end else if (in == 1) begin
                        state <= IDLE; // If not valid, return to idle
                    end
                end

                DATA: begin
                    if (bit_count < 8) begin
                        data[bit_count] <= in; // Shift in data bit
                        bit_count <= bit_count + 1;
                    end else begin
                        state <= STOP; // Move to stop bit after 8 data bits
                    end
                end

                STOP: begin
                    if (in == 1) begin
                        out_byte <= data; // Output received data
                        done <= 1; // Indicate successful reception
                        state <= IDLE; // Return to idle state for next byte
                    end else begin
                        state <= IDLE; // If stop bit not received, go back to idle
                    end
                end
            endcase
        end
    end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

parameter IDLE = 2'b00, START = 2'b01, DATA = 2'b10, STOP = 2'b11;
reg [1:0] state, next_state;
reg [3:0] bit_count;

always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= IDLE;
		done <= 0;
		out_byte <= 8'b0;
		bit_count <= 4'b0;
	end else begin
		state <= next_state;
	end
end

always @(*) begin
	next_state = state;
	done = 0;
	case (state)
		IDLE: begin
			if (in == 0) begin // start bit detected
				next_state = START;
				bit_count = 0;
			end
		end

		START: begin
			next_state = DATA;
		end

		DATA: begin
			out_byte[bit_count] = in; // collect data bits
			if (bit_count == 7) begin
				next_state = STOP;
			end else begin
				bit_count = bit_count + 1;
			end
		end

		STOP: begin
			if (in == 1) begin // stop bit detected
				done = 1;
				next_state = IDLE;
			end else begin
				next_state = IDLE; // wait for correct stop bit
			end
		end
	endcase
end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum reg [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        done = 0;
        case (state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START;
                end
            end

            START: begin
                next_state = DATA;
                bit_count = 0;
            end

            DATA: begin
                if (bit_count < 7) begin
                    out_byte[bit_count] = in;
                    bit_count = bit_count + 1;
                end else begin
                    out_byte[7] = in;
                    next_state = STOP;
                end
            end

            STOP: begin
                if (in == 1) begin
                    done = 1;
                    next_state = IDLE;
                end else begin
                    next_state = IDLE; // Wait for the next valid start bit
                end
            end
        endcase
    end

endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

	reg [3:0] state;
	reg [3:0] bit_count;
	reg [7:0] data;

	parameter IDLE = 4'b0000;
	parameter START = 4'b0001;
	parameter DATA = 4'b0010;
	parameter STOP = 4'b0011;

	always @(posedge clk or posedge reset) begin
		if (reset) begin
			state <= IDLE;
			done <= 0;
			out_byte <= 8'b0;
			bit_count <= 0;
		end else begin
			case (state)
				IDLE: begin
					done <= 0;
					bit_count <= 0;
					if (in == 0) begin
						state <= START;
					end
				end

				START: begin
					if (in == 0) begin
						state <= DATA;
						bit_count <= 0;
					end else begin
						state <= IDLE; // If start bit is not detected, return to IDLE
					end
				end

				DATA: begin
					data[bit_count] <= in; // Capture data bit
					bit_count <= bit_count + 1;
					if (bit_count == 7) begin
						state <= STOP; // Move to stop bit after 8 data bits
					end
				end

				STOP: begin
					if (in == 1) begin
						out_byte <= data; // Output the received byte
						done <= 1; // Indicate that a byte has been received
						state <= IDLE; // Wait for the next byte
					end else begin
						state <= IDLE; // If stop bit is not detected, return to IDLE
					end
				end

				default: state <= IDLE; // Default case to prevent latches
			endcase
		end
	end
endmodule

module top_module (
	input clk,
	input in,
	input reset,
	output reg [7:0] out_byte,
	output reg done
);

	typedef enum logic [2:0] {
		IDLE,
		START,
		DATA,
		STOP
	} state_t;

	state_t current_state, next_state;
	reg [3:0] bit_count;

	// State transition
	always_ff @(posedge clk or posedge reset) begin
		if (reset) begin
			current_state <= IDLE;
		end else begin
			current_state <= next_state;
		end
	end

	// Next state logic
	always_comb begin
		next_state = current_state;
		done = 0;
		case (current_state)
			IDLE: begin
				if (in == 1'b0) next_state = START; // Start bit detected
			end
			START: begin
				next_state = DATA; // Move to data state after start bit
			end
			DATA: begin
				if (bit_count == 4'd7)
					next_state = STOP; // After 8 bits, go to stop
				else
					next_state = DATA; // Stay in data state
			end
			STOP: begin
				if (in == 1'b1) begin
					done = 1; // Stop bit detected
					out_byte = {in, out_byte[7:1]}; // Output the received byte
					next_state = IDLE; // Return to idle state
				end else begin
					next_state = IDLE; // Wait for a valid stop bit
				end
			end
		endcase
	end

	// Bit counter
	always_ff @(posedge clk or posedge reset) begin
		if (reset) begin
			bit_count <= 4'd0;
			out_byte <= 8'd0;
		end else begin
			case (current_state)
				IDLE: begin
					bit_count <= 4'd0; // Reset bit count in idle
				end
				START: begin
					// Do nothing, wait for data
				end
				DATA: begin
					out_byte <= {in, out_byte[7:1]}; // Shift in the data bit
					bit_count <= bit_count + 1; // Increment the bit count
				end
				STOP: begin
					// Do nothing, stop bit has been checked
				end
			endcase
		end
	end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);
    typedef enum reg [2:0] {
        IDLE,
        START_BIT,
        DATA_BITS,
        STOP_BIT
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 3'b0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        done = 0;

        case (state)
            IDLE: begin
                if (~in) begin // Detect start bit (0)
                    next_state = START_BIT;
                end
            end
            START_BIT: begin
                if (bit_count < 3'b111) begin
                    next_state = DATA_BITS;
                    bit_count = 3'b0; // Reset bit count
                end
            end
            DATA_BITS: begin
                if (bit_count < 3'b111) begin
                    out_byte[bit_count] = in; // Capture data bits
                    bit_count = bit_count + 1;
                end else begin
                    next_state = STOP_BIT;
                end
            end
            STOP_BIT: begin
                if (in) begin // Check for stop bit (1)
                    done = 1; // Assert done signal
                    next_state = IDLE; // Return to IDLE state
                end else begin
                    // Stay in STOP_BIT until stop bit is received
                    next_state = STOP_BIT;
                end
            end
        endcase
    end
endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t current_state, next_state;
    reg [2:0] bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 3'b0;
        end else begin
            current_state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (current_state == DATA) begin
            out_byte <= {in, out_byte[7:1]};
        end
    end

    always_comb begin
        next_state = current_state;
        done = 0;

        case (current_state)
            IDLE: begin
                if (in == 0) begin
                    next_state = START;
                end
            end

            START: begin
                next_state = DATA;
                bit_count = 0;
            end

            DATA: begin
                bit_count = bit_count + 1;
                if (bit_count == 7) begin
                    next_state = STOP;
                end
            end

            STOP: begin
                if (in == 1) begin
                    done = 1;
                    next_state = IDLE;
                end else begin
                    next_state = STOP;
                end
            end

            default: next_state = IDLE;
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    typedef enum logic [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t state, next_state;
    integer bit_count;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 1'b0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always_ff @(posedge clk) begin
        if (state == DATA) begin
            out_byte[bit_count] <= in;
            bit_count <= bit_count + 1;
        end else if (state == STOP) begin
            done <= 1'b1;
        end else begin
            done <= 1'b0;
        end
    end

    always_comb begin
        next_state = state;
        case (state)
            IDLE: begin
                if (in == 1'b0) next_state = START;  // Detected start bit
            end
            START: begin
                next_state = DATA; // Move to data state after start bit
                bit_count = 0;     // Reset bit count
            end
            DATA: begin
                if (bit_count == 7) next_state = STOP; // After receiving 8 bits
            end
            STOP: begin
                if (in == 1'b1) next_state = IDLE; // Check for stop bit
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);

    reg [3:0] state;
    reg [3:0] next_state;
    reg [7:0] data;
    reg [3:0] bit_count;

    parameter IDLE = 4'b0000,
              START_BIT = 4'b0001,
              DATA_BITS = 4'b0010,
              STOP_BIT = 4'b0011;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_byte <= 8'b0;
            done <= 0;
            bit_count <= 0;
        end else begin
            state <= next_state;
        end
    end

    always @(*) begin
        next_state = state;
        done = 0;
        case (state)
            IDLE: begin
                if (in == 1'b0) begin
                    next_state = START_BIT;
                end
            end

            START_BIT: begin
                if (in == 1'b1) begin
                    next_state = DATA_BITS;
                    bit_count = 0;
                end
            end

            DATA_BITS: begin
                if (bit_count < 8) begin
                    if (in == 1'b0 || in == 1'b1) begin
                        data[bit_count] = in;
                        bit_count = bit_count + 1;
                    end
                end else begin
                    next_state = STOP_BIT;
                end
            end

            STOP_BIT: begin
                if (in == 1'b1) begin
                    out_byte = data;
                    done = 1;
                    next_state = IDLE; // Go back to IDLE after done
                end else begin
                    next_state = STOP_BIT; // Wait for correct stop bit
                end
            end
        endcase
    end

endmodule

module top_module (
    input clk,
    input in,
    input reset,
    output reg [7:0] out_byte,
    output reg done
);
    typedef enum reg [2:0] {
        IDLE,
        START,
        DATA,
        STOP
    } state_t;

    state_t state, next_state;
    reg [2:0] bit_count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            done <= 0;
            out_byte <= 8'b0;
            bit_count <= 0;
        end else begin
            state <= next_state;
            if (next_state == DATA) begin
                out_byte[bit_count] <= in;
                bit_count <= bit_count + 1;
            end
            if (next_state == STOP) begin
                done <= 1;
            end else begin
                done <= 0;
            end
        end
    end

    always @(*) begin
        case (state)
            IDLE: begin
                if (in == 0) next_state = START;
                else next_state = IDLE;
                bit_count = 0;
            end
            START: begin
                next_state = DATA;
            end
            DATA: begin
                if (bit_count == 7) next_state = STOP;
                else next_state = DATA;
            end
            STOP: begin
                if (in == 1) next_state = IDLE;
                else next_state = STOP;
            end
            default: next_state = IDLE;
        endcase
    end
endmodule