Zhangzheng/CGA-bench
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zhang
2026-05-22 10:02:42 +08:00
commit a349b49b47
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demo/shift18/1_4_TBeval/eval1_GoldenRTL/run_info.txt Normal file
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iverilog simulation passed!
iverilog cmd 1:
~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v
iverilog cmd 1 output:
iverilog cmd 1 error:
iverilog cmd 2:
~/bin/bin/vvp run.vvp
iverilog cmd 2 output:
shift18_tb.v:139: $finish called at 290000 (1ps)
iverilog cmd 2 error: