125 lines
12 KiB
Plaintext
125 lines
12 KiB
Plaintext
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# SystemC::Coverage-3
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C 'ffinal_TB.vl10n7ttogglepagev_toggle/testbenchowalk_right:0->1htestbench' 0
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C 'ffinal_TB.vl10n7ttogglepagev_toggle/testbenchowalk_right:1->0htestbench' 0
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C 'ffinal_TB.vl109n5tlinepagev_line/testbenchoblockS109-110htestbench' 21
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C 'ffinal_TB.vl11n7ttogglepagev_toggle/testbenchoaaah:0->1htestbench' 3
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C 'ffinal_TB.vl11n7ttogglepagev_toggle/testbenchoaaah:1->0htestbench' 3
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C 'ffinal_TB.vl12n7ttogglepagev_toggle/testbenchodigging:0->1htestbench' 0
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C 'ffinal_TB.vl12n7ttogglepagev_toggle/testbenchodigging:1->0htestbench' 0
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C 'ffinal_TB.vl121n5tlinepagev_line/testbenchoblockS121-122htestbench' 21
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C 'ffinal_TB.vl159n5tlinepagev_line/testbenchoblockS159-160htestbench' 21
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C 'ffinal_TB.vl175n5tlinepagev_line/testbenchoblockS175-176htestbench' 21
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C 'ffinal_TB.vl29n1tlinepagev_line/testbenchoblockS29-30htestbench' 0
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C 'ffinal_TB.vl3n6ttogglepagev_toggle/testbenchoclk:0->1htestbench' 139
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C 'ffinal_TB.vl3n6ttogglepagev_toggle/testbenchoclk:1->0htestbench' 139
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C 'ffinal_TB.vl31n22texprpagev_expr/testbencho(clk==0) => 1htestbench' 0
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C 'ffinal_TB.vl31n22texprpagev_expr/testbencho(clk==1) => 0htestbench' 0
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C 'ffinal_TB.vl31n5tlinepagev_line/testbenchoblockS31htestbench' 278
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C 'ffinal_TB.vl34n1tlinepagev_line/testbenchoblockS34-35htestbench' 1
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C 'ffinal_TB.vl38n1tlinepagev_line/testbenchoblockS38,40-48,51-59,62-70,73-81,84-92,95-103,106-109,112-115,118-121,124-127,130-138,141-149,152-159,162-165,168-175,178-181,184-192,195-203,205-206htestbench' 1
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C 'ffinal_TB.vl4n6ttogglepagev_toggle/testbenchoareset:0->1htestbench' 1
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C 'ffinal_TB.vl4n6ttogglepagev_toggle/testbenchoareset:1->0htestbench' 1
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C 'ffinal_TB.vl5n6ttogglepagev_toggle/testbenchobump_left:0->1htestbench' 4
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C 'ffinal_TB.vl5n6ttogglepagev_toggle/testbenchobump_left:1->0htestbench' 4
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C 'ffinal_TB.vl6n6ttogglepagev_toggle/testbenchobump_right:0->1htestbench' 4
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C 'ffinal_TB.vl6n6ttogglepagev_toggle/testbenchobump_right:1->0htestbench' 4
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C 'ffinal_TB.vl7n6ttogglepagev_toggle/testbenchoground:0->1htestbench' 10
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C 'ffinal_TB.vl7n6ttogglepagev_toggle/testbenchoground:1->0htestbench' 9
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C 'ffinal_TB.vl8n6ttogglepagev_toggle/testbenchodig:0->1htestbench' 1
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C 'ffinal_TB.vl8n6ttogglepagev_toggle/testbenchodig:1->0htestbench' 0
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C 'ffinal_TB.vl9n7ttogglepagev_toggle/testbenchowalk_left:0->1htestbench' 3
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C 'ffinal_TB.vl9n7ttogglepagev_toggle/testbenchowalk_left:1->0htestbench' 3
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C 'fprob_lemmings4.vl10n9ttogglepagev_toggle/top_moduleoaaah:0->1htestbench.DUT' 3
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C 'fprob_lemmings4.vl10n9ttogglepagev_toggle/top_moduleoaaah:1->0htestbench.DUT' 3
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C 'fprob_lemmings4.vl11n9ttogglepagev_toggle/top_moduleodigging:0->1htestbench.DUT' 0
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C 'fprob_lemmings4.vl11n9ttogglepagev_toggle/top_moduleodigging:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[0]:0->1htestbench.DUT' 0
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[0]:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[1]:0->1htestbench.DUT' 3
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[1]:1->0htestbench.DUT' 2
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[2]:0->1htestbench.DUT' 1
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C 'fprob_lemmings4.vl14n12ttogglepagev_toggle/top_moduleostate[2]:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[0]:0->1htestbench.DUT' 0
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[0]:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[1]:0->1htestbench.DUT' 3
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[1]:1->0htestbench.DUT' 2
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[2]:0->1htestbench.DUT' 1
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C 'fprob_lemmings4.vl15n12ttogglepagev_toggle/top_moduleonext[2]:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[0]:0->1htestbench.DUT' 19
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[0]:1->0htestbench.DUT' 19
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[1]:0->1htestbench.DUT' 10
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[1]:1->0htestbench.DUT' 10
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[2]:0->1htestbench.DUT' 5
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[2]:1->0htestbench.DUT' 5
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[3]:0->1htestbench.DUT' 2
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[3]:1->0htestbench.DUT' 2
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[4]:0->1htestbench.DUT' 2
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C 'fprob_lemmings4.vl17n15ttogglepagev_toggle/top_moduleofall_counter[4]:1->0htestbench.DUT' 2
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C 'fprob_lemmings4.vl19n5tlinepagev_line/top_moduleoblockS19-20htestbench.DUT' 558
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C 'fprob_lemmings4.vl2n8ttogglepagev_toggle/top_moduleoclk:0->1htestbench.DUT' 139
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C 'fprob_lemmings4.vl2n8ttogglepagev_toggle/top_moduleoclk:1->0htestbench.DUT' 139
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C 'fprob_lemmings4.vl21n12texprpagev_expr/top_moduleo(ground==0) => 1htestbench.DUT' 464
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C 'fprob_lemmings4.vl21n12texprpagev_expr/top_moduleo(ground==1) => 0htestbench.DUT' 94
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C 'fprob_lemmings4.vl21n6tlinepagev_line/top_moduleocaseS21htestbench.DUT' 27
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C 'fprob_lemmings4.vl21n8tlinepagev_line/top_moduleoelsifS21htestbench.DUT' 17
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C 'fprob_lemmings4.vl22n10tlinepagev_line/top_moduleoelsifS22htestbench.DUT' 0
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C 'fprob_lemmings4.vl23n10tlinepagev_line/top_moduleoifS23htestbench.DUT' 0
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C 'fprob_lemmings4.vl23n11tlinepagev_line/top_moduleoelseS24htestbench.DUT' 10
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C 'fprob_lemmings4.vl25n6tlinepagev_line/top_moduleocaseS25htestbench.DUT' 0
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C 'fprob_lemmings4.vl26n5tlinepagev_line/top_moduleoelsifS26htestbench.DUT' 0
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C 'fprob_lemmings4.vl26n9texprpagev_expr/top_moduleo(ground==0) => 1htestbench.DUT' 464
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C 'fprob_lemmings4.vl26n9texprpagev_expr/top_moduleo(ground==1) => 0htestbench.DUT' 94
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C 'fprob_lemmings4.vl27n10tlinepagev_line/top_moduleoelsifS27htestbench.DUT' 0
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C 'fprob_lemmings4.vl28n10tlinepagev_line/top_moduleoifS28htestbench.DUT' 0
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C 'fprob_lemmings4.vl28n11tlinepagev_line/top_moduleoelseS29htestbench.DUT' 0
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C 'fprob_lemmings4.vl3n8ttogglepagev_toggle/top_moduleoareset:0->1htestbench.DUT' 1
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C 'fprob_lemmings4.vl3n8ttogglepagev_toggle/top_moduleoareset:1->0htestbench.DUT' 1
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C 'fprob_lemmings4.vl30n18texprpagev_expr/top_moduleo(ground==0) => 0htestbench.DUT' 464
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C 'fprob_lemmings4.vl30n18texprpagev_expr/top_moduleo(ground==1) => 1htestbench.DUT' 94
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C 'fprob_lemmings4.vl30n47tbranchpagev_branch/top_moduleocond_thenS30htestbench.DUT' 9
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C 'fprob_lemmings4.vl30n48tbranchpagev_branch/top_moduleocond_elseS30htestbench.DUT' 151
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C 'fprob_lemmings4.vl30n49tbranchpagev_branch/top_moduleocond_thenS30htestbench.DUT' 3
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C 'fprob_lemmings4.vl30n50tbranchpagev_branch/top_moduleocond_elseS30htestbench.DUT' 6
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C 'fprob_lemmings4.vl30n9tlinepagev_line/top_moduleocaseS30htestbench.DUT' 160
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C 'fprob_lemmings4.vl31n18texprpagev_expr/top_moduleo(ground==0) => 0htestbench.DUT' 464
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C 'fprob_lemmings4.vl31n18texprpagev_expr/top_moduleo(ground==1) => 1htestbench.DUT' 94
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C 'fprob_lemmings4.vl31n47tbranchpagev_branch/top_moduleocond_thenS31htestbench.DUT' 0
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C 'fprob_lemmings4.vl31n48tbranchpagev_branch/top_moduleocond_elseS31htestbench.DUT' 0
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C 'fprob_lemmings4.vl31n49tbranchpagev_branch/top_moduleocond_thenS31htestbench.DUT' 0
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C 'fprob_lemmings4.vl31n50tbranchpagev_branch/top_moduleocond_elseS31htestbench.DUT' 0
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C 'fprob_lemmings4.vl31n9tlinepagev_line/top_moduleocaseS31htestbench.DUT' 0
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C 'fprob_lemmings4.vl32n17texprpagev_expr/top_moduleo(ground==0) => 0htestbench.DUT' 464
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C 'fprob_lemmings4.vl32n17texprpagev_expr/top_moduleo(ground==1) => 1htestbench.DUT' 94
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C 'fprob_lemmings4.vl32n26tbranchpagev_branch/top_moduleocond_thenS32htestbench.DUT' 0
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C 'fprob_lemmings4.vl32n27tbranchpagev_branch/top_moduleocond_elseS32htestbench.DUT' 0
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C 'fprob_lemmings4.vl32n8tlinepagev_line/top_moduleocaseS32htestbench.DUT' 0
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C 'fprob_lemmings4.vl33n17texprpagev_expr/top_moduleo(ground==0) => 0htestbench.DUT' 464
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C 'fprob_lemmings4.vl33n17texprpagev_expr/top_moduleo(ground==1) => 1htestbench.DUT' 94
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C 'fprob_lemmings4.vl33n26tbranchpagev_branch/top_moduleocond_thenS33htestbench.DUT' 0
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C 'fprob_lemmings4.vl33n27tbranchpagev_branch/top_moduleocond_elseS33htestbench.DUT' 0
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C 'fprob_lemmings4.vl33n8tlinepagev_line/top_moduleocaseS33htestbench.DUT' 0
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C 'fprob_lemmings4.vl34n8tlinepagev_line/top_moduleocaseS34htestbench.DUT' 371
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C 'fprob_lemmings4.vl38n5tlinepagev_line/top_moduleoblockS38htestbench.DUT' 140
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C 'fprob_lemmings4.vl39n3tbranchpagev_branch/top_moduleoifS39htestbench.DUT' 3
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C 'fprob_lemmings4.vl39n4tbranchpagev_branch/top_moduleoelseS40htestbench.DUT' 137
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C 'fprob_lemmings4.vl4n8ttogglepagev_toggle/top_moduleobump_left:0->1htestbench.DUT' 4
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C 'fprob_lemmings4.vl4n8ttogglepagev_toggle/top_moduleobump_left:1->0htestbench.DUT' 4
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C 'fprob_lemmings4.vl43n2tlinepagev_line/top_moduleoblockS43htestbench.DUT' 139
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C 'fprob_lemmings4.vl44n22texprpagev_expr/top_moduleo((state == FALLL)==0 && (state == FALLR)==0) => 0htestbench.DUT' 99
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C 'fprob_lemmings4.vl44n22texprpagev_expr/top_moduleo((state == FALLL)==1) => 1htestbench.DUT' 40
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C 'fprob_lemmings4.vl44n22texprpagev_expr/top_moduleo((state == FALLR)==1) => 1htestbench.DUT' 0
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C 'fprob_lemmings4.vl44n3tbranchpagev_branch/top_moduleoifS44htestbench.DUT' 40
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C 'fprob_lemmings4.vl44n4tbranchpagev_branch/top_moduleoelseS49htestbench.DUT' 99
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C 'fprob_lemmings4.vl45n4tbranchpagev_branch/top_moduleoifS45-46htestbench.DUT' 38
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C 'fprob_lemmings4.vl45n5tbranchpagev_branch/top_moduleoelsehtestbench.DUT' 2
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C 'fprob_lemmings4.vl5n8ttogglepagev_toggle/top_moduleobump_right:0->1htestbench.DUT' 4
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C 'fprob_lemmings4.vl5n8ttogglepagev_toggle/top_moduleobump_right:1->0htestbench.DUT' 4
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C 'fprob_lemmings4.vl6n8ttogglepagev_toggle/top_moduleoground:0->1htestbench.DUT' 10
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C 'fprob_lemmings4.vl6n8ttogglepagev_toggle/top_moduleoground:1->0htestbench.DUT' 9
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C 'fprob_lemmings4.vl7n8ttogglepagev_toggle/top_moduleodig:0->1htestbench.DUT' 1
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C 'fprob_lemmings4.vl7n8ttogglepagev_toggle/top_moduleodig:1->0htestbench.DUT' 0
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C 'fprob_lemmings4.vl8n9ttogglepagev_toggle/top_moduleowalk_left:0->1htestbench.DUT' 3
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C 'fprob_lemmings4.vl8n9ttogglepagev_toggle/top_moduleowalk_left:1->0htestbench.DUT' 3
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C 'fprob_lemmings4.vl9n9ttogglepagev_toggle/top_moduleowalk_right:0->1htestbench.DUT' 0
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C 'fprob_lemmings4.vl9n9ttogglepagev_toggle/top_moduleowalk_right:1->0htestbench.DUT' 0
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