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CGA-bench/demo/shift18/1_1_TBgen/TBgen_codes/shift18.v

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2026-05-22 10:02:42 +08:00
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
endmodule