24 lines
1.4 KiB
Plaintext
24 lines
1.4 KiB
Plaintext
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stage 1:
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1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is
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- 1.1. the problem description that guides student to write the RTL code (DUT) and the header of the "DUT".
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- 1.2. the module header.
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- 1.3. the golden RTL codes in verilog. In testbench you should compare the signals from golden RTL and DUT. If not the same, then this DUT fails in the test.
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Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements from the problem description.
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2. you are in section 4. in this section, you will be provided with test scenarios and golden DUT. please highly based on these information to generate the testbench.
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3. In the scenarios testing part, do not directly write the value of expected value, but generate expected value from golden RTL.
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4. your information is:
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your testbench template is:
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[testbench template]
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[problem description from HDLBits]
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[module header]
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IMPORTANT - golden RTL: (please instantiate it in your testbench. Your code should not contain the full code of golden RTL)
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[module code]
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very very IMPORTANT: If all the test cases pass, the testbench should display "all test cases passed". If any one of the test cases fails, testbench should not display "all test caess passed".
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please don't reply other words except the testbench codes.
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[$$TB_code module_code$$]
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