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CGA-bench/.streamlit/temp_config.yaml

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2026-05-22 10:02:42 +08:00
autoline:
TBcheck:
discrim_mode: col_70_wrong_row_25_correct
cga:
enabled: true
max_iter: 10
debug:
max: 3
itermax: 10
probset:
more_info_paths:
- data/HDLBits/HDLBits_data_RTL_4o_20.jsonl
mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl
only:
- mux2to1v
path: data/HDLBits/HDLBits_data.jsonl
promptscript: pychecker
save_compile: false
timeout: 40
update_desc: false
gpt:
model: gpt-4o-2024-08-06
rtlgen_model: gpt-4o-2024-08-06
run:
mode: autoline
save:
en: true
log:
debug_en: false
pub:
prefix: 'NO'
subdir: Main_Results/CorrectBench