345 lines
18 KiB
Plaintext
345 lines
18 KiB
Plaintext
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---------------custom config--------------
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run:
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mode: autoline
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save:
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en: True
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pub:
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prefix: SimpleSPI
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subdir: MyExperimentsSimple
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gpt:
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model: qwen-max
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rtlgen_model: qwen-max
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autoline:
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result_path: results/myproject_simple_spi
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 85.0
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probset:
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path: data/myproject/spi_controller_simple.jsonl
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mutant_path: None
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more_info_paths: []
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only: ['spi_controller_simple']
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promptscript: pychecker
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timeout: 300
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save_compile: False
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debug:
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max: 3
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itermax: 10
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update_desc: False
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TBcheck:
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discrim_mode: col_70_wrong_row_25_correct
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------------------------------------------
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------config info (custom + default)------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: 20260410_184133
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custom_path: config/myproject_simple_spi.yaml
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mode: autoline
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hostname: localhost
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pid: 633505
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pyversion: 3.12.3 (main, Mar 3 2026, 12:15:18) [GCC 13.3.0]
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save:
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en: True
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root: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/
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pub:
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prefix: SimpleSPI
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dir: saves/0406~0412/
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subdir: MyExperimentsSimple/
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: qwen-max
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: qwen-max
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results/myproject_simple_spi
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cga:
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enabled: True
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max_iter: 15
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target_coverage: 85.0
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probset:
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path: data/myproject/spi_controller_simple.jsonl
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['spi_controller_simple']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 3
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: pychecker
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_70_wrong_row_25_correct
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: False
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save_finalcodes: True
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error_interruption: False
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_initialized: True
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------------------------------------------
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--------------default config--------------
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run:
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version: 2.0
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author: Ruidi Qiu - Technical University of Munich
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time: None
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custom_path: None
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mode: qwen-max
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save:
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en: True
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root: None
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pub:
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prefix: None
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dir: saves/$weekrange$/
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subdir:
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log:
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en: True
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dir: logs/
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notes: None
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cfg_pmode: iwantall
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debug_en: False
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level: TRACE
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message:
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en: True
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dir: messages/
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format: json
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iverilog:
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en: True
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subdir: ivcode_nodebug
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load:
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prompt:
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path: config/initial_prompts/prompt1.txt
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pick_idx: []
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stage_template:
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path: config/templates/stage_template0301.txt
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gpt:
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model: 4o
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key_path: config/key_API.json
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temperature: None
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json_mode: False
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chatgpt:
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start_form: chat
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one_time_talk: False
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rtlgen_model: None
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iverilog:
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dir:
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task_id:
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autoline:
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result_path: results
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cga:
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enabled: True
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max_iter: 10
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target_coverage: 100.0
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probset:
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path: None
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mutant_path: None
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gptgenRTL_path: None
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more_info_paths: []
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only: ['lemmings3', 'lemmings4', 'ece241_2013_q8', '2014_q3fsm', 'm2014_q6', 'review2015_fsm', 'rule110', 'fsm_ps2']
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exclude: []
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exclude_json: None
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filter: [{}]
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checklist:
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max: 3
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debug:
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max: 5
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reboot: 1
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py_rollback: 2
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onlyrun: None
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promptscript: None
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timeout: 300
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TBcheck:
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rtl_num: 20
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correct_max: 3
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discrim_mode: col_full_wrong
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correct_mode: naive
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rtl_compens_en: True
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rtl_compens_max_iter: 3
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itermax: 10
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update_desc: False
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save_compile: True
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save_finalcodes: True
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error_interruption: False
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------------------------------------------
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2026-04-10 18:41:33 | INFO | all configurations are loaded, starting the main process...
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2026-04-10 18:41:33 | INFO |
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2026-04-10 18:41:33 | INFO | ######################### task 1/1 [spi_controller_simple] #########################
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2026-04-10 18:42:03 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (30.45s used)
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2026-04-10 18:42:30 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (27.12s used)
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2026-04-10 18:43:34 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (63.70s used)
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2026-04-10 18:44:10 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (35.55s used)
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2026-04-10 18:46:28 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (138.23s used)
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2026-04-10 18:46:28 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used)
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2026-04-10 20:05:32 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (4744.53s used)
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2026-04-10 20:06:16 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (44.08s used)
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2026-04-10 20:06:16 | INFO | [spi_controller_simple]
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2026-04-10 20:06:16 | INFO | [spi_controller_simple] [TBsim] iverilog compilation : passed!
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2026-04-10 20:06:17 | ERROR | [spi_controller_simple] Error when running TBsim, iter: 1. Message: [Errno 2] No such file or directory: 'saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/1_1_TBgen/TBgen_codes/TBout.txt' | location: autoline/TB_autoline.py, func: run_stages_core, line: 361 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317
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2026-04-10 20:06:17 | WARNING | [spi_controller_simple] ⚠️ Pipeline interrupted. Cooling down for 15s to avoid API Rate Limit... | location: autoline/TB_autoline.py, func: run_stages_core, line: 366 | caller: location: autoline/TB_autoline.py, func: run_stages, line: 317
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2026-04-10 20:07:02 | INFO | [spi_controller_simple] [TBgen] stage_0 ends (27.11s used)
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2026-04-10 20:07:31 | INFO | [spi_controller_simple] [TBgen] stage_1 ends (29.45s used)
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2026-04-10 20:08:34 | INFO | [spi_controller_simple] [TBgen] stage_2 ends (62.65s used)
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2026-04-10 20:09:21 | INFO | [spi_controller_simple] [TBgen] stage_3 ends (47.59s used)
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2026-04-10 20:10:56 | INFO | [spi_controller_simple] [TBgen] stage_4 ends (95.11s used)
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2026-04-10 20:10:56 | INFO | [spi_controller_simple] [TBgen] stage_checklist ends (0.00s used)
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2026-04-10 20:25:32 | INFO | [spi_controller_simple] [TBgen] stage_4b ends (875.32s used)
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBgen] stage_5 ends (47.23s used)
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2026-04-10 20:26:19 | INFO | [spi_controller_simple]
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBsim] iverilog compilation : passed!
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBsim] python simulation : passed!
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBsim] TBsim finished : True!
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2026-04-10 20:26:19 | INFO | [spi_controller_simple]
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] rtl list not found, generating naive rtls for testbench checking
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: missing_assignment | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: stuck_at_state | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_bit | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_counter | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_counter | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: invert_single_signal | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: tiny_offset | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: bit_index_shift | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | DEBUG | [spi_controller_simple] Applied mutation: single_bit_flip | location: autoline/rtl_mutator.py, func: _safe_log, line: 33
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] 20 mutation-based RTLs generated (from reference RTL)
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Capturing Reference RTL outputs as ground truth...
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Capturing Reference RTL outputs as ground truth...
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Reference RTL check results: failed scenarios = [1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7], passed scenarios = []
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Captured Reference RTL outputs for 7 scenarios
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Plan 2: Captured outputs for 7 scenarios
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2026-04-10 20:26:19 | INFO | [spi_controller_simple] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination
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2026-04-10 20:26:20 | POSITIVE | [spi_controller_simple] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 0/7
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] [TBcheck] Testbench passed the funccheck
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] [TBcheck] self funccheck finished. Next Action: [pass]
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2026-04-10 20:26:20 | INFO | [spi_controller_simple]
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] [spi_controller_simple] Starting Coverage-Guided Agent (CGA)...
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] [spi_controller_simple] Running Semantic Analysis (Layer 0)...
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] FSM detected: state (4 states)
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] Total function points identified: 8
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] Energy allocator initialized: 8 targets
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] Diversity injector initialized with history file: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/CGA/test_history.json
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] Quality evaluator initialized
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2026-04-10 20:26:20 | INFO | [spi_controller_simple] --- CGA Iter 0 (Baseline) ---
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2026-04-10 20:26:21 | INFO | [spi_controller_simple] Baseline Coverage: 77.55%
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2026-04-10 20:26:21 | INFO | [spi_controller_simple] --- CGA Iter 1 / 15 ---
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2026-04-10 20:26:21 | INFO | [spi_controller_simple] Target: Exception_DefaultCase
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2026-04-10 20:26:21 | INFO | [spi_controller_simple] Asking LLM to fix missing logic (Current: 77.55%)...
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Quality Evaluation: diversity=1.00
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2026-04-10 20:27:11 | SUCCESS | [spi_controller_simple] Coverage Improved! +16.33% (77.55% -> 93.88%)
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Unreachable analysis: 1 truly unreachable, 2 potentially coverable
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Coverage reached target, but found 1 unreachable branches: | location: autoline/TB_cga.py, func: run, line: 1617 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Truly unreachable by RTL design (1 lines): | location: autoline/TB_cga.py, func: run, line: 1619 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Line 93: default: begin - default branch in fully-covered case statement | location: autoline/TB_cga.py, func: run, line: 1619 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Potentially coverable but not tested (2 lines): | location: autoline/TB_cga.py, func: run, line: 1619 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Line 94: state <= IDLE; - potentially coverable but not tested | location: autoline/TB_cga.py, func: run, line: 1619 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Line 95: spi_clk_en <= 1'b0; - potentially coverable but not tested | location: autoline/TB_cga.py, func: run, line: 1619 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Stopping: unreachable branches exist by RTL design
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] CGA Finished. Final Coverage: 93.88%
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Unreachable analysis: 1 truly unreachable, 2 potentially coverable
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2026-04-10 20:27:11 | WARNING | [spi_controller_simple] Unreachable branches found: 1 lines | location: autoline/TB_cga.py, func: run, line: 1636 | caller: location: autoline/TB_autoline.py, func: run_TBCGA, line: 301
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Unreachable branches report saved to: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/CGA/unreachable_branches_report.txt
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Energy report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/CGA/energy_report.txt
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Diversity report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/CGA/diversity_report.txt
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Quality evaluation report saved to saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/CGA/quality_evaluation_report.txt
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Semantic Coverage: 72.02%
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] Saved optimized TB to: saves/0406~0412/MyExperimentsSimple/SimpleSPI_20260410_184133/spi_controller_simple/final_TB.v
|
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking begins
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2026-04-10 20:27:11 | FAILED | [spi_controller_simple] [TBeval] Eval 1: Golden RTL checking failed!
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2026-04-10 20:27:11 | INFO | [spi_controller_simple] [TBeval] [spi_controller_simple] Eval 2/2b is skipped because Eval 1 failed
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2026-04-10 20:27:11 | INFO | [spi_controller_simple]
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2026-04-10 20:27:11 | INFO |
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########## Analyze of Chatbench_RunInfo ##########
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#### pass numbers:
|
||
|
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Eval2 : 0
|
||
|
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Eval1 : 0
|
||
|
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Eval0 : 1
|
||
|
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total : 1 (Failed: 0)
|
||
|
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passed TB by autoline reboot action (from TB3_check): 0
|
||
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|
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|
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passed TB by functional corrector: 0
|
||
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|
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#### CGA Coverage Info:
|
||
|
|
Average Coverage : 93.88%
|
||
|
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Max Coverage : 93.88%
|
||
|
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Min Coverage : 93.88%
|
||
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|
||
|
|
#### tokens and cost:
|
||
|
|
average prompt tokens: 22081
|
||
|
|
average completion tokens: 17022
|
||
|
|
total cost: 1.4629
|
||
|
|
average cost: 1.4629
|
||
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|
||
|
|
#### time:
|
||
|
|
average time: 6337.85s
|
||
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|
||
|
|
#### debug info table:
|
||
|
|
FUNCTIONAL debug info table:
|
||
|
|
(debugged here means functional debugging)
|
||
|
|
| un-func-debugged | func-debugged | total |
|
||
|
|
failed | 0 | 0 | 0 |
|
||
|
|
Eval0 | 0 | 1 | 1 |
|
||
|
|
Eval1 | 0 | 0 | 0 |
|
||
|
|
Eval2 | 0 | 0 | 0 |
|
||
|
|
|
||
|
|
#### Eval2 ratio:
|
||
|
|
|
||
|
|
#### CGA Coverage Detail List:
|
||
|
|
Task ID | Coverage
|
||
|
|
----------------------------------------
|
||
|
|
spi_controller_simple | 93.88%
|
||
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|
|
loose Eval2 pass metric applied: 0.8
|
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