8 lines
16 KiB
Plaintext
8 lines
16 KiB
Plaintext
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{
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"task_id": "sdram_controller",
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"description": "SDRAM Controller with FSM, bank management, refresh, and command sequencing",
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"header": "module sdram_controller (\n input clk,\n input rst_n,\n input [23:0] addr,\n input [15:0] data_in,\n input we,\n input cas,\n input ras,\n input cs_n,\n inputcke,\n input [1:0] dqm,\n output reg [15:0] data_out,\n output reg [12:0] sdram_addr,\n output reg [1:0] ba,\n output reg cs_n_out,\n output reg ras_n_out,\n output reg cas_n_out,\n output reg we_n_out,\n output reg cke_out,\n output reg [1:0] dqm_out,\n output reg busy,\n output reg refresh_req\n);",
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"module_code": "module sdram_controller (\n input clk,\n input rst_n,\n input [23:0] addr,\n input [15:0] data_in,\n input we,\n input cas,\n input ras,\n input cs_n,\n input cke,\n input [1:0] dqm,\n output reg [15:0] data_out,\n output reg [12:0] sdram_addr,\n output reg [1:0] ba,\n output reg cs_n_out,\n output reg ras_n_out,\n output reg cas_n_out,\n output reg we_n_out,\n output reg cke_out,\n output reg [1:0] dqm_out,\n output reg busy,\n output reg refresh_req\n);\n\n // SDRAM Commands (RAS, CAS, WE combinations)\n localparam CMD_NOP = 3'b111,\n CMD_ACTIVE = 3'b011,\n CMD_READ = 3'b101,\n CMD_WRITE = 3'b100,\n CMD_PRECHARGE = 3'b010,\n CMD_REFRESH = 3'b001,\n CMD_LOAD_MODE = 3'b000,\n CMD_BURST_STOP = 3'b110;\n\n // FSM States\n localparam IDLE = 6'd0,\n INIT = 6'd1,\n INIT_PRECHARGE = 6'd2,\n INIT_LOAD_MODE = 6'd3,\n INIT_REFRESH1 = 6'd4,\n INIT_REFRESH2 = 6'd5,\n ACTIVE = 6'd6,\n READ = 6'd7,\n READ_DATA = 6'd8,\n WRITE = 6'd9,\n WRITE_DATA = 6'd10,\n PRECHARGE = 6'd11,\n REFRESH = 6'd12,\n AUTO_REFRESH = 6'd13,\n LOAD_MODE = 6'd14,\n REFRESH_WAIT = 6'd15,\n BURST_STOP = 6'd16,\n POWER_DOWN = 6'd17,\n SELF_REFRESH = 6'd18,\n ERROR = 6'd19;\n\n // Bank states\n reg [3:0] bank_state;\n reg [3:0] bank_open;\n reg [12:0] row_addr [0:3];\n reg [12:0] col_addr;\n reg [1:0] current_bank;\n\n // Timing counters\n reg [4:0] tRC_count;\n reg [3:0] tRCD_count;\n reg [3:0] tRP_count;\n reg [3:0] tWR_count;\n reg [5:0] tRAS_count;\n reg [9:0] refresh_counter;\n reg [3:0] init_count;\n\n // Command generation\n reg [2:0] sdram_cmd;\n reg [12:0] mode_reg;\n\n // FSM state\n reg [5:0] state, next_state;\n reg [5:0] prev_state;\n reg [15:0] data_buf;\n\n // Command assignments\n assign {cs_n_out, ras_n_out, cas_n_out, we_n_out} = sdram_cmd;\n\n // Mode register: BL=2, BT=0, CAS=2, OPMODE=00, AM[2:0]=000\n localparam MODE_REG_VAL = 13'b000_010_0_00_010;\n\n // Timing parameters (clock cycles)\n localparam tRC = 5'd7; // RAS to RAS\n localparam tRCD = 4'd2; // RAS to CAS delay\n localparam tRP = 4'd2; // Precharge to RAS\n localparam tWR = 4'd1; // Write recovery\n localparam tRAS = 5'd5; // RAS active time\n localparam tRFC = 5'd9; // Refresh cycle\n localparam tREFI = 10'd1560; // Refresh interval (1560ns @ 100MHz = 156 cycles)\n\n // FSM: Command generation\n always @(*) begin\n sdram_cmd = CMD_NOP;\n sdram_addr = 13'b0;\n ba = 2'b00;\n cke_out = 1'b1;\n dqm_out = 2'b00;\n\n case (state)\n IDLE: begin\n sdram_cmd = CMD_NOP;\n end\n\n INIT: begin\n sdram_cmd = CMD_NOP;\n end\n\n INIT_PRECHARGE: begin\n sdram_cmd = CMD_PRECHARGE;\n sdram_addr[10] = 1'b1; // All banks\n end\n\n INIT_LOAD_MODE: begin\n sdram_cmd = CMD_LOAD_MODE;\n sdram_addr = MODE_REG_VAL;\n end\n\n INIT_REFRESH1, INIT_REFRESH2, REFRESH, AUTO_REFRESH: begin\n sdram_cmd = CMD_REFRESH;\n end\n\n ACTIVE: begin\n sdram_cmd = CMD_ACTIVE;\n sdram_addr = addr[23:11]; // Row address\n ba = addr[24:23]; // Bank address\n end\n\n READ: begin\n sdram_cmd = CMD_READ;\n sdram_addr = {3'b000, addr[10], addr[9:0]}; // Column with auto-precharge\n ba = addr[24:23];\n dqm_out = 2'b00;\n end\n\n READ_DATA: b
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"testbench": "`timescale 1ns / 1ps\n\nmodule tb_sdram_controller;\n reg clk;\n reg rst_n;\n reg [23:0] addr;\n reg [15:0] data_in;\n reg we;\n reg cas;\n reg ras;\n reg cs_n;\n reg cke;\n reg [1:0] dqm;\n wire [15:0] data_out;\n wire [12:0] sdram_addr;\n wire [1:0] ba;\n wire cs_n_out;\n wire ras_n_out;\n wire cas_n_out;\n wire we_n_out;\n wire cke_out;\n wire [1:0] dqm_out;\n wire busy;\n wire refresh_req;\n\n sdram_controller dut (\n .clk(clk),\n .rst_n(rst_n),\n .addr(addr),\n .data_in(data_in),\n .we(we),\n .cas(cas),\n .ras(ras),\n .cs_n(cs_n),\n .cke(cke),\n .dqm(dqm),\n .data_out(data_out),\n .sdram_addr(sdram_addr),\n .ba(ba),\n .cs_n_out(cs_n_out),\n .ras_n_out(ras_n_out),\n .cas_n_out(cas_n_out),\n .we_n_out(we_n_out),\n .cke_out(cke_out),\n .dqm_out(dqm_out),\n .busy(busy),\n .refresh_req(refresh_req)\n );\n\n always #5 clk = ~clk;\n\n initial begin\n clk = 0;\n rst_n = 0;\n addr = 24'h000000;\n data_in = 16'h0000;\n we = 1;\n cas = 1;\n ras = 1;\n cs_n = 1;\n cke = 0;\n dqm = 2'b00;\n\n #50 rst_n = 1;\n cke = 1;\n #100;\n\n wait(busy == 0);\n\n @(posedge clk);\n addr = 24'h100000;\n data_in = 16'hDEAD;\n we = 0;\n cas = 0;\n ras = 1;\n cs_n = 0;\n #10;\n we = 1;\n cas = 1;\n ras = 1;\n cs_n = 1;\n\n wait(busy == 0);\n #100;\n\n @(posedge clk);\n addr = 24'h100000;\n we = 1;\n cas = 0;\n ras = 1;\n cs_n = 0;\n #10;\n we = 1;\n cas = 1;\n ras = 1;\n cs_n = 1;\n\n wait(busy == 0);\n #500;\n\n @(posedge clk);\n addr = 24'h200000;\n data_in = 16'hBEEF;\n we = 0;\n cas = 0;\n ras = 1;\n cs_n = 0;\n #10;\n we = 1;\n cas = 1;\n ras = 1;\n cs_n = 1;\n\n wait(busy == 0);\n #1000;\n\n $finish;\n end\n\nendmodule"
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}
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